SU1117304A1 - Multi-channel angle-to-digita converter - Google Patents

Abstract

A MULTI-CHANNEL ANGLE-CODE converter containing a reference signal generator, the first output of which is connected to the inputs of sine-cosine rotary transformers, whose outputs are connected to a channel switch, the first operational amplifier, the output of which is connected to the information input of the first sequential approximation register, the second operational amplifier, characterized in that, in order to increase the converter's bite action, a zero potential tire, two digital-to-analog trigonometric multiplier, nine single-oscillators, six AND-NES elements, one inverter and a second register of successive approximations, I1 "is the 1st D1 input of which is an input of the signal of a logic unit of the converter, the output of the first, second, third and fourth most significant bits of the second register of successive approximations through the first , the second, third and fourth one-shot are connected to the first; vsfszhu, the third and fourth inputs of the first NAND element, the output of which is connected to the clock input of the first sequential approximation register and through the fifth one-channel vibrator is connected to the first input of the second NAND element, the output of which is connected to the clock input of the second sequential approximation register, the rest the bits of which through the serially connected third element AND-NOT and the sixth one-shot are connected to the fifth input of the first element AND-NOT and the start you: one to the sixth input of the first element AND-NOT and through the inverter to the first input of the fourth NAND element, the output of which is connected via the seventh one-vibrator to the second input of the second NAND element, the second output of the reference signal generator is connected to the direct input of the second operational amplifier, the inverse input of which is connected to the zero potential bus, and the output, respectively, through the eighth and ninth one-vibrators is connected to the first and second inputs of the fifth NAND element, the output of which is connected to the first input of the sixth AND-NOT element, the output of which is connected to the second input One of the fourth element IS-NOT, CO the second input of the sixth element IS-NOT is the senior input of the converter, the outputs of the channel switch are connected to the analog inputs of the first and second digital-to-analog trigonometric multipliers, to the digital inputs of which are connected the bits of the bits of the first register of successive approximations the outputs of the converter, the outputs of the first and second digital-analog trigonometric multipliers are connected respectively to the inverse and direct inputs of the first operation th amplifier

Description

1 1117 The invention relates to automation and computer technology and can be used in the implementation of angular information input devices in a computer 5 A multichannel angle-code converter containing an information source connected via the commutator to the first input of the analog-to-magnitude conversion unit is known, The output of which 10 is connected to the memory unit, the control unit, one output of which is connected to the control inputs of the switch and the memory unit, and the other output to the second input of the unit is transformed analog value to a code output block memory is connected to a third input it analogous traction value converting unit in 13Nedostatkom code such transducer is a low speed associated with the choice of the servo using the method of converting down counter for generating output code. The closest in technical essence to the present invention is a shaft rotation angle converter into a binary code comprising sinus-sinus rotary transformers connected to the inputs of a channel switch, the outputs of which are connected via paraphase amplifiers to the inputs of a quad switch, one output of which is connected to the first input of the first code converter voltage, the first output of which is connected to the input of the first operational amplifier, the code of the first operational amplifier is connected to the input of the unit with avneni, the output of which the first is connected to the first input registers of. control unit, a synchronization unit, the output of which is connected through a serially connected clock pulse divider and distribution unit to the second input of the control register, whose outputs are connected to the control inputs of the quad switch and the first code-voltage converter, the second and third operational amplifiers, and the second converter code - voltage, the second quad switch code is connected to the input of the second operational amplifier, the output of which is connected to the input of the second code-to-converter The first output 04 of which is connected to the input of the second operational amplifier, the second outputs of the first and second code-voltage converters are connected to the input of the third operational amplifier, the outputs of the second and third operational amplifiers connected to the inputs of the comparison unit, the control output-output register is connected to To the control input of the second converter, code-voltage 21. A disadvantage of the known converter is also a low speed, which is associated with the selection of BORN, which are equal in duration to the clock The content of the output code bits for the E code of the bit-coded coding and the presence of delays in the paraphase amplifiers and the switch of the quadrants. The purpose of the invention is to increase the speed of the multi-channel angle-code converter. The goal is achieved by the fact that in a multi-channel angle-code converter containing a reference signal generator, the first output of which is connected to the inputs of a sine-cosine rotary transformer is a transformer, whose outputs are connected to a channel switch, the first operational amplifier, whose code is under-connected to the information input of the first register of successive approximations, the second operational amplifier, the zero potential is introduced, two digital-analogue trigonometric multipliers 5 nine one vibrate oa, six IS-NOT elements, one inverter and the second register of successive approximations, whose information input is the input of the signal of a logical unit of the converter, the output of the first, second, third and fourth high bits of the second register of successive approximations through the first second, third and a quarter one-shot is connected to the first, second, third and fourth inputs of the first NAND element, the output of which is connected to the clock input of the first-order register of successive approximations and through the five A subconnector is connected to the first input of the second NAND element, the output of which is connected to the clock input of the second sequential approximation register, the outputs of the remaining 3 bits of which are connected through the serially connected third AND NAND element and the sixth one-vibrator to the NAND and the starting output is to the sixth input of the first NAND element and through the inverter to the first input of the fourth NAND element, the output of which is connected to the second input of the second NAND element through the seventh one-VIB, the second generator output and the reference signal is connected to the direct input of the second operational amplifier, the inverse input of which is connected to the zero potential bus, and the output via the eighth and ninth one-oscillators, respectively, is connected to the first and second inputs of the fifth NAND element, the output of which is connected to the first input of the sixth element AND-NOT, the output of which is connected to the second input of the fourth element AND-NOT, the second input of the eleventh element AND-NOT is the starting input of the converter, the outputs of the channel switch are connected to the analog inputs of the first first and second digital-analogue trigonometric multipliers; the digital inputs of which are connected to the bits of the first register of the sequential first register of successive approximations, which are the outputs of the converter; the outputs of the first and second digital-analogue trigonometric multipliers are connected respectively to the inverse and direct inputs of the first operational amplifier . FIG. 1 is a block diagram of a multichannel angle-code converter; in fig. 2 - the table of transitions of the register of successive approximations; in fig. 3 is a block diagram of a four-square digital-analog trigonometric multiplier. The converter contains a two-phase generator 1 of the reference signal, sine-cosine rotating transformers 2, a 3-channel switch, four-square digital-to-analog trigonometric multipliers 4, the first operational amplifier 5, the first register 6 of successive approximations, the second operational amplifier 7, the single-vibration 8-14, 23 and 24, second register 15 successive approximations, first 16, second 1 third 18, fourth 19, fifth 5 and 0D4 sixth 21 elements AND-NOT, inverter 22 multiplying the digital-to-analog converter (DAC) 25, constant e memorize Miee device (ROM) 26, operational amplifiers (opamps) 27 and 28, resistors 29-31. The Converter operates as follows. Generator 1 produces two reference harmonic signals that are shifted relative to each other by 90 °, one of which is powered by sine-cosine rotating transformers 2 (Fig. 1). A controlled 3-channel switcher connects the outputs of the selected bluetooth-cosine rotary transformer to the analog inputs of four-square digital-analog trigonometric multipliers 4 that multiply the analog signals sinuJt and COS & sin cot to digital codes of signals cos W and sin ×, respectively (9 - ANGLE of shaft rotation; U) t is the phase of the power signal. H is the digital equivalent of the compensating angle). At the output of the operational amplifier 5, the error signal is generated, the corresponding log. Oh, if sip (S-), sinu) t L U, and log. 1, if sin (6-4) .x sinwt AU, where the dead band of the operational amplifier 5 is to change the input signals, determines the resolution of the converter. The logic level from the output of the amplifier 5 is fed to the information input of the register 6 of successive approximations, the functions of which are to form a certain sequence of codes at the clock input at their outputs with simultaneous recording in each of the clock signals from the information input to the output bits from high to low. . The operation of the sequential approximation register is explained in the transition table in FIG. 2 (155IP17-12 standard bit register of successive approximations). The table shows that when a first pulse arrives at the clock input, a code 01 ... 1 is formed, which corresponds to an angle-code angle W 180 ° in the converter. Depending on the magnitude of the angle S, a logic level is formed in the code of the amplifier 5, which, when the second clock pulse arrives, is written to the high register bit 6. At the same time, the output code D ,, 01 ... 1, corresponding to the angle converter code (depending on the value of the angle if 90 or 4. The result of the comparison @ is formed at the output of the amplifier 5 and is recorded in the third clock in the next most significant bit and so on. In the thirteenth clock at the output of the register 6 it turns out to be 12 bit code, corresponding to at the starting output of the register it appears as a log level O indicating the end of the conversion cycle. The next cycle can be started after the start pulse is applied, causing the next series of clock signals. The conversion accuracy can be achieved as much as possible when the measurement cycle is executed the highest amplitude of the power supply signal, and also provided that the conversion cycle time is insignificant with respect to the period Ji / u; signal powering. The signal of the beginning of the transformation and, therefore, the transformation itself can occur twice during the period 2Jr / to of the power signal, in its positive and negative phases. In order to increase the accuracy and simplify synchronization of the moment of the start of the conversion, the reference signal generator 1 is two-phase. The reference signal of the second phase (coswt) is fed to the operational amplifier 10, which fixes positive and negative values of the power supply signal (sinujt) by changing the logic level at its output. The conversion delay includes two components: t. ,, is the switch time of DAC 25 keys in total with the code sample time in ROM 26 (FIG. 3), and also t (U) is the rise time of analog signals in OS 27 and 28 and in the operational amplifier 5. The first component t is not related to the size of the switched signals, while the second t (U) depends directly on them: tf, (U) e U, where d is the ramp up rate (the characteristic of the by-function of an op-amp in the large-signal mode), a and „is the largest value of the signals switched in the nth cycle. The time of one clock cycle T can be represented as In accordance with the bitwise encoding principle, the value of Un in each subsequent clock is half as long as in the previous one, i.e. Uj c, etc., therefore the shortest time T "required for a full cycle of transformation, is: and (and ,,, - yi, c .. ..-, In order to fulfill this equality in the proposed converter, clock pulses are formed variable duration, set by one-shot 8-12, one-shot 8-11, 13, 14 and 23 on a negative front, pulse a zero logical level, one-shot 12 and 24 on a positive front, pulse a zero logical level. amplifier 7 at the output of one of the one-shot 23 or 24, a zero-level pulse is generated, the output of the other one-shot at this time is maintained at level 1. At the output of element 20, the IS-NOT generated pulse is inverted, and when it coincides with the start pulse of a single logical level, through the elements 19 it does NOT start with its negative Front, the one-shot 14, the pulse from which through the element 18 AND-NOT arrives at the clock input of the second register 15 successive approximations. In accordance with the table in FIG. 2, a log is generated in the high order register 15. A. A single-shot 8 on the negative edge of the high-order signal produces a clock pulse, the duration of which T. is set by the output signal duration of the one-shot 8 minimum required to determine the high-order code: the output cell of the 16 AND-NO element is a clock of a single logical level of not-fynaeT the clock input of the first register is 6 consecutive approximations of the SERII and at the end of its negative front starts the one-shot 13 (the pulse of which through the element 18 X-NOT goes to the clock input of the register 15. V The next higher output bit of the register 15 is formed by the log.O, to which the one-shot 9 reacts, the clock pulse from the output of which has the duration minimally necessary for determining the next bit of the code: T, At the end of the second clock pulse, one breaker is formed the third clock pulse with duration of CL- 1/4 behind it with the single vibrator 11 is formed a quarter pulse with duration. + (th clock pulses from the fifth to the last have the same duration T5 lfn, slightly exceeding t how many aktike delay value t (and) U | bj much less than m. The contribution to the total delay is very small. At the end of the cycle, in accordance with the table in FIG. 2, at the starting output of its register 15, a log is generated. About, preparing the register 6 for the next cycle and opening through the inverter 22 element 21 AND-NOT to pass the next starting pulse from the output of element 19 AND-NOT, Setting the log. 1 at the information input D of the register 15 provides the required order of forming logs. the levels at the outputs of register 15. The ability to arbitrarily set the duration of the pulses produced by single-oscillators allows one to form a sequence of pulses of pulse O9, which ensure the minimum conversion delay. The technical and economic efficiency of the proposed converter is to increase its speed while simultaneously narrowing the range of elements used in comparison with the known converters.

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Claims (1)

MULTI-CHANNEL CORNER CONVERTER, containing a reference signal generator, the first output of which is connected to the inputs of the sine-cosine rotary transformers, the outputs of which are connected to the channel switch, the first operational amplifier, the output of which is connected to the information input of the first register of successive approximations, the second operational amplifier, different the fact that, in order to increase the speed of the converter, a zero-potential bus, two digital-analog trigonometric transients are introduced into it a knife, nine one-shots, six NAND elements, one inverter and a second register of successive approximations, the information input of which is an input of a signal of a logical unit of the converter, the output of the first, second, third and fourth senior bits of the second register of successive approximations through the first, second, third and the fourth one-shot connected to the first; the second, third and fourth inputs of the first AND-NOT element, the output of which is connected to the clock input of the first sequential approximation register and through the fifth one-shot is connected to the first input of the second AND-NOT element, whose output is connected to the clock input of the second sequential approximation register, the outputs of the remaining bits which through series-connected the third AND-NOT element and the sixth single-vibrator are connected to the fifth input of the first AND-ΗΕζ element and the start output to the sixth input of the first AND-NOT element and through 3 inverter to the first input of the fourth AND-NOT element, the output of which through the seventh one-shot is connected to the second input of the second AND-NOT element, the second output of the reference signal generator is connected to the direct input of the second operational amplifier, the inverse input of which is connected to the zero potential bus, and the output respectively, through the eighth and ninth single vibrators connected to the first and second inputs of the fifth AND-NOT element, the output of which is connected to the first input of the sixth AND-NOT element, the output of which is connected to the second input of the fourth AND-NOT element, the second input of the sixth AND-NOT element is the senior input of the converter, the channel switch outputs are connected to the analog inputs of the first and second digital-analog trigonometric multipliers, the digital inputs of which are connected to the outputs of the bits of the first register of successive approximations, which are the outputs of the converter, the outputs of the first and the second digits of the analog trigonometric multipliers are connected respectively to the inverse and direct inputs of the first operational amplifier