SU1115047A2 - Calculating device - Google Patents

Abstract

COMPUTER DEVICE according to author. St. No. 1086426, characterized in that, in order to extend the functionality by calculating the quotient of dividing the sum of squares by one number, (S-1) additional matrixes of And elements are entered into the device (S is the number of numbers being built in. Square of numbers), the first inputs Elements And j-ro column of the g-th additional matrix (r-1, ..., S-1) are connected to the input of the j-ro bit (r + 2) -th operand of the device, the second input of the p-th element And j The -ro column of the rth additional matrix is connected to the input of the (j + 1) -ro bit of the (r + 2) -th operand of the device, the output of the q-ro element of the E, E-hundred The edge of the gth additional matrix is connected to the (r + 3) th input of the (q-H) -th th bit of the (B + 1) -th adder. (/) WITH

Description

4 41 The invention relates to computing and can be accepted as a special processor in a complex with a digital computer or in specialized computing devices for the operational computation of a group operation ZxVz. According to the main-auth. No. 1086426 known computing device containing (n-1) adders (n-bit operands), (n-1) switch groups, the first group of elements AND, the first group of elements OR, the first information input of the i-ro switch j-th the group (, ..., p-1,., .., p) is connected to the input of the i-ro bit of the first operand of the device, the first input of the K-th bit, (j-ro adderTk 2, ..., n + 1; 6 1, ..., p-2) is connected to the output of (K-1) -th bit (+ 1) -th adder, as well as the matrix of elements AND, the n-th adder, a group of elements NOT, group of adders modulo two, the second groups of elements AND, OR, p The output of the j-th switch of the j-th group (, ..., n + 1) is connected to the first input of the corresponding modulo-two of the corresponding group, the outputs of the i-ro element OR of the first group and (il) -ro element AND of the first group the groups are connected to the i-ro outputs of the device, the control inputs of the j-th switchboards are connected to the output of the (j + 1) -ro element of the second group, the second information input of the K-th switch of the j-th group is connected by the input of K- 1st bit of the first operand of the device second inputs of modulo adders two j-th groups are connected to the output of the (j + 1) -ro element OR the second group and the first input of the first bit of the j-ro adder, the outputs of the adders modulo two j-th groups are connected to the second inputs of the corresponding bits of the j-ro adder, the first inputs of the elements And the j-ro column of the matrix are connected to the input of the j-ro bit of the second operand of the device, the second input of the pth element AND the j-ro column of the matrix (, ..., nj) is connected to the input (j + 10th bit of the second one rand of the device, output of the q-ro element 2 th matrix column (, ..., p-) is connected to the third input (q + 1) -ro bit (8 + 1) -th adder, the bit inputs of the first operand of the device through the corresponding elements of the NOT group are connected to the first inputs of the corresponding bits of the n-th adder, the second inputs of the n-th and (n-2) -th bits of the n-th adder are connected to the inputs of the n-th and (n-1.) th bits of the second operand of the device, respectively, the second input of the first bit of the n-th adder is connected to the bus unit potential of the device, the output of the element AND (p-1) of the matrix column is connected to the third input of the n-th digit of the adder, the third input the first bit of the first totalizer is connected to the input of the first bit of the second operand of the device Naturally, the first input of each element OR of the first group is connected to the output of the corresponding modulo adder two pth groups, the second input of the 1st element OR of the first group is connected to the first transfer output (il) -ro adder, the first input of the i-ro adder module two of the i-th group and the first input of the i-ro element And the first group is connected to the output of the (i + 1) -ro element AND of the second group, the second input of the i-ro modulo two i-th group, the second input of the i-ro element of the first group and the first input of the i-ro element OR of the second group is connected to the second transfer output of the i-ro adder a, the second input of each element OR of the second group is connected to the output of the corresponding element OR of the first group, the first input of the i-element of the AND element of the second group is connected to the output of the corresponding element of the first group of the first group, and the second input is connected to the output of the subtotal -th bit (i-1) -th adder G The disadvantage of the known device is the limited functionality due to the fact that it is impossible to calculate the type of xV / Z. The aim of the invention is to extend the functionality of the device by calculating the quotient from dividing the sum of squares by one number. The goal is achieved by introducing (S-1) additional matrices of elements AND (S is the number of squares of numbers), and the first inputs of the AND j-ro column of the rth additional matrix (, 2, .. ., S-1) are connected to the input of the j-ro bit (r + 2) -th operand of the device, the second input of the p-th element And the j-ro column of the z-th additional matrix is connected to the input (j + 1) - ro bit (g + 2) -th operand of the device output q-ro element And t-th column of the g-th additional matrix is connected to (g + 3) -th input (q + 1) -ro bit (+1) th adder. The drawing shows a diagram of the proposed computing device for the case when,. The device contains adders 1, switches 2 groups, a matrix of elements And 3, adders 4 modulo two of the first and second groups, elements NOT 5 groups, elements OR 6 of the first group, elements AND 7 of the first group, elements AND 8 of the second group, elements OR 9 second group, adders 10 modulo two third groups, additional matrices of elements 11 and 12, inputs 13 of the first operand, inputs 14 of the second operand, inputs 15 of the third operand, inputs 16 of the fourth operand, outputs 17, bus 18 of a single potential and bus 19 zero potential. The work of the group operation processor that implements the implementation of the C + C + C + ... + X | - + .. dependency. + X | r2 0 presented in the form f X ..... 4Xj ..... 47 4 and recorded in the bit form VV / V LT / VVX, X + ... ajXj ... tXgXg-ZoE, 0 . (2) Let us explain in a concrete example where the bit vectors are bit images of the numbers XV, ot, 0; / bit matrices representing the bit image of the numbers XI and Z, respectively, with n 3. Let us write the expansion (2) in expanded form for the case when, and.

Denote in expression (3) the vectors

x;

0

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where is the value of the transfer from the highest bit of the vector l, determined on the basis of expressions. Each i-th bit (, 2, ..., n) of the desired vector ot is determined by 1; O P, 2,3 ,, .., n, (4) x -.... (i) g ;; (|:; i). v «) Cx (.2 (x; L .... v (a, p (2). (, (srv (3, v (| v (a), v (; p (H, :( H ( v ,, v ,, j, p (,, a value that takes on the value when., О When implementing the calculations in accordance with (4) - (6), one of two cases is also possible. If, in the first realization of the hyphenation (5) accordingly, (4) it turned out, that is C О C O, and in the subsequent implementation of (5) (i.e., 1), the transfer value from the highest bit in expression (5) of the vector, (i + 1) iO -i / v (iH) v (itij v (i4i | SA 2 K + l t -...-- l is one, then it is assumed that W 1 and the computational process proceeds as in (4) - (6). If, as a result, i- ro calculator by the expression of 1, and during the subsequent (i + DM by calculation by expression (5) the vector v,) -. | J (H.) vOH) jUH) j Longer or equal to twice the vector Z, i.e. the inequality is fulfilled., (7) then the next ( 5) is realized with, doubled vector l,, the value of оС is considered to be equal to zero ОЫ, and the value of ot 1 is added 1. In fact, the value of the i-th bit ot of vector c is represented in the binary redundant number system, i.e. o (. can take the values 0, 1, 2. The criterion for the second case or the 1st implementation of expressions (4) - (6) is based on the following: оС g the value of the highest bit of the vector S must also be equal to one if equal the highest bit of the vector Z. In this case, if the transfer value from the high bit of 7 "and the vector is equal to one, then at Oj-.C 1 is accepted, and the computational process continues according to (4) - (6). as follows: When applying to the inputs 13 values of bits Z, Z, ..., of the vector and to the inputs 14-16, respectively X, X, X, X X | and Xj, X |, X vectors X ,, X ,, and X are temporarily discharged in the device at the output of the nth adder fo expression (5) forms a vector that enters at the second adder 1, and at the output of the higher-order carryover of adder 1 and, respectively, at the output 17, the value of the higher-order bit bb of the desired vector ° C is formed. Then, the input of the second adder 1 is received V (2.1 Xd and Ze, in which (5) a vector is formed, and at the output of the high-order bit transfer it is a zero or single signal, which, in accordance with (4) is steps onto output 17. Similarly, the inputs of the third, second, and first adders 1 post (2) subsume, respectively, the vectors X; Ze, in accordance with expressions (4) - (6) at the output of the transfer of the first adder 1 and, accordingly, at the output 17, the discharge value of the desired vector d is formed. If the output 17 is the value, and the output of the higher-order transfer of the subsequent CW of Mat 1 produces a single signal, then it enters the output of 17, i.e. in this case, oi 1. If a single signal d 1 was formed at the output 17, and an intermediate signal at the output of the intermediate sum of the high bit (il) -ro is also a single signal, then in this case, a single signal is formed at the corresponding output 17, due to to which the outflow (5) in (1-1) -th adder 1 is realized with the doubled vector Z. At the same time, at the output of the higher-order carry (i-l) -ro of the adder 1, a single signal is generated, which arrives at the output 17. Then the computational process proceeds similarly in accordance with (4) -Cb). The use of additional matrices of elements And, as well as new connections between them, allows, in contrast to the known device, in which 7 only the value is calculated, in the proposed device to calculate the quotient from dividing the sum of squares

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Claims (1)

COMPUTER DEVICE by ed. St. No. 1086426, with the fact that, in order to expand functionality by calculating the quotient of dividing the sum of squares by one number, (S-1) additional matrixes of elements And (S - the number of squared numbers), and the first inputs of the AND elements of the j-ro column of the rth additional matrix (r-1, S-1) are connected to the input of the j-ro discharge of the (r + 2) -th device operand ^ the second the input of the rth element AND of the j-ro column of the rth additional matrix is connected to the input of the (j + Τ) -th category of the (g + 2) -th operand of the device, the output of the q-ro element of And, Е -th hundred The column of the rth additional matrix is connected to the (r + 3) -th input of the (q + 1) -th discharge of the (8 + 1) -th adder. I 1115047 2