SU1102037A1 - Multichannel device for coding information by product codes - Google Patents

Abstract

MULTI-CHANNEL INFORMATION ENCODING CODING DEVICE, containing in each channel a switch, the first input of which is connected to the input of the channel, and the first output is connected to the input of the external code encoder, as well as connected in series the internal code encoder, ring shift register and unequal element, the output of which is connected with the output of the device, the synchronization unit, whose INPUT is connected, is connected to the control input of the ring shift register and the second inputs of the switches of all channels, characterized by then, in order to improve the functionality and simplify the device, the multiplexers of the internal and external code, the priority control block, and the buffer register of the internal code, whose input is connected to the second output of the switch, and the binary code of the external code are entered into it. ,: the first and second inputs of which are connected respectively to the output of the external code encoder and the third output of the switch, and the outputs of the buffer registers of the internal code of each channel are connected to the corresponding inputs of the mule an internal code multiplexer whose output is connected to the input of the internal code encoder, while the I outputs of the buffer codes of the outer code of each channel are connected to (L the corresponding inputs of the multiplexer of the outdoor code whose output is connected to the second input of the inequality element, the fourth outputs of the switches of each channel are connected to respective inputs of the priority control unit, the first and second outputs of which are connected respectively to the input of the synchronization unit and to the control input of the multiplex pa vneschnego code as E9 sync block output is connected to the gate of the multiplexer departures external code rloka priority control and buffer registers vieschnego yseh code channels.

Description

The invention relates to a pulse technique and can be used in digital information transmission systems. A device for encoding information by nonlinear Draft codes on a uniform, equal two degree, containing the first and second memory devices and a modulo two adder, the outputs of the first and second memory devices are connected to the input of a modulo two adder, the output of which is connected to the input of the second storage device and the output of the coding device C J The disadvantage of such a device is that it allows coding information by Plotkin codes having a dimension equal to the power of two, whereas the codes Pl SCID may be defined matrices. Hadamard of any dimension, multiple chetrem, The closest technical solution to the invention is an information encoding device with Plotkin codes containing a switch in each channel, the first input of which is connected to the input of the channel, and the first output is connected to the input of the external code encoder, and also connected in series internal code, ring shift register and inequality element, the output of which is connected to the output of the device, the synchronization unit, the output of which is connected to the control input of the ring register Shift stratum and second switch inputs of all L2 channels. A disadvantage of the known device is that it allows coding information by product codes only on the basis of Hadamard matrices of multiple dimensions. The use of this encoder in a multichannel encoder leads to significant hardware costs. The purpose of the invention is to enhance the functionality and simplify the device. The goal is achieved by the fact that in a multi-channel device for encoding information by product codes, there is a switch in each channel, the first input of which is connected to the channel input, and the first output is connected to the input of the external code encoder, as well as connected in series | ring (the shift register and the unequal element 7 house device, the synchronization unit, the output of which is connected to the control input of the ring shift register and the second inputs of the switches of all channels, introduced multiplexers inside An external and external code, a priority control block, and in each channel, an internal code buffer register, whose input is connected to the second switch output, and an external code buffer register, the first and second inputs of which are connected to the external encoder code and the third switch output, the outputs of the buffer registers of the internal code of each channel are connected to the corresponding inputs of the multiplexer of the internal code, output. which is connected to the internal code inode, while the outputs of the buffer registers of the external code of each channel are connected to the corresponding inputs of the external code multiplexer, the output of which is connected to the second input of the unequalities element, the fourth outputs of the switches of each channel are connected to the corresponding inputs of the priority control block, the first and second outputs which are connected respectively to the input of the synchronization unit and the control input of the external code multiplexer, and the output of the synchronization unit connected to the control inputs of the external code multiplexer, priority control block and buffer registers of the external code of all channels. . FIG. 1 shows a block diagram of the device, FIG. 2-time diagram of his work. Each channel 1 of a multichannel information-encoding device with product codes contains a switch 2, the first output of which is connected to the input of the external code encoder 3, the output of which is connected to the first input of the buffer register 4 of the external code. The second and third outputs of the switch 2 are connected respectively to the input of the buffer register 5 of the internal code and the second input of the buffer register 4 of the external code, and the fourth inputs of the switches 2 of all channels 1 are connected to the corresponding inputs of the priority control unit 6. Buffer outputs. The internal code registers 5 are connected to the corresponding inputs of the internal code multiplexer 7, the output of which is connected to the input of the internal code encoder 8, the output of which is connected to the parallel recording input of the ring shift register 9, the output of which is connected to the first input of the inequality element 10. The outputs of the buffer register 4 external code connected to the corresponding inputs of the multiplexer 11 external code, the output of which is connected to the second input of the unequal element. The first and second outputs of the priority control unit 6 are connected to the input of the synchronization unit 12 and the control input of the external code multiplexer 11. The input 13 of each channel 1 is connected to the first input of the switch 2, while the second inputs of the switches 2 and the control inputs of the priority block 6. Whose control, multiplexer 7 internal code and ring shift register 9 are connected to the output of synchronization unit 12. The output of the element 10 inequality is connected to the output 14 of the device. The operation of the device is based on the following principles. If the vector 1 1 belongs to the external code, and the vector belongs to the internal code, then “Ktor O, ... . ; will be of dimension n and will be a sequence of n vectors V, on position x, where / tu is f a O, and inversions of V stock vectors, where a 1. Here the symbol means addition modulo two. . The code thus generated is called the product code of the original vectors. Vector 2 belonging to the internal code is given by the Hadamard matrix Hf,. The vector Vv belonging to the outer code is given by the coefficients of the cyclic systematic polynomial (n, m) code f (x), which is formed as follows. on; The polynomial a (x), the corresponding -digit combination of a redundant one, is multiplied by x, where. The artwork a (x) x is divided into a basic polynomial of a cyclic code (x) of degree- k. In the general case of division, we obtain some frequent q (x). the same degree as a (x) is the remainder of g (x), the degree of which does not revise k-1. The polynomial f (x) of cyclic systematic (n, m) code corresponding to the input combination (x) is formed by the formula f (x) a (x) x fg (x). The device functions as follows. In the initial pemiMe, all buffer registers 4 and 5 and the ring shift register 9 are cleared; at the input of the priority control block 6, there are no applications. Let the sources start typing informational sequences arriving at the inputs of the corresponding channels 1. The formation of external and internal codes in the channels occurs in the same type. For definiteness, we assume that the intensity of the sources is the same. Let the information come to the input of the device in the following order a, a, a- .... The switch 2 of channel 1 splits the information sequence a ,, coming at its input 13 into two parts of length and m, respectively. The first part of the sequence, log &n; n, is written to the buffer register 5 of the internal code. The second part of length t, containing information about the state of the object and its address, is fed to the external code encoder 3, which is a (n-m) -discharge feedback register (n is the total number of characters of the external code, m is the number of informational simsol). For m clock cycles in such a registrator, the formation of (n-m) check symbols occurs, which are written into the n-bit buffer register 4, followed by the information symbols "Synchronization of encoder 3 and buffer registers 4 and 5 are performed by switch 2. Arrived. the later sequence a is similarly prepared in its channel. It came even later after-. condemnation a. also begins to prepare in his channel. At the end of Iog2n2 + n clock register 5, the internal code is recorded in the first part of the message and in the register 4 in the outer code the cyclic systematic (n, m) code is recorded, which is the external code of the output code-product, the signal on the service is given to the priority control unit 6 the first channel 1. Since block 6 is free, it performs dynamic priority service of the first incoming request from channel a, while block 6 connects the output of buffer register 4 of the external code of the first channel through mu tipleksor vneshneto -code 11 to the second input element 1 nonequivalence unit 12 and starts sinhronizaschta. The synchronization unit 12 feeds the internal code to the encoder 8 through the internal code multiplexer 7 of the internal code buffer register 5, with which one of the n code words is matched to the encoder 8, is rewritten into the ring shift register 9. Upon completion of the formation of the internal code symbols in the ring shift register 9, the synchronization unit 12 resets the switch 2 of the first channel 1, thereby preparing it to receive new information, and starts pushing out the external code 11 characters of the external code from the buffer register 4 the second input of the element 10 is unequal. During the time each of the n external code symbols is located at the second input of the element 10, the internal code of length n in the ring register 9 is shifted by the pulses of the synchronization unit 12 by n positions and at the first input. element 10, connected to the output of the ring register 9, the symbols of the inner code appear in series. After n shifts in the ring register 9, the word of the internal code will again take up its original position. On the non-unique element 10, the product code vector is calculated by the formula (1). After the formation of the product code is completed, the synchronization unit 12 removes the served channel charge a- from the corresponding input of the priority control block b. Let during the service time of the channel a external codes be formed that put the channels for servicing in block 6. At this, a queue of the form was formed: After the php cycles, the synchronization unit 12 generates a signal that removes the service from channel a, and the priority control unit 6 goes to service the next queue for channel a. In this case, the state of the queue becomes the following:.-F, where F is the empty place in the queue corresponding to the served channel a. The service is similar. After servicing the channel a, the synchronization unit 12 generates a signal that removes its application and the unit 6 proceeds to processing the application from channel a ,. In this case, the state of the queue was: a,.,. F, F. The further operation of the device is that the information from the sources enters its channels, where it is encoded with an external code. In this case, the priority control unit 6 forms a queue of prepared messages. The message, which occupies the first place in the queue, is served by the internal code encoder 8. Then there is a shift in the queue by one position. In the future, the process proceeds similarly. Consider the operation of the device described in the following example. Let the number of serviced sources be three. Each source generates a sequence of pulses of length 6. Let the device receive information as follows: a, -2 use the Plotkin code specified by the Hadamard matrix H as the internal code. Then, the information sequence of the length log, n 2 . The coding of the internal code will be performed according to the rule:. 00-1111 01-1010 10-1100 11-1001

Let the cyclic systematic code (7,4) with the constituent polynomial g (x) x + X + 1 be used as the outer code. Let the information sequence of the first source a- be the next 11,100, Then the information is the sequence of the inner code, given the switch 2 of the first channel to the buffer register 5 of the internal code, and through the multiplexer 7 of the internal code to the input of the encoder 8 of the internal code, will be next 11. At the output of the encoder 8, the internal code code vector is 1001. The information code of the external code is 1001. Here, the two right bits define the source address code according to the rule:

1 source - 01

 - ten

 - eleven

In the buffer register 4 of the outer code, the outer code is formed - 1001 011 (according to the formula (2)). The code vectors of the component codes are fed to the inputs of the unequal element 10 and a vector product appears at its output (according to formula (1)).

0110 1001 1001 0110 1001

0110-0110

Let the third source's information sequence be the next: 111111, then the output of the internal code encoder 8 is 1100, the external code is generated in the buffer register 4 of the third external code channel 1111 111. Then the vector production will be as follows

0011 OOP 0011 0011 0011

0011 0011

Let the information sequence of the second source a-j be 010110, then on

The output of the internal code encoder 8 is in accordance with the Wits code vector of the internal code - 1010, and in the buffer register 4 of the second channel of the external code, the external code is formed - 0110 100. Then the product vector will be as follows

1010. 0101 0101 1010 0101 1010 1010

This example is illustrated by a timing diagram (Fig. 2), where the signals in the first (a-d), second (e-k) and third (l-n) channels are indicated.

. at the following points: a, e, l - the input of channel 1, b, w, m - the input of the buffer

register 5 of the internal code, c, z, n the input of the coder 3 of the external code, g, and, o the input of the buffer register 4 of the external code, d, k, n, is the fourth output of switch 2; p is the output of the ring register 9 shift; s is the output of the external code multiplexer 11, t is the output 14 of the device.

In a multichannel device, the coding information expands the functionality by coding information and work codes, using Plotkin code of any dimension multiple of four as the internal code, and cyclic systematic (n, m) code for the internal code less hardware costs.

In the known device hardware

j costs are equal to ni + n, where n and A2 are the length of the code vectors of the outer and inner codes, respectively. In this device, the hardware costs for each channel are approximately

g

П2 + Пд + 1 (п + 10§2П2) will be t

where p and P2 are the length of the code vectors of the outer and inner codes, respectively, 1 is the number of channels.

Claims (1)

MULTI-CHANNEL INFORMATION CODING DEVICE CODES-PROFILE 3 DETAILS, containing in each channel a switch, the first input of which is connected to the channel input, and the first output is connected to the input of the external code encoder, as well as the internal code encoder connected in series, the ring shift register and the unequal element, the output of which connected to the output of the device, the synchronization unit, the output of which is connected to the control input of the circular shift register and the second inputs of the switches of all channels, characterized in that In order to expand the functionality and simplify the device, it includes internal and external code multiplexers, a priority control unit, and a buffer register of the internal code, the input of which is connected to the second output of the switch, and a buffer register of the external code, the first and second the inputs of which are connected respectively with the output of the external code encoder and the third output of the switch, and the outputs of the buffer registers of the internal code of each channel are connected to the corresponding inputs of the multiplexer the early code, the output of which is connected to the input of the encoder of the internal code, while the outputs of the buffer registers of the external code of each channel are connected to the corresponding inputs of the multiplexer of the external code ', the output of which is connected to the second input of the disambiguation element, the fourth outputs of the switches of each channel are connected to the corresponding inputs of the priority block control, the first and second. the outputs of which are connected respectively to the input of the synchronization unit and the control input of the external code multiplexer, and the output of the unit with nhronizatsii connected to control multiplexer departures external code _(priority control unit and Bu; open source code registers SU .... 1102037 channels.