SU1101836A1 - Device for executing fast fourier transform - Google Patents

Abstract

A FURIER FAST TRANSFORMATION DEVICE containing an input register of numbers, an input register of a weighting factor whose information inputs are device inputs, a multiplying unit, a component register, an adder, four result registers and a control unit, characterized in that, in order to reduce hardware costs, an OR element is entered into it, and the control unit consists of a clock generator, a clock counter, an AND element, a NOT element, and a memory block, while the output of the digital bits of the weight coefficient register The input is connected to the digital bits of the first input of the multiplying block, the output of the sign bit of the weight coefficient register is connected to the first input of the EXCLUSIVE OR element, the output of which is connected to the sign bit of the first input of the multiplying block, the second input of which is connected to the output of the input number register, the output of the multiplying unit is connected to the information input of the register of the components, the inverse output of which is connected to the first information input of the adder, the output of which is connected to the information inputs four result registers, the outputs of which are combined and connected to the output of the device and to the second information input of the adder, the output of the clock generator of the control unit is connected to the counting input of the clock counter, the bit outputs of which are connected to the address inputs of the memory block, the output of the first digit of the counter cycles connected to the input of the input (L register of the items, the output of the second bit of the counter of cycles is connected to the input of the element NOT, the output of which is connected to the first input of the element I, S the output of which is connected with the input of the clock counter in O, the outputs of the third and fourth bits of which are connected to the second and third inputs of the AND element, the outputs of the first group of the memory block are connected to the inputs of the input number register, the input from the register of the weighting factor, the register (35 country with and registers of results, respectively, the outputs of the second group of the memory block are connected to the inputs of the result registers, respectively, the output of the third group of the memory block is connected to the input of the O register of the weighting factor nta and with the second input element EXCLUSIVE OR, the outputs of the fourth group of the memory block are connected to the control inputs of the adder.

Description

1 The invention relates to computing and can be used in constructing a device that implements the Fast Fourier Transform (VPF) algorithm. A device that performs operations with complex numbers is known. The device contains the registers of the real and imaginary parts of the factors, the compilers of the serial works, the combinational-accumulating summers, the translation unit into the additional code lj. However, this device requires a large amount of equipment. The closest to the invention to the technical essence is a device for fast Fourier transform, containing four input registers of numbers and two input registers of weight coefficient, the inputs of which are the inputs of the device multiplication unit, adder, addendum commutator, commutator commutator, two addendum registers, even registers of works and a control unit, the first input of which is connected to the control input of the commutator of the terms, the second one - with the control input of the commutator commutator, the outputs of the registers weight The new coefficient is connected to the first two information inputs of the commutator switch, the outputs of which are connected to the inputs of the multiplying block, all of which are connected to the output AND of the work registers, the outputs of which are connected to the first four information inputs of the switch are composed of 1) 1x, the other four information inputs of which are connected to the outputs input registers- numbers, the outputs of the addendum of the addends are connected to the inputs of the adder, the output of which is connected to the output of the device not by the inputs of the registers of the addends, passages which are connected to third and fourth data inputs of the register N. factors. A disadvantage of the known device is the high cost of equipment. In addition, the disadvantages include the presence of multiple inputs, which requires memory parallelization, and this, in turn, leads to an increase in external communications and addressing complexity or the need to install a data distributor at the device input. The aim of the invention is to reduce hardware costs and the number of external links. The goal is achieved in that a device for fast Fourier transform containing an input register of numbers, an input weight register, whose information inputs are device inputs, a multiplier unit, a sum register, an adder, four result registers and a control unit, is entered EXCLUSIVE OR, and the control unit consists of a clock generator, a four-bit clock counter, an AND element, a NOT element, and a microprogram memory block, while the output of the digit bits of the registers is and the weighting factor is connected to the digital bits of the first input of the multiplying block, the output of the sign bit of the weighting register is connected to the first input of the EXCLUSIVE OR element, the output of which is connected to the sign: the bit of the first input of the multiplying block, the second input of which is connected to the output of the input number register , the output of the multiplying unit is connected to the information input of the register of the components, the inverse output of which is connected to the first information input of the adder, the output of which is connected to the information By the inputs of four results registers, the outputs of which are combined and connected to the output of the device and to the second information input of the adder, the output of the clock generator of the control unit is connected to the counting input of the clock counter, the outputs of the bits of which are connected to the address inputs of the memory block, the output of the first yes the clock counter is connected to the input of the registers of the addends, the output of the second stage and the clock counter is connected to the input of the element NOT, the output of which is connected to the first input of the element I, the output of which is soy Inen with the input to the O clock counter, the outputs of the second and fourth bits of which are connected to the second and third strokes of the AND element, the outputs of the first group of the memory block are connected to the corresponding inputs of the input of the input register of the weighting factor, the register of the terms and the result registers , the outputs of the second group of the memory block are connected to the inputs of the result registers, respectively, the output of the third group of the memory block is connected to the input of the installation in O of the input register of the weighting factor and from the second The input element is TEMPTING OR, the outputs of the fourth group of the memory block are connected to the control inputs of the adder. FIG. 1 shows a block diagram of a device for fast Fourier transform in FIG. 2 is a block diagram of the control unit; in fig. 3 is a timing diagram illustrating the operation of devices a, in FIG. 4 is a block diagram of the operation of the control unit. The device for fast Fourier transform contains an input register of 1 numbers, whose input is the first input of the device, and the output is connected to the first input of the multiplying unit 2, the digital discharge of the second input of the duplicating unit 2 is connected to the digital discharge of the weighing unit factor coefficient, the input of which is the second input of the device. In this case, the output of the sign bit of register 3 of the weight coefficient is connected to the first input of the EXCLUSIVE OR 4 element, the output of which is connected to the input of the sign bit of the second input of the multiplying unit 2. The output of the multiplying unit 2 is connected to the information input of the register 5 the output of which is connected to the first information input of the adder 6. The output of the adder 6 is connected to the information inputs of four registers 7-10 of the results, the outputs of which are combined and connected to the second input of the adder 6 and to the output of its device. The outputs of the control unit 11 are connected to the control inputs of all the registers (1,3,5, 7f10), the bis adder to the second input element EXCLUSIVE OR 4. The adder 6 is a cooler with advanced functionality. It is required that it executes the following Three operations: Alignment, subtraction and omission of one, from operands unchanged. Directly combining the outputs of registers is permissible if registers with three states at the output are used as these registers. The control unit 11 may be implemented, for example, as shown in FIG. 2. It contains a generator of 12 clock pulses, a counter of 13 clocks, a memory block 14, element 15, an element of NOT 16, the generator output 12 connected to the counter input of a four-bit counter 13 clocks, the outputs connected to the corresponding inputs of the microprogram memory block 14 of the memory. In addition, the output of the first (low) bit of the 13-beat counter is the output 17 of the control unit and connected to the input of the register 5 of the addend, the output of the second discharge of the 13-beat counter is connected to the input of the HE element 16, the output of which is connected to the first input of the AND element 15. The outputs of the third and fourth bits of the counter 13 cycles are connected respectively to the second and third inputs of the element 15, the output of which is connected to the input of the installation in About the counter 13 cycles. The outputs of the memory block 14 are the outputs 18t-30 of the control unit 11, the output 18 is connected to the receiving input of the register of 1 numbers, the output 19 is connected to the receiving input of the weight register 3, outputs 20723 are connected to the receive of the result registers 7-10, respectively and outputs 24-727, respectively, to the control inputs for issuing information of the same registers 77-10. The codes 28 and 29 are connected to the control inputs, executed by the operation of the adder 6, the output 30 is connected to the second input of the EXTRACTOR element OR 4, and to the installation input in the register 3 of the weighting factor. FIG. 4a and 46, the following conventions are accepted:, i-j - i-th cycle, j-th - semi-cycle {C - result at the output of adder 6, FFT - time of the result of the transformation indicating what kind of result is given; Pr1 - input register of 1 numbers; PRL - input register 3 weighting factor; Pr5 - register 5 terms; Pr77Rg10 - registers 7-710 results, MO - the result of the output of the copying unit. 5 The device performs the basic operation of the fast Fzfier algorithm for a base of 2 A; 8, C, -W;,., 6, -C-. 8eA; Re8, + l eC-ReW -l, C ;. tmftrIvnB; ReC, -I W4i C; -ReW PieA -, - Re8-ReC; -ReWni C; -I W; n.H imBrReC ... where B, C are reference samples, A-, are converted samples; W is a CELLULAR coefficient, W e, - j t N is the number of samples in the original array; Re ... is the real part of the number; the imaginary part of the number. Consider the operation of the device when performing the basic operation. We will assume that the reception of information in the registers is carried out at the time of the arrival of the falling edge, the sync pulse. The device works with additional codes of numbers. From the external memory, the weight coefficients W are inverted, i.e. (W4-1)) o Information on the first input of the adder is taken from the inverse outputs of the register of 5 terms. The third input of the youngest bit of the adder 6 (transfer input) is permanently connected to the signal corresponding to the presence of transfer, i.e. 1. At the end of the first clock cycle, according to the signal from the output 18 of the control unit 11, the real part ReC j of the initial counting C is received in the input register 1 of numbers, and the input signal 19 is received in the input register 3 of the weighting factor. the ReW part of the weight coefficient W In the second cycle, multiplication is performed in duplication unit 2 and according to the signal output 17. At the end of the cycle, the ReC ReW output is received in register 5. The output signal 19 in 3 receives the imaginary part of the weight coefficient W. In the third clock cycle, the duplicate block 2 is executed; multiplication and product rec. 1, y1 W, the signal from output 17 is received in register 5 of the terms. The adder 6, by signals from outputs 28 and 29, performs skipping of the first operand and, in register 7, by signal from output 20, it receives a 36 ReC output.; - ReW. In the input register 1 numbers signal c. output 18, the real part ReBi of the original reference B is received. In the fourth clock cycle in multiplication unit 2, the real part ReBj of the initial reference B | per unit and unchanged by the signal from output 17 is taken to register 5. Multiplication by one is performed by the signal from output 30, which sets the contents of register 3 to O, and the value of the sign bit inverts. That is, the number 1.00 is given as a multiplier. .. About, when multiplying by which the product is equal to the multiplicand. The adder 6, by signals from outputs 28 and 29, skips the first operand and, in register 8, results by signal from output 21, the product ReC is received. In input register 1 by signal from output 18, the imaginary part 1 of the initial sampling timeframe in the duplicate block is received 2, multiplication of I hl Bi unit is performed and, according to the signal from the output 1 7 1, B, is received in register 5. In the input register 1, the signal from the output 18 receives the imaginary part I C, of the initial count C. In register 3 of the weighting factor according to the signal from exit 19, the imaginary part 1 V of the weighting coefficient U is taken. By the signal from output 24 from register .7, the product ReCjReW is drawn. In addition, in the first half of the fifth cycle, the adder 6 performs the subtraction operation and in the middle of the clock, by the signal from the output 22, the difference ReBj-ReC is received in register 9. ReW In the second half of the fifth cycle of the adder 6, according to the signals from outputs 28 and 29, it performs the addition operation and at the end of the clock cycle from the signal from output 20, the sum ReB j-1-ReC ;. ReW is received in register 7. In the sixth cycle in multiplication block 2, multiplication is performed and the product of the signal from output 17 is received in register 5, in the input register 3 of the weighting factor, signal from output 19 is received, the ReW part of the weighting factor W. 8 according to the output signal, 25 the product ReCj-l W appears. In addition. in the first half of the sixth clock cycle, the adder 6 performs the subtraction operation from the signals from the outputs 28 and 29, and a difference is received in the middle of the clock to the register 10 from the signal from the output 23. . In the second half of the clock, the adder 6 performs the addition operation and at the end of the clock, the output from 21 to register 8 receives the sum of 1 B -ReCi. In the seventh cycle in multiplication block 2, multiplication is performed and the product is received from the output 17 signal into register 5. The ReW input register 1 is taken as the real part of the ReC of the original count. In the input register 3 is accepted the real part of the ReW BecoBoro coefficient i In addition, in the first half of the sf of the tact from the output 24, the contents of the register 7 ReB- + ReC- ReW The adder 6 performs the subtraction operation from the signals from outputs 28 and 29, and the real part ReAj ReB- is received into register 7 mid-clock by the signal from output 20. Re. I-w. On the second half of the seventh clock cycle, a signal from the output of 26. Out of register 9, ReBj-ReC is output -. I-eW, the adder 6 performs the addition operation and at the end of the clock, the signal from output 22 to register 9 takes the real part ReA:;, ReBj -ReC x y ReW%. In the eighth cycle in the copying block. 2, the multiplication and the product of ReC are performed. a signal from output 17 registers 5; an input register 3 receives an imaginary signal from output 19: input ImW of the weight coefficient W In addition, in the first half of the eighth clock cycle from register 10, a signal from output 27 is output 1 "B-ReC; The adder 6, according to the signals from the outputs 28 and 29, performs the subtraction operation and in the middle of the clock, the signal from the output 23 to the register 10 is assumed to be imaginary, hour 1 ", A ;,, -ReC; .y-.T-, ReW second half of the eighth clock cycle out of 68 register 8, a ReC signal is output from a signal from output 25. , the adder 6 performs the addition operation and the signal from the output 21 to the register 8 receives the imaginary part 1..A; IB-ReC, -.-ReW. In the ninth bar in multiplication block 2, multiplication and the product of ReC are performed. the signal from output 17 is received into register 5. the terms, the adder 6, by signals from outputs 28 and 29, skips the nepBqro operand, the product ReC; and ReW from the signal from output 20 is received into register 7. In input register 1, the real part of of reference B ,. . In addition, in the first half of the ninth clock cycle from register 7, the output of the system at the signal from output 24 is issued ReAj. In the second half of the ninth clock cycle, a signal from output 25 to the output of the device is given the imaginary part 3 "A ;. In the tenth cycle in multiplication unit 2, the real part is multiplied by the unit and, according to the signal from output 17, is received in register 5, and in input register 1, according to the signal from output 18, imaginary part 1 8 is received; reference readings in. In addition, in the first half of the tenth clock cycle, a valid ReA part is output from the signal from output 26 of register 9, and in the second half of the tenth clock cycle, an imaginary part ip 1 + 1 is output to the device from the output signal 27 the entire device is similar. Thus, in comparison with the known device, the proposed device with the same performance has five registers and two adders less. In addition, the known device has six inputs, whereas the proposed device has only two, which significantly reduces the number of external connections and allows working with linear memory.

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Claims (1)

DEVICE FOR FAST FOURIER TRANSFORM, containing an input register of numbers, an input register of a weight coefficient, information inputs of which are device inputs, a multiplier block, a register of terms, an adder, four result registers and a control block, characterized in that, in order to reduce hardware costs, an OR element is introduced to it, and the control unit consists of a clock generator, a clock counter, an AND element, an NOT element, and a memory unit, while the output of the digital bits of the weight register it is single with the digital digits of the first input of the multiplying unit, the output of the sign discharge of the weight register is connected to the first input of the EXCLUSIVE OR element, the output of which is connected to the sign of the first input of the multiplying unit, the second input of which is connected to the output of the input register of numbers, the output of the multiplying unit is connected to information input of the register of terms, the inverse output of which is connected to the first information input of the adder, the output of which is connected to the information inputs of four register Of the results, the outputs of which are combined and connected to the output of the device and to the second information input of the adder, the output of the clock generator of the control unit is connected to the counting input of the clock counter, the bit outputs of which are connected to the address inputs of the memory block, the output of the first bit of the clock counter is $ S with the input of the reception of the register of terms, the output of the second bit of the clock counter is connected to the input of the element NOT, the output of which is connected to the first input of the element And, the output of which is connected to the input of the set to 0 a clock tick whose outputs of the third and fourth digits are connected to the second and third inputs of the AND element, the outputs of the first group of the memory block are connected to the inputs of the input input register of numbers, the input register of the weight coefficient, the register of terms and the registers of results, respectively, the outputs of the second group of the memory block are connected to inputs of the output of the registers of results, respectively, the output of the third group of the memory block is connected to the input of the input in the input register of the weight coefficient and to the second input of the element EXCLUSIVELY OR the outputs of the fourth group of the storage unit connected to the control inputs of the adder.