SU1092517A1 - Programmable processor for spectral processing of signals - Google Patents

Description

the memory, the nepBOio information input of the buffer register is connected to the third output of the communication switch with the interface, the information outputs of the registers of the second group are connected to the information input of the second arithmetic unit, the shift control inputs are connected to the corresponding control outputs of the microprogram memory node group.

The invention relates to computing and can be used in computing systems and digital signal processing devices. A programmable spectral signal processing processor is known, which contains a register block, an arithmetic logic unit, a multiplication unit, a random access memory unit, a communication unit with an interface interconnected by a bus, a control unit Cl. The disadvantage of this processor is low that data is exchanged between all blocks on a single bidirectional trunk, i.e. the efficiency of loading individual blocks is relatively low. The closest in technical essence to the invention is a programmable processor for spectral signal processing, which comprises the first arithmetic logic unit, the first input of which is connected to the first inputs of the first register through the first highway and the multiplication unit. a block of registers and a multiplier and with the second input of the first arithmetic logic unit, a memory block of constants, a memory block, the output connected through the second line with: first and input and output of the communication unit and the interface, the second input and whose output are the input and Yield of the processor respectively. To enable execution of algorithms for spectral signal processing, this processor additionally contains an addressing index block, a coordinate conversion block, and a synchronization block. Data and microinstructions are exchanged via three C 21 trunks. When performing the basic operation of the Fast Fourier Transform FFT algorithm, the first arithmetic logic unit, the first register block, the multiplication unit, the memory block, the constant memory block, the first, and the second are used. and a third of the highway. When performing the averaging algorithm, a drive, a RAM unit, a second and a third line are used. When performing the coordinate transformation algorithm, the coordinate transformation block is used, as well as the second and third arrays. Thus, in view of the fact that all three highways during the execution of these algorithms are almost always loaded, it is impossible to combine the implementation of these algorithms in time by processor blocks, i.e. loading of these blocks is characterized by low efficiency. The program and processing, constants and data in the processor are in the same memory area formed by the memory block of constants and the memory block, the outputs connected to one second main. This area is addressed to the same addressing index block, hence the impossibility of combining micro-instructions, sampling constants, and data sampling in time for sampling and decoding of micro-instructions. Besides; the microinstruction sampling signal travels a long way from the control unit through the first and third lines to the addressing index block, i.e. loads two trunks at once. The transfers between the first arithmetic logic unit, the first block of registers and the multiplication unit are performed one at a time (first (the main line, so it is impossible to parallelize the execution of operations in the multiplication unit and in the first arithmetic logic unit). Consequently, the disadvantage of this processor is low performance with relatively the greatest hardware cost. The purpose of the invention is to increase the speed of the processor. The goal is achieved by having a processor of spectral processing; 1 signals containing the first arithmetic unit, the information output of which is connected to the information inputs of the registers of the first group and the first information input of the multiplication unit, the information output of which is connected to the information outputs of the registers of the first group and connected to the information input of the first arithmetic unit, a communication switch with the interface, the first input of which is connected to the information output of the memory unit, the second input and the first output of the communication switch with the interface are respectively and The information input and the information output of the processor, the Permanent Memory block, whose information output is connected to the second information input of the multiplication unit, the control block consisting of the addressing node and the microprogram memory node, the information output of which is connected to the input of the next address of the addressing node, the input the sign of which is the input of the sign of the control unit, the output of the addressing node is connected to the address input of the microprogram memory node, the outputs of the group of bits which are connected to the control inputs with The nepBo arithmetic unit, the registers of the first group and the multiplication unit, respectively, contains the shifter, the first and second buffer registers, the second arithmetic unit, the second group of registers, the program memory and the addressing unit, the output of which is connected to the address input of the program memory, information the output of which is connected to the input of the next address of the addressing block, the control input of the second arithmetic block, the information input of the second arithmetic block, the input of setting the starting address of the addressing node b control location, clock inputs of the second group of registers and the control input of the communication switch with the interface, the second output of which is connected to the installation input of the starting address of the addressing block, the input of the conditional transition flag of which is connected to the output of the calculation end of the second arithmetic block, the information output of which is connected to the information the inputs of registers of the second group with 1 input of the memory block and the block of the permanent memory, the first input of the communication switch with the interface and the information input of the first the first buffer register, the information output of which is combined with the information outputs of the shifter and connected to the information input of the first arithmetic unit, the information output of which is connected to the information inputs of the shift and information input of the second buffer register, whose information output is connected to the information input of the block , the information input of the first buffer register is connected to the third output of the communication switch with the interface, the information outputs of the registers of the second group with connected to the information input of the second arithmetic unit, the control inputs of the gate are connected to the corresponding inputs. control units of the evil group of the memory of the microprogram of the control unit. FIG. 1 shows a block diagram of a processor; in fig. 2 is a flowchart of an algorithm for calculating an address sequence for transforming coordinates; in fig. 3 is a block diagram of an algorithm for computing an address sequence of averaging; in fig. 4: averaging flowchart; in fig. 5 is a block diagram of the algorithm for digital signal processing. The programmable spectral signal processing processor contains an arithmetic unit 1, highway 2, a group of registers 3, multiplication unit 4, a control unit 5, a block of permanent memory (constants) 6, 6J7OK (main memory 7, highway 8, a communication switch with an interface 9, input 10 and processor output 11, respectively, shifter 12, buffer register 13, highway 14, buffer register 15, program memory block 16, output 17 of block 16, arithmetic block 18, register group 19, addressing block 20, block output 21 18, input 22 (input of the installation of the initial address of the program} address 20, input 23 (conditional transition flag). The programmable spectral signal processor operates as follows: Block 1, group of registers 3, multiplier 4 and shifter 12 under Bd by the action of control signals from control unit 5, exchanging as operands through highways 2 and 14, perform one of the elementary operations, such as the basic operation of the FFT algorithm, the averaging operation, the coordinate transformation operation, and others. The code of this operation enters the control unit 5 from the output 17 of the program memory block 16. The processed arrays of operands are stored in memory block 7, read from it and through trunk 8 and the buffer register 13 enter trunk 2 and then into blocks 1, 3, 4, 12, where they are processed according to the algorithm of a given elementary operation. The results of this operation from trunk 14 via buffer register 15 are written to memory block 7. Constants required for performing elementary operation are stored in memory block 6 of constants, from where they are output to trunk 14. Addresses for memory block 6 of constants and block 7, the RAM is received from the output 21 of the unit 18. Initial data from the input 10 of the processor is fed to the switch 9 of communication with the interface through its input and then from its output through the main 8 is written to the RAM 7. The processing results are read out from the RAM block 7 and through the trunk 8 arrive at the input of the switch 9 of communication with the interface, from the output of which are output to the output 11 of the processor. From the output 17 of the program memory block 16, the control information is fed to the input of the communication switch 9 with the interface. From the output of the communication switch 9 with the interface to the input 22 of the addressing unit 21, the starting address of the spectral signal processing programs is supplied.

In program memory block 16, spectral signal processing programs are stored. Each such program contains a sequence of processing commands according to one or another signal-processing algorithm. The command field contains the code of the elementary operation which, via output 17 of block 16, enters the control unit 5, as well as the address code of the subroutine for calculating straight sequences, which is fed to the first input of the addressing unit 20. Subroutines for calculating the address sequences are stored in the same memory block 16 programs. Microprograms of subroutines in block 18 and register group 19 compute the addresses of operands, results and coefficients that go to bus 2, while from block 16 to the input of block 18 the constants are received, which is necessary when calculating the width sequence.

On one command, the processor performs one cycle of computations, for example, one iteration of the FFT algorithm, the averaging cycle, or the coordinate transformation cycle of the operands of the array stored in the operational memory block 7. The number of elementary operations in the cycle is equal to the number of N operands in the array. The control unit i, having received an elementary operation code from the bus 17, outputs control signals to blocks 1, 3, 4 and 12, which are repeatedly executed in these blocks. given an elementary operation until a new elementary operation code arrives from block 16. At the same time, block 18 and register group 19 according to the subprogram calculate the sequence a, cres operands, results and constants involved in the calculation of the elementary operation, and the calculation time for one elementary operation is equal to the time for calculating the addresses for the next elementary operation. to determine the end of the subroutine in one of the registers of the register group 19, the number of elementary operations is counted. Upon reaching a predetermined number of elementary operations, the output unit 18 outputs a signal to the input 23 of the 20s1 block of the Dresser, which returns from the subroutines and the following command is selected from the program memory 16. At that time, when 1-elementary operation is calculated in blocks 1, 3, 4, and 12, the basic data for 1 +, 1st elementary operation and from buffer register 15 are read into block 1 from the RAM block 7. 7, the memory of the i-1st elementary operation is recorded.

Thus, the processor combines in time the determination of addresses of operands, results and constants, accesses memory block 7, accesses constants memory block 6 and directly calculates the elementary operation by blocks 1,3, 4, 5 and 12, which allows you to load all the blocks of the processor and get high performance. Performing various elementary operations with the same set of blocks of 1, 3, 4, 5, 7 and 12 roses. It is necessary to refuse the use of a coordinate conversion unit and an accumulation unit, which simplifies the processor and reduces hardware costs.

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Claims (1)

A PROGRAMMABLE SPECTRAL SIGNAL PROCESSING PROCESSOR, comprising a first arithmetic unit, the information output of which is connected to the information inputs of the registers of the first group and the first information input of the multiplication unit, the information output of which is connected to the information outputs of the registers of the first group and connected to the information input of the first arithmetic unit, with an interface, the first input of which is connected to the information output of the memory unit, the second input and the first output of the switch with ides with an interface are respectively an information input and an information output of a processor, a read-only memory unit, the information output of which is connected to a second information input of a multiplication unit, a control unit consisting of an addressing unit and a microprogram memory unit, the information output of which is connected to the input of the next address of the addressing unit, the input of the feature of which is the input of the feature of the control unit, the output of the addressing node is connected to the address input of the microprogram memory node, the outputs of the group of bits They are connected to the control inputs of the first arithmetic block, the registers of the first group and the multiplication block, characterized in that, in order to increase the processor speed, it contains a shifter, the first and second buffer registers, the second arithmetic block, the second group of registers, the program memory block and the addressing unit, the output of which is connected to the address input of the program memory block, the information output of which is connected to the input of the next address of the addressing unit, the control input of the second arithmetic unit, the information input of the second arithmetic unit, the input of the installation of the starting address of the addressing unit of the control unit, the clock inputs of the registers and the control input of communication with the interface, which is connected to the group of the second switch 5, the second output {installation input. the starting address of the addressing block, the input of the conditional transition sign · which is connected to the output of the end of the calculation of the second arithmetic block, the information output of which is! it is connected to the information inputs of the registers of the second group, the address inputs of the memory block and the read-only memory block, the first input of the communication switch with the interface and the information input of the first buffer; register, the information output of which is combined with the information outputs of the shifter and connected to the information input of the first arithmetic block, the information output of which is connected to the information inputs of the shifter and the information input of the second buffer register, the information output of which is connected to the information input of the block> memory, the information input of the first buffer register is connected to the third output of the communication switch with the interface, the information outputs of the registers of the second group are connected to the information input of the second arithmetic unit, the control inputs of the shift of the body are connected to the corresponding control outputs of the group of the memory unit of the microprogram of the control unit.