SU1088016A1 - Multiplying-dividing device - Google Patents

Abstract

A MULTIPLE-EFFICIENT DEVICE, containing the first and second keys, whose copies are pushed to the integrator input, the output of which the memory unit is connected to the inputs of the third and fourth keys, the output of the third key is connected to the integrator input, the phase controller is spacing into the time interval The input of which is the input of the first signal-multiplier device, the output of the clue of the right key is connected to the output of the fifth key, the input of which is connected to the input of the first key and is the input of the second signal-multiplier device tva, the input of the second key is the input signalE of the device divider, accumulating an adder, the output of which is the output of the device, the synchronization unit, the first output of which is connected to the control input of the voltage amp in the time taggervap, the second, the third , the fourth and fifth outputs of the synchronous block. The control inputs are, respectively, connected to the memory unit, the third to the fourth keys and the accumulating adder, characterized in that, in order to improve accuracy. It includes the sixth and seventh CL1OCHIs, the first and second elements AND, the inverter, the trigger, the first, second and third de-multiplexers, the voltage converter into the code, the memory retractor and the code converter into the time interval, the integrator entering through the sixth and seventh keys with a zero potential bus, the output of the trigger through the inverter is connected to the first input of the first element I, the code of which is connected to the control input of the memory register, with an additional control to the input of the adder and with the first | the input of the second element is And, the second input of which is connected to the code of the pr & (About the voltage generator in the time interval and to the information input of the first demultiplexer, the first and second outputs of which are connected respectively to the control inputs of the first and sixth kilograms, the output of the second element I is connected to the control input of the fifth key, the output of the fourth key is connected with the input of the voltage pre-phaser in the code, the output of the non-dripping adder through the memory register O) is connected to the input of the code converter in the time interval, whose Kitxoa is connected to the information input ffcoporo demulti the plexer, the first and second outputs of which are connected respectively to the control inputs of the second and seventh keys, the output of the voltage converter into the code is connected to the information input of the third demultiplexer, the first, second and second outputs of which are connected respectively to the direct and inverse inputs of the accumulating sum

Description

motor, trigger output soicinen with control inputs of the first, second and third cement types, sixth, seventh and eighth outputs of the synchronization unit are connected to the trigger input of the first And element and to the control input of the code converter into the time interval respectively.

The invention relates to electrical computing devices and can be used in analog and analog-digital computing machines.  A multiplying device is known which holds a voltage-to-time converter, keys, an integrator, a memory unit and a control unit l.  This device does not implement the operation method, which is a disadvantage.  Closest to the invention is a multiplying-healing device containing a voltage converter in a time interval, the first and second outputs of which are connected to the controllers of the first and second keys, the input of the voltage converter in the time interval is the input of the first signal multiplier, The second signal factor Vl1pots connected inputs of ps and second keys, the input of the signal separator are the input of the third key output of the first connected to the outputs of the third and fourth keys and the integrator input, the output of which is connected to the input of the memory unit, the output of which is connected to the input of the nsrro key and the input of the large-scale converter, the output of which is connected to the input of the fourth key, the outputs of the second and fifth keys are connected to the input of the integrating converter in pulse duration , the first output of which is connected to the control input of the third key, the second output of the integrating converter is connected to the first input of the accumulating torus sum, the output of which is The device output, synchronization unit, the first, second, third, fourth, fifth and sixth outputs of which are connected respectively to the control input of the voltage converter in the time interval, with the control input of the fourth key, with the control input of the fifth key, with the control at the input of the integrating voltage converter in the pulse duration and with the second input of the accumulator adder {2}, the error of the known device depends on the duration of the integration intervals and, therefore, from the current values s input n emeshshth.  The aim of the invention is to increase the accuracy of work.  With this circuit, a multiplier device containing the first and second switches, the outputs of which are connected to the input integrate), the output of which through the memory unit is connected to the inputs of the third and fourth, the output of the third switch is connected to the input of the integrator, the interval whose input is the input of the first signal multiplier of the device, the output of the fourth key is connected to the output of the fifth key, the input of which is connected to the input of the first key and is the input of the second signal multiplier In this case, the input of the second key is the input of the device's signal-divider, accumulating the adder, the output of which is the output of the device, the synchronization unit, the first output of which is connected to the control input of the voltage converter in the time interval, second, third, fourth and fifth the synchronization unit is connected to the control inputs of the memory unit, the third and fourth keys and the accumulating adder, respectively; the sixth and seventh keys are entered, the first and second elements are AND, the inverter, trigger, first, second second and third demuptipleksory, voltage converter to the code, the register memory and preobrazovatep koaa time-IVGervap, wherein vhots integrator via the sixth and seventh kpyuchi soetsinen with zero potential bus vyhots latch through an inverter poschkshochen to the first input of the first AND gate, which vyhots connected with the memory register control input, with the additional input of the accumulator and with the first input of the second element, and the second input of which is connected to the output of the voltage converter in the time domain and to the information inlet of the first demo typexor, the first and second outputs of which are connected respectively with the ynpaBnsno inputs of the first and sixth keys, the output of the second element AND is connected to the control input of the fifth key, the output of the fourth key is connected to the input of the voltage converter into the code, the output of the accumulator through the memory register is connected to the input of the code generator in the time interval, the output of which is connected to the information input of the second demultipexor, the first and second of which are connected to Respectively to the control inputs in the horn and seventh keys, the output of the voltage pre-phaser code is connected to the information input of the third demo luminaire, the first and second outputs of which are connected respectively to the direct and inverse inputs of the accumulating adder, the output of the trigger is connected to the control inputs of the first , and the third demo-plexers, the sixth, seventh and eighth outputs of the synchronization unit are connected respectively to the counting input of the trigger, to the second input of the first element And and to the control input eaten code in the time interval.  FIG.  1 shows the functional on the scheme of the multiplier-separating device, on which the variant of the possible is presented. performing an onizashas blue block; in fig.  2 - timing charts of control signals.  The proposed device contains a voltage converter 1 at a time interval, an integrator 2, a memory block 3, first, second, third, fourth and fifth keys 4-8, an accumulating adder 9, a block 10 of synchronization, sixth and seventh keys 11 and 12, the first, second, and third demultiplexers 13–15, register 16 memories.  10 64 converter 17 codes into a time interval, voltage converter 18 into a code, trigger 19, first and second elements 20 and 21, inverter 22, inputs of the first and second multiplier signals and divider 23-25 and output 26 of the device, 27 generator pulses, the first and second counters 28 And 29, the first and second decoders 30 and 31, the first, second, third and fourth pulse shapers 32-35 and element And 36.  FIG.  2 shows the control signals generated by the synchronization unit 1O and the changes they cause at the outputs of the integrator 2 and memory 3.  For control signals, a positive level (logical) in the diagram corresponds to the switched on state of the block controlled by it or to the closed state of the switched block.  FIG.  2a, the solid line shows the pulses at the sixth output of the synchronization unit 10, by which trigger 19 switches, the current state of which is shown by a punter.  FIG.  2c shows a dotted line signal at the fifth output, a solid pin signal at the seventh output of the synchronization unit 10.  FIG.  2C, Ct, the solid line shows, respectively, the signals controlling the sixth key 11 and the first key 4, dashed line 9M is the signal on the first code.  FIG.  2e, {the solid line shows control signals arriving at the seventh and second keys 12 and 5, the dotted line is the signal at the eighth output of the synchronization clock 1O.  FIG.  2 gi L, K respectively, the signals on the second, third and fourth outputs of the synchronization unit 10 are shown, dotted in FIG.  2 к - control signal by the fifth key 8.  FIG.  2 I shows the equivalent input signal of the integrator 2, FIG.  2It - changes in the output voltage of the integrator 2 (the point rum shows the output voltage of the storage unit 3).  FIG.  2p shows the output voltage of the voltage converter 18 in the code, the + sign indicates those intvapas of time during which the result of converting this voltage goes to the direct input of accumulating adder 9, and the - - interval during which the preform result arrives on the inverse inlet of the accumulating adder 9.  The computational process takes the color of the clock cycle, each of which contains L cycles (in FIG.  2 depicts a partial case with n 3).  The beginning of each clock coincides with the impulse formed by the block 1O and timing at the sixth output (FIG. 201 1 this impulse, impact on the trigger 1 changes its state to the opposing one.  Thus, the current state of the trigger 19 determines the number of the current clock: the state O corresponds to the first clock (FIG. 2 a), and the second state (FIG. 2C | 3).  At the beginning of the first clock cycle, the trigger 19 is set to the state O and controls the ISIS multiplexers with its output signal: according to this signal, the outputs of the voltage converters in time interval 1 and ring in time interval 17 are connected respectively to the control inputs of the sixth and seventh keys 11 and 12, and the output of the voltage converter in the kotz - to the direct input of the accumulating adder 9.  At the same time, block 10 at the seventh output produces a pulse, the duration of which is equal to the cycle intensity T "(this pulse, which is the signal for the passage of the first cycle, is shown in FIG.  2b1).  Together with the output signal of the inverter 22, which indicates the passage of the first clock cycle, this pulse includes the first Hj2O element. The output signal of the included first element AND 20 gives the accumulating adder 9 and the memory register 16 permission to operate during the first cycle of the first cycle, as well as during This interval allows the voltage converter 1 to provide a pulse to the control input of the fifth key 8 via the second And 21 element.  During each cycle of the first and second cycle, the synchronization unit 10 generates four time intervals of a constant duration sequentially in time, which produce pulses of a corresponding duration at the first, eighth, second and third outputs.  The pulse at the first output has a duration exceeding the maximum duration of the output value of the voltage converter 1 in the time interval, and ensures that it starts at the beginning of the cycle: with this signal it converts the first variable at the input 23 of the first signal multiplier represented by, for example, time-frequency group or code in the time interval  duration t and produces impups corresponding duration.  Similarly, the pulse at the eighth output has a duration longer than the maximum duration of the output variable of the code converter 17 in the time interval and also uses to start it: by this signal, the code recorded in memory register 16 is converted by the code converter 17 into the time interval, having a factor conversion, to a time interval defined by a pulse of proportional duration.  The pulses emitted at the second and third outputs are used as control signals, respectively, permitting the memorization of the output voltage of the integrator 2 by the storage unit 3 and the closure of the third key 6, the pulse duration at the third output being equal to the nominal time of the integrator 2.  At the beginning of the first cycle of the first cycle, the trigger signal from the first output (, d), the transducer 1 is stressed in the time interval and produces a pulse of duration t.  This impulse, arriving at the control inputs of the fifth and sixth 11 keys through the included second element 21 and the first demultipexor 13, respectively, closes the fifth 8 and sixth 11 keys at the time IK (Fig. 2K1, C2).  In the first operation, the input of the voltage converter 18 to the code at time 4 / is connected to the second input 24 (the equivalent input signal of the voltage inverter & inverter 18 to the code is shown in FIG.  2p1), and as a result, the second input of the integrator 2 is connected to the zero potential bus, and the output voltage of the integrator 2 (Fig. 2ml) is the response to an equivalent input signal, due to the parasitic input current J of the operating usipntel of the integrator 2 (Fig. 211).  The output voltage of the integrator 2 after the end of this part of the cycle is 11 C, where C is the capacitance of the integrating capacitor of the integrator 2.  Simultaneously with 7: l. 0 the integration process of converting the second signaling to the second sign is multiplied.  The voltage converter 18 in kotz operates in a continuous & start mode, tracking the instantaneous value of the input signal: the conversion period in this mode is T (T, i Hip by the internal conversion generator. The voltage receiver 18 in Kotz and Hertz iCmin is the minimum value of the output voltage of the voltage transducer 1 in the intervap.  When the fourth and the first switches 7 and 8 are open, there is no voltage to the voltage converter in the input keyhole, and zero output signals are formed on its output, and during the closing of the nsrroro key 8, the voltage signal from the voltage converter 18 that is different from the zero signal is converted in cc F, L t U, H c L is the conversion coefficient.  Through the third cement multiplexer 15, the coke parcels arrive at the direct input accumulator 9, because the number of non-zero parcels in the first cycle of the first cycle is equal to the transformation time, if any.  , then in the accumulating adder 9, after the completion of the interval, the number is written down, representing the total sum, (2) a constant.  The number N (|, which is the first approximate result of the calculation, is copied to the memory register 16 by the enable signal of the first element And 20).  At the end of the pulse at the first output of the synchronization unit 10 (FIG. 2c1, at its eighth output, a pulse is generated to turn on the kotz converter 17 in the time interval (Fig. 2 ". 1, 4, and 1, using this signal, this converter produces a pulse of duration TO N-i which, via the second cement-multiplexer 14, is fed to the control input of the seventh key 12.  Similarly to the first part of the cycle, key 12 closes at time T (,, input integrat 2 for time f connects to zero potential bus, and at output integrate 2 for response to an equivalent input signal loaded with current 3 (in FIG.  lE, ni2 are shown, respectively, the equivalent input signal of integrator 2 in the frequency of the cycle and the change in its electrical voltage caused by it).  As a result of the datasheet, the output voltage of the integrator reaches a level of 21–11 ° C. At the end of this part of the first cycle of the first cycle, a resolution signal is generated at the second output of the synchronization unit (FIG. ), by which block 3 is turned on and remembers the level (3); The output voltage of the memory unit 3 is set in this part of the cycle along the curve of FIG.  and at the end of the transition process is (VT,).  (4) In the final part of the first cycle of the first clock cycle, a signal is generated at the third output of the synchronization unit 10 (FIG. 2H1), in which the third key 6 closes for a time T.  Due to this operation, the output of the storage unit 3 is connected to the input of the integrator 2, and it integrates the sum of the output voltage of the storage unit 3 and the equivalent signal due to the value 3 (the equivalent input signal of the integrator 2 and the response it caused in the frame part of the cycle are shown in FIG.  2t3, nn4).  At the end of the integration interval, the output voltage of the integrator is 2.  u; u ;; - iT-uWt. -iT. uti).  i- where UG is the actual time constant of the integrator 2.  The operation of voltage converters in time 1 and code in time interval 17, integrator 2 and memory block 3 in the second and subsequent cycles of the first clock cycle is similar to the 1CNM operatives in the first cycle: the voltage across the time interval 1 and the time code the 17th interval of the sixth and seventh closures 11 and 12 ensure the integration of the equivalent signal during the corresponding time intervals; then, the memory output voltage level is remembered by the memory side 3 pa 2 ;, and the remainder of the cycle vyhots storage unit 3 to connect with the input of the integrator 2.  Thus, the termination voltage of block 3 is remembered at the end of the nth cycle of the first cycle Lf - (/ rn, t) {. - (. - IGHZ R - scale resistance of the integrator; T RC; T / 1.  During the last cycle of the first clock on the fifth output of the 1O synchronization block, an apitality pulse TU is generated, which serves as a signal for the hth cycle and for the second time during the first clock time it gives a resolution to the accumulating adder (Fig. 2 (At the fourth output of the synchronization unit 10, in the final part of the cycle, the interval in the vice of the pulse of frequency T is formed (FIG. 242) arriving at the control input of the fourth key 7, during the pan interval, the fourth switch is closed and the output voltage of the storage unit 3 is fed to the input of the voltage converter 18 (the equivalent input signal is shown in FIG. 12p2).  Like the first cycle of the cycle, the voltage converter 18 in kot produces code dressings F, j - L U Sp1, which through the third cemultipexor arrive at the direct input of the accumulator adder 9, the hertz produces an accumulation of all the parcels formed during this cycle and their summation with the first approximate result of N.  By the end of the last cycle of the first cycle in the accumulating adder 9 the result is recorded.  n At the beginning of the second cycle, the trigger 19 is set by the output signal of the synchronization unit 1O to the state (FIG. 2a3) and switches the demultipexors 13-15 to the state opposite to their state in the first clock cycle.  The control signals generated on the first, eighth, second and third outputs of the synchronization unit 1O in the second cycle repeat the sequence of signals output in the first cycle.  According to the signal from the first output of the synchronization unit 1O at the beginning of each cycle of the second cycle (FIG. 2C3, 12) the voltage converter 1 is turned on in the time interval and its output pulse closes the first switch 4 (cJtrHan controlling the first switch 4 is indicated in FIG.  2d3), connecting the input 24 to the input of the integrator 2.  As a result, the output voltage of the latter varies according to the sawtooth law, due to the total effect of the magnitude of the signal from the second input 24 and the equivalent signal caused by the parasitic current 3 (the corresponding input and output signals of the integrator are shown in FIG.  2l4, m5).  Toward the end of this part of the first cycle of the second cycle, the output voltage of the integrator is 2 3, n X Then, as in the cycles of the first cycle, the eighth output of the synchronization unit 10 produces a pulse through which the kotsv converter 17 is turned on (Fig. 213, 2), the impulse of duration Tp produced by this transducer lem (Fig. 2 {3) closes the second key 5 for the indicated time, connecting the third in hop 25 to the input of the integrator 2.  As a result, the total effect of the variable Ej from the third input 25 and the equivalent signal due to J varies the output voltage of the integrator 2 (the input and output signals of the integrator 2 are shown respectively in FIG.  2t5, m6).  At the end of this interval, the output voltage of the integrator is 2: -f (v. ) 4 (,) According to the enabling signal from the second output of the synchronization unit 10 (FIG. The output voltage of the integrator 2 is stored by the memory side 3 (a change in the output voltage of the block 3 of the input circuit is shown in FIG.  2t 7).  By

, 111О8801612

In order to shorten the transac- tion process of the tact of coax kits, the final cut at the output of the memory calculation unit 3 of the computation. In the final part of the first cycle of the second cycle at the third output of the synchronization unit 10 a signal is generated (FIG. 2b2), by which the third key 6 closes at time T . The output of this output of memory block 3 is to the input of integrator 2 and it integrates the sum of the output voltage of memory block 3 and the equivalent signal caused by the value (the input signal of integrator 2 and the changes it causes are shown in fig. 8). At the end of this interval, the output voltage of the integrator is 2; h M-I -. (In the subsequent cycles of the second clock cycle, the indicated operations are repeated in the result, as in the first clock cycle, an interactive process takes place at the outputs of the integrator 2 and the memory block 3. Similarly to the first clock, the output voltage of the memory block 3 after P second cycle "UV t" UI ... dlr, .n As in the first cycle of operation, during the last cycle of the second cycle on the fifth step of the synchronization unit, a pulse is generated, which gives permission to the accumulating adder 9 (FIG. 2) 3) . At the fourth output of the synchronization unit U in the final part of the cycle, an interval is formed in the form of a pulse of duration T (FIG. 2X3) controlling the closure of the fourth key 7. As a result, the output voltage of the storage unit 3 is fed to the input of the voltage converter 18 to the code (equivalent input the signal of the voltage converter 18 to the code is shown in Fig. 2p3). The voltage converter 18 generates code jumps F, which, through the third demultiplexer 15, receive, as opposed to the first clock, the inverse input of the accumulating adder 9. In it, after accumulating the sprinkling data and adding it to the result of the first) -CLE E. T)) Having provided, as in the known device U1 “1, where L 1, we get VE, t (l) - ((14). Thus, as in the known device, the accuracy of the result of the calculation does not practically depend on the stability of the transfer coefficient of the coding gfeobrae vatel: like the famous devices , in the first cycle, the approximate result is calculated, and in the second cycle, the correction is determined, and the accuracy of the correction, as in the known device, depends on the parasitic input current of the operational amplifier in the integrator 2. However, unlike the known device, in the nerve cycle, simultaneously with the approximate result calculates the additional correction, taking into account the subsequent influence of the output current of the operational amplifier in integrator 2 on the magnitude of the main correction in the second cycle. Due to this, the result of the calculation does not depend on the specified current, and therefore, its accuracy is improved. In the proposed multiplying device, the synchronization unit 10 may, for example, contain a pulse generator 27, the first and counters 28 and 29, the first and second AO diffusers and 31 , shapers 32 - 35 pulses, element 36, In this embodiment, pulse generator 27 produces pulses with a constant frequency of the following fQ, which both allow periodic variation of the soot (code) of consecutively connected counters 28 and 29, Em awn Purves th counter 28 is equal to i Tc, and the capacity of the second counter 29 - pikpov number n in each cycle. The beginning of each pick-up coincides with the transfer pulse, which is extracted by the first counter 28 at the moments of the e-th ream, and the beginning of each clock cycle - with the transfer pulse of the second counter 29, arriving at

Stichyy vykots block 10 synchronization. The threshold number of the cycpa is determined by the current state (code) of the second counter 29, and then

a shift relative to the beginning of the cycle, determined with an accuracy of the following period of the 1D generator of 27 pulses) the current state of the first counter 28 At one of the outputs of the second decoder 31, corresponding to the given code of the second counter 9 and, therefore, the current cycle number, there is a logical and on the output outputs of the second decoder 1 - logical O. Similarly, each position of the cycle corresponds to one of the outputs of the first decoder 30 on which a logical tapi appears at the moments corresponding to the foam position. The signals obtained in this way are used to start and stop pulse formers 32-35 (for example, triggers controlled by set inputs) at times that determine the 1st cycle position and also generate a signal on the fourth the output of the block 10 synchronization. These signals provide the required cp of the computational process with a sequence of control intervals of constant duration at the outputs of the synchronization unit 1O (fcg.2).

Compared with the known device, the proposed multiplying-dividing device has a higher accuracy of operation.

 ""

Claims (1)

A MULTIPLE DIVISION DEVICE containing the first and second keys, the outputs of which are connected to the integrator input, the output of which is connected to the inputs of the third and fourth keys through the memory unit, the third key output is connected to the integrator input, a voltage converter into the time interval, the input of which is the input of the first the device multiplier signal, the output of the fourth key is connected to the output of the fifth key, the input of which is connected to the input of the first key and is the input of the second device multiplier signal, input d of the second key is the input of the device’s healer signal, accumulating the adder, the output of which is the output of the device, the synchronization unit, the first output of which is connected to the control input of the voltage converter in the time interval, the second, third, fourth and fifth outputs of the synchronization unit are connected to the control inputs, respectively memorization unit, third and fourth keys and accumulating adder, characterized in that, with a chain for increasing accuracy, the sixth and seventh PDA> chi, the first and second oh elements And, inverter, trigger, first, second and third demultiplexers, voltage to code converter, memory register and code converter in a time interval, the integrator input connected to the zero potential bus through the sixth and seventh keys, the trigger output through the inverter connected to the first the input of the first element And, the output of which is connected to the control input of the memory register, with an additional control input to the droplets of the weighing adder and with the first ί “input of the second element And, the second input of which is connected to an ode to the voltage converter in the time interval and to the information input of the first demultiplexer, the first and second outputs of which are connected respectively to the control inputs of the first and sixth keys, the output of the second element And is connected to the control input of the fifth key, the output of the fourth key is connected to the input of the voltage converter into code, the accumulator adder through the memory register is connected to the input of the code converter in the time interval, the outlet of which is connected to the information input of the second demultip eksora, the first and second outputs of which are connected respectively to the control inputs of the second and the seventh key converter output voltage into a code coupled to the data input of the third demultiplexer lane vy and second outputs which are respectively connected to the direct and inverse inputs of the accumulator sum Matora, the trigger output is co-operative with the control inputs of the first, second and third demultiplexers, the sixth, seventh and eighth outputs of the synchronization block are connected respectively to the counting input of the trigger, to the second input of the first elements and to the control input of the code converter in the time interval.