SU1088004A1 - Device for simulating markovian signal arrivals - Google Patents

Abstract

A DEVICE FOR MODELING MARKOVSKY SIGNAL FLOWS, comprising a random code generator, a clock generator, an OR block, an AND block, a memory block, and a distribution law setting block consisting of n identical nodes; each of which contains a group of registers, a group of adders, the first and second groups of elements AND, a group of comparison circuits, the bit inputs of registers of all nodes of the block, the assignments of the distribution law are the corresponding installation inputs of the device, and in each node the outputs of the first register of the connection group with the first inputs of the corresponding elements And the first group, the outputs of the k-ro register of the group (, p) are connected to the inputs of the first group (It-l) -ro of the adder of the group, the second group of inputs of the first adder of the connection group It is corresponding with the outputs of the first register of the group, the second group of inputs of the M-th group adder (, p-1) is connected according to ifrMbrf .-. a terminal from the output of an (Ml) -ro group adder, the outputs of all group adders are connected to the first inputs of the corresponding elements AND of the first group, the outputs of which are connected to the inputs of the first group of the corresponding group comparison circuits, the output k-ft of the group comparison circuit is connected to the right the input (kl) -ro of the element AND the second group, the output of the p-th group comparison (, n-1) is connected to the p-m inverse inputs of the elements AND of the second group with a number greater than p, the output of the first comparison circuit of the group and the outputs of the elements AND the second groups are appropriate the outputs of the block node (L assign the law of distribution, the same output of the nodes of the block of the assignment law are connected to the corresponding inputs of the same name; the OR element of an OR block, whose outputs are connected respectively to the first inputs of the AND block, the second inputs of which are combined and connected to the output of the clock generator and the start input of the random code generator, the outputs of the elements And the block of elements And 4 are connected to the corresponding inputs of the memory block, the outputs of which are connected. to the second combined inputs of elements AND of the first group of the corresponding node of the distribution law assignment unit, the inputs of the second group of comparison circuits of which are connected respectively to the outputs of the random code generator, which differs in order to extend the functionality by means of

Description

splitting the input and output flows of queuing systems,. it additionally contains a register, a second and second comparison units and a delay element trn, whose inputs are pitch to the output of the clockwise 1T pulses, the memory block outputs, “MXMQiec group of outputs of the salt device, respectively, with register mode memory of the first group and the second (comparison units, the second groups of inputs of which are connected respectively to the bit outputs of the register, the outputs of the first and second comparison circuits are respectively the first and second gateways, the outputs of the first and second elements The delay items are connected respectively to the write enable input and the register reset input, and the third delay element is connected to the compare enable inputs of the first and second comparison circuits

The invention is based on computing technology and can be used for modeling the systems described by the apparatus of the theory of mass service.

A device for simulating queuing systems containing the first and second geyrators of a random stream of pulses, the element of SET-ETET, the reversible counter, the contiguous block of random time delays, the first and second elements of OR, bpoc comparison, the element I, the first, second and third counters, a block of elements And, the generator of pulses, the output of the first generator of a random stream of pulses is connected to the first counter and through the BAN element to a multichannel block of random time delays and a summing input m of a reversible counter, the output of which is connected through a block compared to the first input of the first element S1I, the output of which is connected to the control inputs of the AND element and the BAN, the input element I input is connected to the input of the first counter, and output 3 (it and the connected with the input of the second counter, the output of the second generator of a random stream of pulses is connected to the second input of the first element OR l the first input of the pulse generator, whose bridge is connected to the input of the third counter and through the second element OR to subtract the other input p of the eversive counter, whose discharge outputs are connected through the block of elements And to the second input of the pulse generator, and the output of the multichannel block of random delays is connected to

Another input of the second element IL1 SPnedost device consists in limited functionality, since the device simulates the operation of only systems with losses.

A device for simulating a queuing system is known, comprising first and second random pulse generators, a pulse generator, first and second crosshead meters, first and second reversing counters, a BAN element, a delay element, a multichannel block of random time delays, first, second, third , the fourth and fifth elements of the NL, the first, second and third elements AND, the block of elements AND, the synchronization unit, the adder, the threshold element, the driver and the switch, and the output of the first random generator from the pulses is connected to the input of the first counter and to the first input of the first element SH, the output of which is connected to the first input of the BAN element, the output of which is connected to the summing input of the first reversing counter and the input of the multichannel random time delay unit whose output is connected to the first input of the second element OR, the output of which is connected to the subtractive input of the first reversible counter, the output of which through the threshold element is connected to the first input of the third element OR, the second input of which is connected It is connected to the generator of a random pulse flow and is combined with the first input of the pulse generator. the second input of which is connected via the first element I to the bit outputs of the first reversible counter, and the output of the pulse generator is connected to the second input of the second element OR, the output of the third element OR is connected to the second input of the BAN element and The second input of which is combined with the input of the first counter, the first and second outputs of the synchronization unit are connected respectively to the controls of the inputs of the block of elements And and the adder, whose inputs are connected to the outputs of the block of elements And correspond nno whose inputs are connected. to the bit outputs of the second reversible counter and through the fourth element OR are connected to the first input of the third element AND, the second input of which is connected to the first output of the switch, the second output of which is connected to the input of the second reversible counter, the output of the third element And through the delay element is connected to the second input of the first element And directly with the subtractive input of the second reversible counter, the summing input of which is connected to the output of the fifth OR element, the inputs of which are connected to the output of the second ele And with the third output. A switch, respectively, whose inputs are connected respectively to the output of the pulse generator and to the output of the sixth OR element, whose inputs are connected respectively to the first input of the second OR element and to the pulse generator L2J. When modeling systems, each distribution law for the incoming message flow requires its own random flow generator. The device does not fix the temporal distribution of the output flow of requirements, which is important for modeling, for example, multiphase systems (in communication systems technology), as well as the occupation of service devices (busy period). All this limits the functionality of the device, which also differs in implementation complexity.

Closest to the invention in 5S with the first inputs of the corresponding,

the set of structural and function-elements And the first group, outputs

The main features of the group register (, p) are a connection containing a clock generator, respectively, with the inputs of the first 108 25 4 pulses, a random code generation unit, a distribution law setting unit, a block of elements AND, a block of DLI elements, a memory block The first installation inputs are connected to the first inputs of the assignment unit for the distribution laws, the second inputs of which are connected to the outputs of the random code generation unit, the input of which is connected to the output of the clock pulse generator and to the first input of the element block And that, the second inputs of which are connected to the outputs of the OR block elements having inputs connected to the outputs, the job distribution laws, the third inputs of which are connected to the outputs of the device and outputs the memory block, KdToporo inputs connected to the outputs of the AND block SPZ. The known device models a Markov process, which also describes queuing systems. If we set sufficiently small time intervals over which to investigate (simulate) a change in the states of the queuing system, then it is easy to imagine a probabilistic automaton as a model of the queuing system. However, the device does not allow recording the moments of entry and exit of requirements from the system, as well as the system’s maintenance, which limits the functionality of the known device. The purpose of the invention is to expand the functionality by simulating input and output streams in queuing systems. This goal is achieved by the fact that a device for modeling Markov signal streams, comprising a random code generator, a clock pulse generator, an OR block, an AND block, a memory block and a distribution law setting block, consisting of n identical nodes, each of which contains a group of registers, a group of adders, first and second groups of AND, a group of comparison circuits, bit inputs of registers of all nodes of the assignment law block are the corresponding installation inputs of the device, and in each The first outputs of the group of connectors of the () -th group adder are second, the second inputs of the first group accumulator are connected respectively to the outputs of the first group register, the second group of inputs of the M-th group accumulator, h -J) is connected respectively to the outputs (LL -) - the group's adder, the outputs of all adders of the T1 group are connected to the first inputs of the corresponding elements AND the first group, the outputs of which are connected to the inputs of the first group of the corresponding group comparison circuits, the output of the 7th-comparison group, is connected to the forward input of the (k-1) -th element This AND the second group, the output of the P-th comparison circuit of the group (f, h-1) is connected to the P-th inverse inputs of the elements AND of the second troupe with the number greater than P, the output of the first comparison circuit of the group and the outputs of the elements AND of the second group are the corresponding outputs of the node of the distribution law setting block, the same outputs of the nodes of the distribution law setting block are connected to the corresponding inputs of the element of the same name OR the block of elements OR whose outputs are connected respectively to the first inputs of the elements AND of the block of AND elements, the second inputs of which are connected and connected to the output of the clock generator and the start input of the random code generator; the inputs of the AND blocks of the AND block are connected to the corresponding inputs of the memory block whose output is connected to the second combined inputs of the AND elements of the first group of the corresponding node of the distribution law setting block; groups of comparison circuits of which are connected respectively to the outputs of a random code generator 1, additionally contains a register, the first and. the second comparison block and three delay elements, the inputs of which are connected to the output of the pulse clock generator, the outputs of the memory unit, which is a group of device outputs, are connected respectively with the bit inputs of the register, with the inputs of the first group of the first and second comparison blocks, the second groups of inputs which are connected to the bit outputs of the register, respectively, the outputs of the first and second circuits are compared and are respectively the first and second outputs of the device, the outputs of the first and second delay elements are connected respectively tween a write enable input and reset input of the register and the output of the third delay member is connected to the enable input of the first comparator and second comparator circuits. Fig, 1 shows a block diagram of the device; Fig. 2 is a functional diagram of the node of the distribution law setting unit; Fig, 3 - temporary / ulagramml operation of the device. A device for simulating queuing systems (Fig. 1) contains a group of setup inputs 1, block 2, specifies the distribution law, Generator 3 random code, generator 4 clock pulses, first 5, second 6 and third 7 delay elements, block 8 And elements , block 9 of elements OR, register 10, first 1) and second i 2 comparison blocks, the second comparison block 12 being implemented similarly to the first comparison block 11, output group 13, memory block 14, first and second outputs 15 and 16, Block 2 the assignment of the distribution law contains n nodes of the same type, to Each unit of block 2 includes a group of registers 17, a second group of inputs 18 connected to the corresponding outputs of generator 3, a group of circuits 19. comparison, the first group of elements AND 2, output 13j for each node connected to the corresponding i-th output 13 of the device, the second group of elements And 21, a group of adders 22, a group of outputs 23. The same types of nodes are connected to the inputs of one of this same element of the block of the block of elements OR, the device works as follows. According to the setup inputs I to the registers 17 of the block 2, the assignments of the distribution law are entered into the codes of the matrix of probabilities of transition of the queuing system. In this case, the probability P, -: - of the transition of the system to the e state, is entered into the register, provided that it was in the 1st state at the previous time. The device can simulate the process of the functioning of queuing systems as single-channel, ak and lgokanalnyh with failures and without reference. Moreover, for lossless systems, a restriction is imposed on the maximum queue length. In this case, in each case, the matrix of transitional potencies is formed individually.

Consider the formation of a matrix of transition probabilities for a n channel system. Bceli channels are absolutely identical, the vacant channel occupies the first requirement in the queue. The probability of Ro (r1-s (Cd, Po, and the probabilities of P, 2, PQ ..- P are equal to zero as the highest order value of wardship compared to POQ and cLintensity of the incoming Poisson flow of service requirements.

For lossless queuing systems with 1-channel, the matrix of transient probabilities has the same form as for the system with service devices 5, but in this case n is the maximum allowable number of queued queues (selected from the condition of maximum deviation from mathematical expectation ) .40

Suppose that a model is simulated with k devices and the maximum possible number of requirements in a system equal to h.

Then the presence of a signal at the first output 13- indicates that there are no requirements in the system and all the devices are free, the presence of a signal at output 132 in the system is one requirement and one channel is occupied, and the presence of a signal at output 5013 is occupied by two devices. If the output signal is busy servicing jBce V devices. If the signal is at the output of 13J, then the i devices are also occupied in the C-tkHl queue of requirements. 5S

Time intervals are chosen to be significantly smaller in magnitude than, e and. And the less D, the more

The accuracy P jf / tAt,, and

the probability P is distributed from the condition that the next demand enters the system, i.e. where L is the flow rate of the debugging. The probabilities are 0 ° (i 3, P). Validity R.l P P 2 normalized.

In general, the matrix of transition probabilities is

oCdi l + oiAt

the accuracy of the simulation, however, in this case, the simulation time increases. . .

The 4 clock frequency generator sets the time intervals, different for the period of its pulses.

The device works as follows.

/

The initial state of the simulator provides for the presence of a signal at output 13, ..., i.e. there are no requirements in the queuing system. According to the setup inputs 1, the P-matrix P codes are entered into the registers 17 of the block 2 of the assignment of the distribution law. With the arrival of the generator A pulse, which is fed to the inputs of the first. 5, the second 6 and the third 7 elements of the delay time. at the first input of the block of elements And 8 and the input of the generator 3 of a random code. it produces a code of a number evenly distributed in the interval from zero to one.

Since the output 13 is potted, then a potential is applied to the input 13-, block 2, the elements AND 20 of the first node of block 2 are opened and the register codes 17 as well as adders 22 | -22 | Served to the second inputs of the circuits {9; | -1 $ comparison If in registers 17 | -C stored codes ROO PO I PDI r codes are generated at the outputs of the register 17 and adders. -R ... R. f-I ,. Р, 2, ..., Ров Р о J.P Р + Р f 00 Т d «00 01 .., Р, 11th sum of the last element of the line is equal to one. Suppose that generator 3 has generated a random code А „. The number of which is less than the value of the code Rd. This code is fed to the inputs of circuits 19 | irl9} rv. Since code A is smaller in magnitude of codes supplied to another group of inputs of comparison circuits 19, potentials appear at their outputs, and the potential from the output, comparison circuit 19, closes all elements 21 and the signal only at output 23 of block 2 This signal comes through the block of 9 elements OR. Then, from potential 13, the potential is removed again (Fig. 3), i.e. during the time dt, the queuing system Hfe enters the queuing system. On the falling edge of the generator 4 signal, through the first delay element 5 to the register 10, a recording of the output state of the outputs 13 occurs. Moreover, before the leading edge of the generator pulse 4 with a slight delay generated by the third delay element 7, the numbers are compared in blocks 11 and 12 of the comparison register - 10 and the new state of outputs 13 in the position code. As changes occur, there are no signals at the outputs of the first 11 second 12 blocks of comparison. After comparing, the second delay element resets the register 10 to the zero state, i.e. The process of comparison with the previous exit code 13 occurs before writing the new state of the outputs 13 to the register 10. Suppose (Fig. 3) that only the fourth interval At has received a message in the mass service system. Consider how this is modeled in the system. With the arrival of the fourth pulse from the 4 clock pulse generator, the generator of the 3 random code generates a code whose value is less than the number Q + Pjj, but greater than the number PQJJ. In this case, the schemes are triggered, -1 equals. The signal from the output of the P circuit detects the AND elements. and at the output 137 of the unit 2, a potential appears, which passes through the block 9 of the elements OR, the block 8 of the elements AND, a potential appears at the second input of the block 14 of memory and at the output 13 of the device. This simulates the case of a demand arriving at the system for an interval Ai and accepting it for service. In the system, one channel is serviced. The presence of a signal at output 13 indicates that service is busy in the system with one channel of one demand and the absence of a queue in the system. t By the appearance of a pulse at the output of the third delay element 7, a potential is applied to the inputs of the blocks 11 and 12. Since at the outputs of register 10 the code 1QOO ... is taken, fed to one input of block J1, and the code 01000 ... which is less than code 10,000 ... is applied to its other inputs, the output of the comparison block I1 appears which is applied to output 15. The appearance of potential at output 15 indicates the arrival of a demand in the sweep time set by generator 4, and that the service of one channel is occupied. Fig. 3 shows that in the sixth interval At, another requirement arrives in the system and the second channel is occupied by the service, since the signal appears at the output 1X of the device and at output 13. If, after any interval, L will the service is completed, then a signal appears at output 13 in the order of the index number, less by one than I3j. In this case, the second comparison block is triggered. At the third output 16 of the device, a potential appears, which makes it possible to fix the time for the demand to leave the queuing system. Thus, in the process of modeling the queuing system, it is possible to obtain a model of the input message flow by analyzing the cob impulse flow at output 15, the model of the output message flow by analyzing the flow of impulse at output 16, the occupancy model of the service system. on the analysis of the potentials at the outputs 13.

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Claims (1)

DEVICE FOR SIMULATING MARKOV SIGNAL FLOWS, comprising a random code generator, a clock, a block of OR elements, a block of AND elements, a memory block and a block for setting the distribution law, consisting of η identical nodes; each of which contains a group of registers, a group of adders, the first and second groups of AND elements, a group of comparison circuits, bit inputs of the registers of all nodes of the block, the assignments of the distribution law are the corresponding installation inputs of the device, and in each node the outputs of the first register of the group are connected, yens with the first inputs of the corresponding elements of the first group, the outputs of the k-th group register (k = 2, p) are connected respectively to the inputs of the first group (ic-l) -ro of the adder of the group, the second group of inputs of the first adder of the group is connected to responsible Exactly with the outputs of the first register of the group, the second group of inputs of the Mth adder of the group (M = 2, η-l) Connected respectively with the outputs (Ml) -ro of the adder of the group, the outputs of all adders of the group are connected to the first inputs of the corresponding elements of the first group , the outputs of which are connected to the inputs of the first group of the corresponding group comparison circuits, the output of the kth ^ group comparison circuit is connected to the direct input of the (k-1) th element of the second group, the output of the rth group comparison circuit (p = 1, η-l) is connected to the rth inverse inputs of the elements AND of the second group with number, pain they p, the first output circuit outputs the comparison group element and _β 'cops and second groups are co-responsible ® output node job distribution law block of the same name setting unit outputs the distribution law of nodes connected to respective inputs of OR ^ homonymous block OR- elements (the outputs of which are connected respectively to the first inputs of the elements AND of the block of AND elements, the second inputs of which are combined and connected to the output of the clock generator and the input of the start of the random code generator, the outputs of the elements And the block elements are connected to respective inputs of the storage unit, whose outputs podkpyu-. are the terms for the second combined inputs of the elements And of the first group of the corresponding node of the block for setting the distribution law, the inputs of the second group of comparison circuits of which are connected respectively to the outputs of the random code generator, which differs in that, in order to expand the functionality by modulating input and output flows in queuing systems, it additionally contains a register, first and second comparison units and * three delay elements, the inputs of which are connected to the output of the clock pulse generator memory outputs, which are a group of device outputs, are connected respectively to the bit inputs of the register *, to the inputs of the first corpses of the first and second comparison blocks, the second input groups of which are connected respectively to the bit outputs of the register, the outputs of the first and second comparison circuits are respectively the first and the second outputs of the device, the outputs of the first and second delay elements are connected respectively to the recording enable input and the register reset input, and the output of the third delay element is connected to the inputs and permitting comparison of the first and second comparison schemes.