SU1078435A1 - Adaptive amplitude analyzer - Google Patents

Abstract

An ADAPTIVE PULSE ANALYZER containing a subtracting unit, the first information input of which is the analyzer input, and the clock input of the subtracting unit combined with the reset input of the shift register and connected to the first output of the synchronization unit, the second output of which is connected to the information input of the counter, whose output outputs are connected respectively, with the bit inputs of the decoder, the bit outputs of which are connected to the first group of bit inputs of the first switch, the second group of bit inputs of the cat It is connected respectively to the outputs of the weighting factors block, the bit outputs of the shift register are connected respectively to the bit inputs of the second switch, the bit outputs of which are connected to the first group of inputs of the meter block, respectively, in order to improve the accuracy a priori indefinite. properties of the signal, it contains the sign discriminator, the third switch, the key, the delay element, the comparison circuit, the AND elements, the maximum calculator, the module driver and the averager whose input is connected to the analyzer input, and the output is the first analyzer output and connected to the second information the input of the subtraction unit, the output of which is connected to the input of the discriminator of the sign and the input of the generator module, the output of which is connected to the first input of the comparison circuit and the information input of the maximum computer, ticks The input I of which is connected to the third output of the synchronization unit, and the output is connected to the input of the weight setting unit, the second input of the comparison circuit is connected to the output of the first switch, and the output is connected to the reset input of the counter and the information inputs The control of which inputs are connected respectively. With the first and second sign outputs of the sign discriminator, vj and the outputs of the And elements are connected to X 4 00 SP respectively to the information inputs of the second and third switches, the bit inputs of the third switch are connected to the bit outputs of the shift register, and the bit outputs of the third switch are connected to the second group of inputs of the counter block, respectively, the output of the counter block is the second output of the analyzer, the clock input of the key is connected to the second output of the synchronization block, the first output of which is connected through the delay element to the information input of the shift register, the shift input of which is connected to the output of the key.

Description

The invention relates to specialized means of automation and computer technology designed to determine the characteristics of random processes under conditions of lack of a priori information, for example, in oceanology, meteorology and radio physics. An adaptive amplitude analyzer containing an analog-to-digital converter, a memory device and an adder are connected, respectively, the output of the adder is connected to the information storage device, averager, subtraction unit, number register, comparison unit, adjustable frequency divider and synchronization unit G. The drawback of the device is the need for a priori knowledge of the properties of the signals, and to rationally set the comparison threshold, determine the accuracy of the calculations and the rate of convergence of the algorithm. An adaptive analyzer is known that contains a sample counter, a block for fixing the moment when the sample ends, two memory blocks, a minimum code memory block, a unit voltage source, an adder, a switch, a shift shift register, the output of which is connected to the address inputs of the memory blocks. The disadvantages of the analyzer are low speed and a large amount of memory. The closest in technical essence to the present invention is a time-pulse amplitude analyzer containing a calculator (threshold device), a synchronization unit connected to the clock input of the shift register, the outputs of which are connected to the inputs of the second switch through the first switch The outputs of which are connected to the inputs of the block of meters, while the control input: the second switch is connected to Biji; the codes of the decoder, the input connected to the output of the counter Sj Disadvantages of the analyzer the pa- tat are the need to iteratively set the threshold level for the yarn given by the human operator in the experiment, setting the width of the differential corridors once, the need for rational (manual) operation modes depending on the properties of the input signal, since for different ranges (amplitude range ) the analyzer provides a different accuracy of the histogram approximation, a different value of the average value of the signal leads to a shift of the histogram from the middle of the range (w kala) analysis. Together, this leads to the need for a significant increase in the memory volume (the number of counters), an increase in the duration of experiments to set optimal analysis parameters, or to a proportional decrease in the amplitude analysis accuracy: signal properties. The purpose of the invention is to increase the accuracy of the analysis under the conditions of a priori uncertainty of the signal properties. The goal is achieved in that an adaptive amplitude analyzer containing a subtracting unit, the first information input of which is the analyzer input, and the clock input of the subtracting unit are combined with the reset input of the shift register and connected to the first output of the synchronization unit, the second output of which is connected to the information input the counter, the bit outputs of which are connected respectively to the bit inputs of the descrambler, the bit outputs of which are connected to the first group of bit inputs of the first switch, the second group of bit inputs of which is connected respectively to the outputs of the weight setting unit; the bit outputs of the shift register are connected respectively to the bit inputs of the second switch, the bit outputs of which are connected to the first group of inputs of the counter block, the sign discriminator is entered, the third switch, the key, the delay element, the comparison circuit, the AND elements, the maximum calculator, the module driver and the averager whose input is connected to the analyzer input, and the output is the first The device is connected to the second information input of the subtractor, the output of which is connected to the input of the sign discriminator and the input of the module former, the output of which is connected to the first input of the comparison circuit and the information input of the maximum transmitter, the clock input of which is connected to the third output of the synchronization unit, and the Bt input is connected to the input of the weighting factors block, the second input of the comparison circuit is connected to the input of the first switch, and the output is connected to the reset input of the counter and to the information the inputs of the key and the first and second elements And, the control inputs of which are connected respectively to the first and second sign outputs of the discriminator of the sign and the output of the elements K are connected respectively to the information. the inputs of the second and third switches, the bit inputs of the third switch are connected to the bit codes of the shift register, and the bit inputs of the third switch are connected to the second group of counter-block detector pairs, respectively, the output of the counter block is the BTOps-.M output of the analyzer with the second output of the synchronization unit, the first output of which is connected via an element of the zadaruski to the inlay input of the shift register, the shift input of which is connected to the output of the key.

Figure 1 shows the structural diagram of the analyzer; Fig.2Aillustration signal processing; Fig. 26 shows a comparison of the absolute value of each sample of a signal with a measurement scale (normalized to the maximum value of samples) in FIG. 2c - types of density of distributions without rationing by argument.

The adaptive amplitude analyzer contains averager 1, sequentially connected subtractor 2, shaper 3 modules, calculator 4 maxima, weight setting unit consisting of a number of weight resistors 5 |, 5y ,,. ,, 5} i. The counter 6, the decoder 7, the first switch 8 are connected in series. The output of the comparison circuit 9 is connected to the control inputs of the counter 6, the key 10 and the first inputs of the elements 11 and 12, the second inputs of which are connected to the discriminator 13 inputs.

The first and second inputs of the synchronization unit 14 are connected to the clock input of the counter 6, through the key 10 to the clock input of the shift register 15, and through the delay element 16 to the information input of the shift register 15, the outputs of which through the switches 17 and 18 are connected to the corresponding inputs of the block 19 counters.

The adaptive amplitude analyzer calculates the density of the amplitude distributions in two stages: the learning stage and the evaluation stage of the function W (x).

In the initial state, the analyzer blocks are set to the zero state; in the second code of the synchronization unit 14, the sampling frequency of the signal under investigation is set.

At the training stage, the signal under study is fed to the inputs of the averager 1 and subtractor 2. The current aggregate of mean value M (x) calculated in the averager 1 is fed to the second input of the subtraction unit 2, the output of which thus forms a centered random process.

x. (),

where n - the moments of the reference signal to the pulse pulses from the block 14 synchronization (figure 2 a).

Centered bipolar signal x; enters the generator module 3 in which the absolute value of these samples / x is formed. When reading each -th sample to the input of the calculator 4 maxima, it compares the amplitude of the sample / x / s with the maximum value of the previously received sequence of samples and the largest of these values is remembered. for a subsequent comparison.

Thus, in the maximum 4, the maximum of the signal samples is selected and recorded, which is a characteristic of the magnitude of the calculated function V / (x).

Consequently, the value of / X | „d, sets the scale of measurement (figure 2) and the step size LK (x,) of the mouth X / k, where -K is the number of differential corridors (ordinates of the function). Since the determination of the maximum of the values of the sample modules does not require high reliability, the learning stage is performed at a small interval TgJ: (0.2 - 0.3) TC, where, TC is the interval for calculating the Vx estimate, i.e. duration of the assessment phase

The evaluation stage is implemented under the initial condition formed during the training phase. Information on the expected amplitude range of the function is obtained from the original current data.

In this case, the argument pitch & x is set with the aid of the p and the weight resistors 5, 5,,. . . , 5, connected to the output of the maximizer 4, and the control potential input to it in this mode is prohibited, i.e. stopping the counting of Xjj samples in block 4.

Similar to the learning phase, the procedure is performed by the clock pulses from the synchronization unit 14. The samples x (4ut) obtained at the output of subtraction unit 2 are fed to the inputs of the imaging unit 3 and the sign discriminator 13, in which the sign of the count (xi) is determined according to which the discriminator 13 of the sign forms the potential for opening element 11 and 12 ( for example, npHSgur + l is open And 12, and -1 open And 11). At the same time, a reference module is formed in the mold body 3, which is fed to one input of the comparison circuit 9. The second input of the comparison circuit 9 is given to the corresponding resistors 5fy, and through the switch 8 a sequence of threshold levels U, At the time the relation ini is performed in the comparison circuit 9, a single impulse is formed (Fig.26) which through the corresponding element 11 and 11 12 receives the input of the switch 17 or 18. Simultaneously with these conversions, the synchronization unit 14 receives a sequence of clock pulses as counter 6 (for interrogation via the decoder 7 and switch 8 in series with the weight resistors 5 |, 5 ,,., 5 |) , This and through the key 10 to the clock, the input of the register 15 shift, each clock pulse shifts a single pulse 1 (recorded at the moment of taking the signal to the first cell of the shift register 15) in the next register 15 register. Therefore, when you read the threshold voltage Y, and n, t, „.. register 15 simultaneously opens the corresponding m, m +1) ,, .. switch input 17 (or 18). Consequently, at the moment the comparison circuit 9 is triggered, this impulse goes through the open input of the switch 17 (or 18) to the corresponding counter hij (kn +1),. block 19 counters. The same impulse is applied to the control key input 10, closing it, and to the control input (reset input) of the counter 6, setting it to the zero state. When the next control (14) pulse is supplied from the second output of the synchronization block 14, it arrives at the control input of block 2, forming a signal count) bt to the control input Setting zero (reset) of the shift register 15, and through the delay element Egg 16 to the information input (installation) of the same register; 15 and 15, so that the next signal processing cycle begins in the analyzer blocks. Subsequent transformations, i.e. forming the module, comparing it alternately with threshold voltages (figs 2a, b), determining the sign (y) and recording a single pulse from the output of the comparison circuit 9 to the corresponding counter of the counter block 19 is made similarly in the loop, resulting in an estimate in the counters amplitude distribution density (Fig. 2c). Thus, due to such a sequence of microoperations, a new computational procedure is provided in comparison with the prototype with the specification of an analysis scale with an argument step proportional to the maximum signal value, which makes it possible to calculate the distribution density in a wide range of amplitudes without increasing the error and reading the data characteristic of digital analyzers, allows to simplify the structure of the analyzer and to increase its speed, while reducing the requirement The blocks are provided by introducing a centering mode and distributing the samples into the counters depending on their sign. The application of the proposed analyzer for the operative processing of random signals under the conditions of a priori uncertainty of their amplitude properties is relevant in scientific and technical experiments, for example, in remote sensing of the sea surface using the integrated program “Development of the World Ocean”, during technical diagnostics of various objects, as well as in medical research, require simple maintenance of the equipment at low preparatory time for trial experiments and a minimum of tiyu human operator.

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Claims (1)

ADAPTIVE AMPLITUDE ANALYZER containing a subtraction unit, the first information input of which is the input of the analyzer, and the clock input of the subtraction unit is combined with the input of the shift register reset and connected to the first output of the synchronization unit, the second output of which is connected to the information input of the counter, the bit outputs of which are connected respectively to bit inputs of the decoder, the bit outputs of which are connected to the first group of bit inputs of the first switch, the second group of bit inputs of which inena respectively to the outputs of reference weighting coefficients block, bit outputs of the shift register are connected to bit inputs of the second switch, bit outputs of which are connected respectively with the first group of inputs of counters block distinguishing by the fact that, in order to improve accuracy under a priori uncertainty. In addition to the signal properties, it contains a sign discriminator, a third switch, a key, a delay element, a comparison circuit, AND elements, a maximum calculator, a module driver and an averager, the input of which is connected to the analyzer input, and the output is the first analyzer output and connected to the second information input a subtraction unit, the output of which is connected to the input of the sign discriminator and the input of the module former, the output of which is connected to the first input of the comparison circuit and the information input of the maximum calculator, a clock input it is connected to the third output of the synchronization block, and the output is connected to the input of the weighting unit, the second input of the comparison circuit is connected to the output of the first switch, and the output is connected to the counter reset input and to the information inputs of the key and the first and second elements AND, control inputs which are connected to corresponding, governmental with first and second outputs of the discriminator iconic ^mark; · And the outputs of the AND elements are connected 'respectively to the information inputs of the second and third switches, the bit inputs of the third switch are connected to the bit outputs of the shift register, and the bit outputs of the third switch are connected to the second group of inputs of the counter block, respectively, the output of the counter block is the second output of the analyzer, clock the key input is connected to the second output of the synchronization unit, the first output of which is connected through the delay element to the information input of the shift register, the shift input to It is connected to the key output. ί