SU1078431A1 - Versions of device for rotating vector - Google Patents

Abstract

1. A device for rotating a vector containing two registers, two shifters, four adders, a pulse generator, a memory block, a subtraction block, a group of threshold elements, a priority block, an accumulator and an analog-to-digital converter, the input and output of which are connected respectively to the accumulator output of the adder and subtracting the input of the subtraction, the aggregation of the input, the clock input, the sign and informational outputs of which are connected respectively to the analog input of the device, the output of the pulse generator , the input increment accumulating adder and the inputs of the group threshold elements, the clock input and the output accumulator of the totalizer are connected respectively to the output of the pulse generator and the information output of the device, the outputs of the threshold elements of the group are connected to the corresponding information inputs of the priority block, the control input of which is connected to the output of the generator of pulses , the first informational entries of the first and second registers are connected respectively to the first and second informational inputs of the the second information inputs of the first and second registers are connected to the outputs of the first and second, respectively., adders, the output of the first register is connected to the first information inputs of the first and third adders and the first output of the device coordinate code, and the output of the second register to the first information inputs of the second and fourth adders and the second output code of the device coordinates, the second information (About the inputs of the third and fourth adders connected to the outputs, respectively, of the first and second summat The ditch, information inputs and outputs of the first and second shifters are connected respectively to the outputs of the third and fourth adders and the second information inputs of the second and first adders, X) in order to increase its 4; ib speed, start up the device input connected to the gene input : pulse racer, installation input of accumulator 1W of the adder and first control inputs of the first and second registers, the second control inputs of which are connected to the input of the pulse generator, output the priority The leg unit is connected to the control inputs yuschimi first and second shift) motors or address input of the memory unit Tvyhod is connected to the data input of accumulator amount of the torus, and the control inputs of the first and second adders are connected to the input of subtracting block landmark.

Description

2. Device II. 1, it is 1U e e so that the priority block contains a group of P elements OR, a group of prohibition elements, an encoder and a priority register, the output of which is connected

with the output of the unit, control-avl gcia. and the information inputs of the priority register are connected respectively to the control input of the block and the output of the encoder, the first of which is connected to the output of the first OR element of the group, and the second, third ,. (P + 1) -th inputs of the encoder are connected to the outputs of the corresponding group prohibition elements, each information input of the block is connected to the first input of the corresponding OR element of the group and the forward input of the corresponding group prohibition element, the prohibition input of which is connected to the output of the last OR element and to the second input is a corresponding element of the OR group.

3. A device for rotation of a vector containing two registers, two shifters, four adders, a pulse generator, a memory unit, a subtraction unit, a group of threshold elements, a priority block, an incremental register, accumulating aggregator and a D / A converter, an input and the output of which is connected respectively to the output of the accumulating adder and subtracting the input of the subtraction unit, summation, the input whose sign and information outputs are connected respectively to the analog input of the device, the input nakaplivagatsego increment inputs of the adder and the threshold elements of the group information input

the output of the accumulating adder is connected respectively with the per-HCTi-a incremental increment code and the information output of the device, f.jax ;;.;:, bj of the threshold elements grout-1 are connected to the corresponding: cym information inputs of the priority block, the output of which is connected to the information input of the incremental increment register; the first information inputs of the first and second registers are connected respectively to the first and second information inputs of the device; the second information inputs of the first and second registers are connected There are outputs of the first and second adders respectively, the output of the first register is connected to the first information inputs of the first and third adders and the first code of the device coordinate code, and the output of the second register to the first information inputs of the second and fourth adders and the second output of the device coordinate code, the second information inputs the third and fourth adders are connected to the outputs of the first and second adders, respectively; information inputs and outputs of the first and second shifters are connected respectively naturally to the outputs of the third and fourth adders and the second information inputs of the second and first adders, distinguished so that, in order to control its speed, a counter, two encoders, a trigger, two AND elements, a prohibition element, a modulo two and a zero decoder are entered whose output is connected to the trigger information input, the setup input and the output of which are connected respectively to the trigger input of the device and first to the inputs of the first and second elements AND, the trigger input of the device is connected to the input of the device The settings of the accumulating adder, the direct input of the inhibit element, the first control inputs of the first and second registers, and the input of the pulse generator, the first, second and third outputs of which are connected respectively to the second input of the second element AND, the trigger input and the inverse of the element whose output connected to the second control inputs of the first and second registers, the output of the second element I is connected to the clock inputs of the subtraction unit, the incremental increment register and g "accumulator of a second adder, The second input and output of the first element I are connected respectively to the second output of the pulse generator and the synchronous input of the counter, the output of the incremental increment register is connected to the inputs of the first and second encoders, the synchronous information input and output of the counter are connected respectively to the third output of the pulse generator, the output of the second encoder and the decoder input zero, the first and second address inputs and the first and second information outputs of the memory unit are connected respectively to the output of the counter, the output of the nepgoro control encoder yuschim inputs of the first and the second shifter and the first input of the adder of modulo two, the second input and whose output is connected respectively to the output of the subtractor landmark and kschimi control inputs of said first and second adders.

The invention relates to computing and can be used in the control of model and girder devices of both general and special purpose.

Rotation of vectors and coordinates is used in many control and simulation tasks using real hardware. In this case, the rotation angle is often taken from the sensors in analog form, while the coordinates of the object are represented in the digital computer in digital form.

An analog-digital device for rotating a vector is known, which contains two adders, an OR element, four groups of AND elements, a reversible counter, two registers, a comparison circuit and other auxiliary elements, with the argument being represented in analog form by means of a comparison circuit and a reversible counter disintegrates with the Breaking of the elementary increments used to rotate the vector according to the method of solution on digital differential analyzers (CDA) of the defining systems of differential equations ij.

The disadvantages of this device are low accuracy and speed inherent in the methods of calculation by means of CDA.

A digital device for rotating a vector is known, which contains three registers, two shift blocks, seven adders, a memory block and a control block, moreover, the connections between the blocks are made according to the scheme that realizes the Wolder algorithm with result correction. If the argument is in analog form, then analog-to-digital converter 2 must be connected in series with the input of the third register. i The disadvantages of this device consist in large hardware costs and low speed, due to the need to perform a large number of iterations for each variable argument value.

Closest to the present invention is a device comprising serially connected standard tracking-type analog-to-digital converter, a digital device for rotating a vector, three registers, five adders, two shift blocks, a memory block, a state analysis block, a set of threshold elements, a logic block, a digital-to-analog converter and an accumulating adder, with an analog-to-digital converter converting an analog argument

into a digital code, after which the ocyine rotation of the vector each time from the initial state by the specified value of the argument.

A disadvantage of the known device is the low speed, due to the presence of a multi-step iterative process. When the vector is rotated from the initial state to the specified one.

The purpose of the invention is to increase vigor.

The goal is achieved in that, in the first embodiment, a device comprising two registers, two shifters, four adders, a pulse generator, a memory unit, a subtraction unit, a group of threshold elements, a priority unit, a accumulating adder and a digital-analogue converter, whose input and output are connected correspondingly with the output of the accumulating adder and subtracting the input of the subtracting unit, the summing input, the clock input, the sign and information outputs of which are connected respectively to the analog input of the device the output of the pulse generator, the increment input of the accumulator of the adder and the inputs of the threshold elements of the group, the clock input and output of the accumulator are connected to the output information of the device and the information output of the device. unit, the control input of which is connected to the output of the pulse generator, the first information inputs of the first and second registers are connected respectively to the first and second information inputs of the first and second registers are connected to the outputs of the first and second adders, the output of the first register is connected to the first information inputs of the first and third adders and the first output of the device coordinate code, and the output of the second register to the first information inputs of the second and the fourth adders and the second output of the device coordinate code, the second information inputs of the third and fourth adders are connected to the outputs, respectively the first and second adders, information inputs and outputs of the first and second shifters are connected respectively to the outputs

the third and fourth adders and the second information inputs of the first and the first adders, the trigger input of the device is connected to the input of the pulse generator, the installation input of accumulating its adder and the first control inputs of the first and second registers, the second control of the secondary inputs of which are connected to the output of the pulse generator, the output of the priority the block is connected to the control inputs of the first and second shifters and the address input of the memory block whose input is connected to the input (the memory input of the accumulator accumulator And control inputs of the first and second adders are connected to the sign output of the subtraction unit.

In addition, the priority block contains a group of n elements OR, a group of prohibition elements I, an encoder and a priority register, the output of which is connected to the output of the block, controls and information inputs of the priority register are connected respectively to the control input of the block and the output of the encoder, the first input which is connected to the output of the first element OR of the group, and the second, third, ... (n + 1) -th inputs of the encoder are connected to the outputs of the corresponding elements of the group prohibition, each information input of the block. connected to the first input of the corresponding element of the group and the direct input of the corresponding prohibition element of the group, the prohibition input of which is connected to the output: the next OR element and the second input of the corresponding OR element of the group.

According to the second variant, the device contains two registers, two shifters, four adders, a pulse generator, a memory block, a subtraction block, a group of threshold alimony, a priority block, an incremental register register, nakapg;; - 1st, this adder and digital-analogue converter, the input and output of which are connected respectively to the output of the accumulated iron accumulator and the subtractive input of the subtraction unit, the summing input, the sign and information outputs of which are connected respectively to the analog input of the device, the input increment no accumulating cyi-vCvsaTOpa and inputs. give the group threshold elements, the information input and output., the cy cymator accumulator is connected respectively with the output of the incremental increment register and the information output of the device, the outputs of the group threshold elements are connected to the corresponding information inputs of the priority block, the output of which is connected to the information input of the incremental increment register; the first information inputs of the first and second registers are connected respectively to the first and second information the device moves, the second information inputs of the first and second registers are connected to the outputs of the first and second adders, respectively, the output of the first register is connected to the first information inputs of the first and third adders and the first output of the device coordinate code, and the output of the second register is connected to the first information inputs of the second and fourth adders and the second output of the device coordinate code the second information inputs of the third and fourth adders are connected to the outputs of the first and second summers, respectively o, information inputs and outputs of the first and second shifters are connected respectively to the outputs of the third and fourth adders and the second information inputs of the second and first adders, additionally introduced a counter, two encoders, a trigger, two elements And, a prohibition element, a modulo two and a decoder zero , the output of which is connected to the information input of the trigger, the installation input and the output of which are connected respectively to the trigger input of the device and the first inputs of the first and second elements AND, the starting input The device is connected to the installation input of the accumulating adder, the direct input of the inhibit element, the first control inputs of the first and second registers and the input of the pulse generator, the first, second and third outputs of which are connected respectively to the second input of the second element And the clock input of the trigger and the inverse input a prohibition element whose output is connected to the second control inputs of the first and second registers, the output of the second element I is connected to the clock inputs of the subtraction unit, the register is incremental increments and accumulating adder, the second input and output of the first element And are connected respectively to the second output of the pulse generator and synchronous input of the counter, the output register of incremental increments is connected to the inputs of the first and second encoders, synchronous input, information Hbrii input and output of the counter are connected respectively to the third output of the generator of pulses, the output of the second encoder and the input of the zero decoder, the first and second address inputs and the first and second information outputs of the memory block are connected respectively to the output of the counter, the output of the first and ifrator, the control inputs of the first and second shifters and the first input of the modulo-two adder, the second input and output of which are connected respectively to the sign output of the subtractor and control the cadmium inputs of the first and second adders.

FIG. 1 shows a block diagram of a first embodiment of a device for rotating a vector; 2 is a block diagram of a priority block for the first embodiment of the device; in fig. 3 is a block diagram of a second embodiment of a device for rotating a vector; figure 4 - plot, illustrating the work of the second variant of the device.

The device for rotating the vector (Fig. 1) in the first embodiment contains two registers 1 and 2, two shifters 3 and 4, four adders 5-8, a pulse generator 9, a memory unit 10, a subtraction unit 11, a group of threshold elements 12, a priority block 13, accumulating adder 14 and digital-to-analog converter 15, the input and output of which are connected respectively with the output of accumulating adder a4 and subtract the input of block 11 of deduction. The summation input, the clock input, the sign and information outputs of the subtraction unit 11 are connected respectively to the analog input of the device 16, the generator output 9 pulses, the increment input on the left of the adder 14 and the inputs of the threshold elements 12 of the group. The clock input and output of accumulating adder 14 are connected respectively to the output of the pulse generator 9 and the information input of the device 17. The outputs of the threshold elements 12 are connected to the corresponding information inputs of the priority block 13 whose control input is connected to the output of the pulse generator 9. The first information inputs of the first 1 and second 2 registers are connected respectively to the first 18 and second 19 information inputs of the device. The second information inputs of the first 1 and second 2 registers are connected to the outputs of the first 5 and second b adders, respectively. The output of the first reg.gra 1 is connected to the first 1 information inputs of the first 5 and third 7 adders and the first output of the device 20 coordinate code, and the output of the second register 2 to the first OHOHcJM information of the second 6 and fourth 8 adders and the second output of the coordinate code 21 of the device 21. The second information inputs of the third 7 and fourth 8 adders are connected to the outputs of the first 5 and second 6 adders, respectively. Information inputs and outputs of the first 3 and second 4 shifters are connected respectively to the outputs of the third 7 and fourth 8 adders and the second information inputs of the second b and first 5 adders. The launch 22 of the device 22 is connected to the input of the generator 9 pulses, the input of the installation Q accumulates only cyNiMaTOpa 14 and the first control inputs of the first 1 and second 2 registers, the second control inputs of which are connected to the output of the pulse generator 9. The output of the priority block 5 is connected to the control inputs the first 3 and second 4 shifters and the address input of the memory block 10 whose output is connected to the information input of the accumulator of its adder 14. The control inputs of the first 5 and second 6 summers are connected to the sign output th subtractor block 11.

The device priority block 13 (Fig. 2) contains a group of Vi elements OR 23, a group of prohibition elements 24, an encoder 25 and a priority register 26, the output of which is connected to the output of block 13. The control and information inputs of the priority register 26 are connected respectively to the control input of the block 13 and the output of the encoder 25, the first input of which is connected to the output of the first element OR 23 of the group. The second, third, ... (n-t-l) -and the inputs of the encoder 25 are connected to the outputs of the corresponding elements of the ban group 24. Each information input unit 13 is connected to the first input of the corresponding element OR group 23 and the direct input of the corresponding element 24 of the group ban, the input of which is connected to the output of the subsequent element OR 23 and the second input of the corresponding element IL 23 group.

The previous device for rotating the vector according to the second variant (FIG. 3) contains two registers 27 and 28, two shifters 29 and 30, four cyNiMBTOpa 31-34, a pulse generator 35, a memory block 36, a lock 37, two and an actuator 38 and 39, three germs 40, two elements And 41 and 42, a bar element 43, an adder 44 modulo two, a decoder 45 zero, a subtraction unit 46, a group of threshold elements 47, a priority block 48, a register — 49 incremental increments, a accumulative adder 50 and a digital-to-analog converter 51, the input and output of which are connected respectively to the input accumulator cy 1 matopa 50 and subtractive input block 46 subtraction. The summing input, sign and information outputs of subtraction unit 46 are connected respectively to the analog input 52 of the device, the increment input of accumulating adder 50 and the threshold inputs of the group elements 47. The information input and output accumulate the totalizer 50 are connected respectively with the output, register 49 incremental increments and information output 53 of the device. The outputs of the threshold elements 47 of the group are connected to the corresponding information inputs of the priority block 48, the output of which is connected to the information input of the register 49 incremental increments. The first information inputs of the first 27 and second 28 registers are connected respectively to the first 5 and iiTOpOMy 55 information - / device inputs. The second information: the first inputs of the first 27 and second 28 / registers are connected to the outputs of the first 31 and second 32 adders, respectively. The output of the first register 27 is connected to the first information ports and the first 31 and third 33 adders and the first 56 code of the device coordinates, and the second register 28 to the first information inputs of the second 32 and fourth 34 matrices

and the second output 57 of the device coordinate code. The second information inputs of the third 33 and fourth 34 adders are connected with in turns 31 and 32 of the second adders respectively. Information inputs and inputs of the first 29 and 30 of the second EE / gay are connected to the outputs of the third

33 and the fourth 34 adders and the second information inputs of the second 32 and par 31 of the adders Output 58 of the decoder cool 45 is connected to the information input of the trigger 40, the installation input and output 59 of which are connected respectively to the trigger input 60 of the device and the first inputs of the first 41 5 and second elements I. The triggering input 60 of the device is connected to the input of the installation of accumulating adder 50, the direct input of the prohibition element 43, the first control inputs of the first 27 and

the second 28 registers and the input of the generator 35 pulses, the first 61, the second 62 and the third 63 outputs of which are connected respectively

5 to the second input of the second element And 42, the clock input of the trigger 40 and the inverse input of the prohibition element 43, the output of which is connected to the second control inputs

0 first 27 and second .28 registers. The output 64 of the second element And 42 is connected to the clocking of the inputs of the block 46 subtraction, register 49 incremental increments and accumulate only

5 adder 50. The second input and output 65 of the first element AND 41 are connected respectively to the second output 62 of the pulse generator 35 and the synchronous input of the counter 37. The register register of incremental increments is connected to the inputs of the first 38 and second 39 encoders. The counting input, the information input and the output of the counter 37 are connected respectively to

 the third output 63 of the pulse generator 35, the output of the second encoder 39 and the input of the distributor 45 zero. The first and second address inputs and the first and second information outputs of the memory unit 36 are connected respectively to the output of the counter 37, the output of the first encoder 38, the control inputs of the first 29 and second 30 shifters and the first input of the modulo 44 modulo two, the second input and the output of which is connected respectively to the sign output of the block 46 of the subtraction and control of the first inputs of the first 31 and second 32 adders.

The device in the first embodiment

works as follows.

The coordinates L and 1.2 of the source vector are numerically set at the information inputs 18 and 19 of the device (Fig. 1), the argument X at the analog input 16 and the start signal tg at the start of input 22 and after the tracking time the results at output 17 and outputs 20 and 21 codes of coordinates of the device in each clock cycle of the generator 9 pulses.

In subtraction unit 11, the difference between the analog value, the argument X and the voltage from the output of the digital-to-analog converter 15 is determined. At the sign output of the block, subtracting 11, the difference sign is fixed when the positive edge of the pulse arrives at the clock input. The module of the difference through the information output enters the threshold elements 12. The operation levels E of these elements correspond to the formulas:

for trigonometric functions

- (and 41

"about

for hyperbolic and exponential functions

E Artb2-4,

where E is the voltage corresponding to a value of X equal to one;

V is the sequence number of the threshold element 12.

Therefore, the trigger level of the threshold element 12c with the minimum number V 1 is maximum. Since the modulus of the argument X goes in parallel to all the threshold elements 12, then (n + 1-V) of these elements, for which the condition E, iX is fulfilled, go to the excited state (c - the total number of threshold elements 12), In the priority block, 13 groups of elements OR 23 and prohibition elements 24 (FIG. 2) form the excited one input of the encoder 25. At the output of this encoder 25, the code V of the excited threshold element 12 having the minimum number is formed. At the output of the priority register 26, the V code Vits when a positive pulse 13 is received from the generator 9 pulses at the control input of the priority block 13. The input to the control input of the memory block 10, the V code selects the Vth memory cell in which the digital CSC of the constant Ey is written. Consequently, both for trigonometric functions and hyperbolic functions together with exponential in memory block 10, made in the form of a ROM, the constants C 2arctd2 or C -2Arth2 should be stored with p-I-4

where N is the digital-to-analog converter 15.

The accumulating adder 14 accumulates the constants Su, and the result of the algebraic summation at the next cycle is recorded in the register of the accumulating adder 14 when the negative pulse front arrives at the clock input of the accumulating cyMN.aTopa 14. The register of this adder receives the code as output 17 of the device, so and to the input of a digital-to-analog converter 15 for generating a tracking signal on the subtracting input of the subtracting unit 11.

Thus, in comparison with the known analog-digital converter in the device

Fig. 1 changes the trigger levels of threshold elements 12; priority block 13 in this case generates a non-incremental (equal to one bit) increment of the argument, but only the sequence number of the multi-bit increment code. ; the magnitude of the multi-bit increment enters the accumulation of the adder 14 from the memory block 10;

As a result of this increment

the arguments take the values that allow the rotation of the vector in one cycle of operation of the generator 9 pulses.

. To rotate the vector of realization, the following ratios

-Cv-t4

Gd, .d.) -,

Uv .., .cho,

y and y

the contents, respectively, of the first 1 and second 2 registers at a given clock; (and y is the result of calculations at the outputs of the first 5 and second 6 adders, respectively, at the end of a given clock. ak for trigonometric functions 2- U% -,

so

y ..,)

.4.4T (, b from where the required relations follow to rotate the vector by a multi-bit increment of the argument

H, u ,,. Wv ,,.

47 ,. .

Since relations (1) are written in a non-explicit form, their realization per cycle is possible provided that adders are used, which are made according to the summation scheme of binary numbers in the redundant sign bit system. Since V varies from 1 to fj-4, the information is shifted in shifters 3 and 4 to the right by (5-M) bits. And since the depth of propagation of carries in each adder does not exceed two bits, then, thus, the stability of the combination circuit with feedback is ensured (four days of matrices and two shifters).

In general, the device operates as follows.

When the start-up pulse IQ arrives at the input 22, the front edge resets the generator 9 to its initial state, thereby synchronizing its output pulses I. In addition, the IQ pulse through the input of the installation zeroes the accumulating cy-1mator 14 and through the first control inputs prepares the first 1 and second 2 registers for entering information on the first information inputs of these registers, i.e. with information inputs 18 and 19 devices. Each information is entered into the indicated registers; times when the positive edge of pulses L is received at the second control inputs of the first 1 and second 2 registers. The first impulse L is delayed relative to the impulse for a time: J equal to approximately half of the duration of the launch of the impulse LQ, therefore, the coordinates of the coordinates b, and L, respectively, are primary at 1HF 1 and all 2 times later: i 110-: l & :: blunting a trigger img, / ;: v.f: - ;; .Also, the front FR | ENTO: .-. impulses 1 with generator; .for 9 of the pulses, the control input of the priority block 13 memorizes the code V, and the clock input of the subtracting block 11 - the difference sign at the sign output of the subtracting block 11 The output code V of the priority block 13 forms the number of shifts for the 3 l 4 shifter and also selects the address of the constant in block 10 of memory. According to the signal from the sign output of the subtraction unit 11, the operations of Addition or Subtraction are formed in the accumulation of the adder 14 as well as in the first 5 and second 6 summators.

during the pulse duration, the constants are sampled from memory block 10, the algebraic summation of su is performed in accumulator adder 14, the codes are shifted by shifter 3 and 4, and the summation operation is performed in cyMj-iaators 5 - V. The result is fixed on the negative pulse front output accumulative adder 14. In the pause between pulses 1) digital-to-analog converter 15 generates a signal that is subtracted from the argument X, forming a new difference.

In addition, transients are completed in the digital blocks by performing the implicit relationship (1).

Since by this time the starting impulse if ended, then the first control inputs and the first 1 and second 2 registers are prepared for recording information from their second information inputs, i.e. with the outputs of the first 5 and second 6 adders, respectively. Therefore, with the arrival of a blackened pulse With a positive front, the second y control inputs will have y and y values written to registers 1 and 2, respectively. In addition, in the subtraction unit 11 and the priority unit 13, new values of the sign of the difference and the V code will be fixed along this front; which, arriving at the appropriate blocks, provide the execution of calculations for the following clock cycle C.,

The maximum frequency of the signal X on the analog input 16 with amplitude Ffy | is defined by the expression

-CVi41

tg2

arc

;and

1 Ek

If 15.2 Hedgehog / E, then kHz.

At the same time, the duration of a clock in the 0.5 MCS is sufficient for performing the transfers in both the digital and analog parts of the device. Since the vector rotation operation itself is carried out without methodical error, and there is only a rounding error, which by increasing the bit size can be obtained arbitrarily small, the error of the rotating vector module is minimal, and the phase error is determined by the accuracy of the analog-digital converter and speed 5 analog signal changes X.

Thus, the zyin processing of a single value of the rotation angle XJ from the analog-digital converter in the proposed device requires one cycle of operation of the devices and in the prototype from 1 to W cycles, i.e. on average, BNt (2 times large (where N is the size of the digital-to-analog converter), and hence the frequency range of the signals on the analog input X for the plug-in device will be as many times as wide as for the prototype.

The information lag in the proposed device is 2 ticks (1 tick in analog-digital conversion units and 1 tick in units for digital vector rotation), and in the prototype this delay is variable and varies from (- | +1) to ( Jj + N) cycles {- cycles for analog-digital conversion and (1 -N) cycles for vector rotation), therefore, the efficiency of the proposed device for vector rotation is approximately (4 T f Bbiuje than the prototype).

The hardware costs in the proposed device are significantly less, since in comparison with the prototype, the register eliminates the adder, the control unit and the analysis unit, which is the total amount of the equipment.

As a basic device, a vector rotation device is used, built on digital differential analyzers of the Meteor-4 type with an analog-to-digital converter of the next type. Digital differential analyzers integrate according to the simplest formula of rectangles, therefore in such a device there are big contradictions between accuracy and speed, since to increase the accuracy a decrease in the integration step is required, which leads to a significant increase in the vector rotation time and a decrease in the frequency range of the device.

In the proposed device, the operation of vector rotation is neglected without methodical error and the integration step without an increase in error can be hundreds of times more than in the base device, which provides the proposed device with a much higher accuracy of vector rotation and speed

at comparable with the base device hardware costs.

The sequence of operation of the device according to the second variant (FIG. 3) consists in setting the coordinates Lj and (xu of the reference vector in the digital form on the information inputs 54 and 55 of the device, setting the argument X. on the analog input 52, setting the trigger signal on the input 60 and after tracking the results at the outputs 53, 56 and 57 of the device.

In blocks 27-34, the coordinates of the vector are calculated according to 5 with the ratios

,, r4, 4-2100, and .., U., Lou ,, ,, „,

where .ii ,, - the contents of the first 27 and second respectively

28 registers on the current 4th cycle;

U- ,. the output values of the outputs, cit) are responsible of the first 31 and second 32 sum TcjpOB; y-4 and the end of the i-th cycle; 2 - the coefficients generated by the shear blocks

29 and 30;

- sign size (41 or -1), received on the control of adders 31 and 32, All adders 31 - 34 are calculated by the summation scheme of numbers in the redundant binary sign number system, therefore, the correlations (1) are calculated per cycle Since the limited depth of propagation of carries of the second bit ensures the stability of calculations at V, 4. 5 Presenting the coefficients of 2-CV, +) as

,

50 where Su- is some constant, at the outputs of the first 31 and second 32 adders at the end of the clock cycle will be received

Ju.), T, py ,, Cvi -,

1 7 ,,) j, -5i, .co5,

WHAT corresponds to the rotation vector

at an angle of 5, With V,.

The initial information about the coordinates L, and Lj is entered into registers 27 and 28 by the signal at the first control inputs of these registers, and the results of the calculations are recorded with

adders in the same registers on the signal at the second control inputs.

Argument X in analog form is fed to the summed-up input of subtraction unit 46. The difference between the argument and the signal from D / A converter 51 is presented in subtraction unit 46 as a module at the information output and a sign at the sign output of subtraction unit 46. The sign signal is detected by a pulse at the clock input of subtractor 46 and is fed to the second input of modulator 44 modulo two and to the input of increments of accumulating adder 50 to form a summation or subtraction operation. The increment module from the information output of subtraction unit 46 is supplied to threshold elements 47 having trigger levels proportional to 2, where V is the number of threshold element 47. Priority unit 48 selects the excited channel with the minimum V number. The resulting unitary incremental increment code for the clock input is stored in the incremental increment register 49 and outputted to both the inputs of the encoders 38 and 39 and the information input of the accumulator 1 atope 50 for algebraic addition to the previous result, the result is added to the accumulator with the previous result 50 pulse 50 at the clock input. The installation input about accumulating the accumulator 50 is used to reset its contents to zero. The result of the addition, which is the tracked argument value. X in the digital code, is fed both to the information output of the device 53, and to the input of the digital-to-analog converter 51 to form a compensating signal on the subtractive. block 47 subtraction.

Since in the described set of blocks, represented by an analog-to-digital converter, incremental arguments of the argument X are formed, and elementary (per clock) rotations of the vector in blocks 27 - 34 calculate the coordinates for increments

C ,,. 2a.,

then incremental increments appear in the silt

 ,, Cvi 2Z. nn. (

- V; .Cii ctd-2

n - 1 t S3

where ,, is the sign of -, -, and constants for incremental increments of 2 coming from the output of the register of 49 incremental increments.

To set the value of the chiller in the device serves the second encoder 39, from the output of which this value enters the counter 37 for its preliminary installation. At the output of the first encoder 38 is formed

0 code V. The value i from the output of the counter 37 and the value V are fed respectively to the first and second address inputs of the memory block 36, made in the form of a ROM,

5 On the second information output of the memory block 36, the value V, which, together with the size of the sign of the increment on the sign output of the subtractor 46, is formed

0 specifies the sign of the elementary argument argument. The first information output of the memory block 36, which is connected to the control of the inputs of the shifters 29 and 30, forms the value Vj corresponding to the required constant Su; for the i-th step. The zero-decimal amplifier 45 serves to determine the zero state of the counter 37, which indicates the completion of the required steps.

for this incremental calculation 2,

Shshulsov generator 35, trigger 40, elements And 41 and 42 and the element

e: prohibition 43 form pulse signals that ensure the operation of the entire device.

The triggering signal of the low level enters the triggering input 60 (diagrams in figure 4) of the device at the moment of time tg.

the leading edge of the pulse generator 35 is reset to the zero state, with the formation of a series of pulses ll, and cj, respectively

5, the third 63 and first 61 outputs of the pulse generator starts with a delay C; The series of pulses generated at the second output 62 of the pulse generator 35 represents 0, delayed by IQ, IJ-,

In addition to the synchronization of the pulse generator 35, on the leading edge U i, the information oL and 1 | via information inputs 54 and 55, as it enters the first control inputs of registers 27 and 28,

During the duration of the unit, the prohibition element 43 blocks the signal from the second control inputs of the registers through the prohibition element 43. On the setup input, the trigger 40 is set to one state and on the input of the installation O of the pump, the adder 50 of the analog-to-digital converter is reset to the zero state. Since the trigger 40 is set to one, then with the arrival of the series, at the first output 61 of the generator 35 pulses and at the output 64 of the second element I

42 a positive impulse of 2 dC is formed. On the leading edge, SD 1, pn the output of the register of incremental increments 49 and the sign output of the subtraction unit 46 are fixed respectively to the values of the increment and the sign of the increment. The increment code 1 is iffed to i and v values, therefore with the arrival of the leading edge of the series

at the output of the first element And 41, a strobe is formed, allowing the entry of values into counter 37.

The durations of the series are counted, and 1, -5 is carried out from the falling edge of the triggering pulse O-jn The duration of the pulses of the series t is less than the series and ... At the end of the pulse, the series about 3 ends and the dc pulse ends with its falling edge fixing the result on the device 53 information output , as it arrives at the clocking input of the accumulating adder. 50. At the end of the pulse series bi from the third output 63 of the generator 35 pulses at the output of the circuit

43 banned signal is recorded, according to which information from the outputs of the first 31 and second 32 adders is copied to the corresponding registers 27 and 28. In addition, the falling edge of the series

1c, which arrives at the counting input of the counter 37, changes its state by one (counter 37 operates for subtraction). This state is decrypted by the decoder 45 zero, and if it turns out to be null, then a single signal 58 is sent to the information input of the trigger 40, which is transmitted to the output 59 of the trigger 40 at the moment of the end of the pulse t from the second output of the pulse generator. If the counter 37 is not in the zero state, then the trigger 40 has the zero state, as a result of which signals from dcp at the clock inputs of the corresponding blocks 46, 49 and 50 of the analog-to-digital converter are blocked, and the strobe entry is blocked at the synchronous input of the counter 37. In this case, the information about V is saved, and the counter 37 operates only in the subtraction mode. In this case, the blocks 27 34 carry out the sequence of the hpu elementary turns for incremental increment 2.

If the counter 37 is in the zero state, then by the back edge of the pulse, the trigger 40 is switched to the one state, therefore, according to the pulse t-J, a pulse is generated

Г (CPU controls the operation of the analog-digital converter units, and impulses ij are formed on the counter 37, the leading edge sets the depth for the new value V. The number of Wy values depends on the increment value and size of the coordinate calculation unit. For a steady-state tracking mode in blocks of analog-digital converter value

V is usually close to the maximum, therefore, P1 V most often takes values equal to one. In this case, the blocks 27-34 coordinate calculations work together with the analog-digital converter in a conveyor mode, i.e. parallel, without loss of time. In some cases, when the signal slope is sufficiently strong, it can be on the order of 5 to 10, which slightly increases the transient tracking of the argument X.

The development of one value of the input signal X increment from the analog-digital converter of the device according to the second variant is carried out mainly in 1 - 3 clock cycles compared to (1 -) clock cycles of the prototype, i.e. in the proposed device, the speed is N | 3 times higher than in the known. The hardware costs are reduced by 10 - 15% compared with the prototype due to the exclusion of the register, adder, memory block and state analysis block in the block forming the remainder of the argument from the device.

Unlike the first variant of the proposed device, the second variant has almost 30% slower performance with the same equipment waste, however, due to the fact that incremental increments are used for the argument, coordination with other incremental type devices can be made much easier.

G8

t, lft |; g J

26

Claims (3)

1. A device for rotating a vector, containing two registers, two shifters, four adders, a pulse generator, a memory block, a subtraction unit, a group of threshold elements, a priority block, accumulating the adder and a digital-to-analog converter, the input and output of which are connected respectively to the output of the accumulating adder and the subtracting input is a subtraction block, summing the input, the clocking input, the sign and information outputs of which are connected respectively to the analog input of the device, the output of the pulse generator, the input the increments of the accumulating adder and the inputs of the threshold elements of the group, the clock input and the output of the accumulating adder are connected respectively to the output of the pulse generator and the information output of the device, the outputs of the threshold elements of the group are connected to the corresponding information inputs of the priority unit, the control input of which is connected to the output of the pulse generator, the first information inputs of the first and second registers are connected respectively to the first and second information inputs of the device, the second the information inputs of the first and second registers are connected to the outputs of the first and second., adders, the output of the first register is connected to the first information inputs of the first and third adders and the first output of the device coordinate code, and the output of the second register to the first information inputs of the second and fourth adders and. the second output of the coordinate code of the device, the second information inputs of the third and fourth adders are connected to the outputs of the first and second adders, respectively, information inputs the outputs of the first and second shifters are connected respectively to the outputs of the third and fourth adders and the second information inputs of the second and first adders, characterized in that, in order to increase its speed, the trigger input of the device is connected to the input of the pulse generator, the installation input 'Ό of the accumulating adder and the first control inputs of the first and second registers, the second control inputs of which are connected to the output of the pulse generator, the priority block output is connected to the control inputs p the first- and second shift | motors or address input of the memory unit, whose output is connected to the data input of the accumulator and the control inputs of pervot-vto'rogo and adders are connected to the input of the subtracting unit landmark. 2. The device according to and. 1, characterized in that the priority block contains a group of η OR elements, a group of P prohibition elements, an encoder and a priority register, the output of which is connected to the output of the block, which controls. and the information inputs of the priority register are connected respectively to the control input of the block and the output of the encoder, the first input of which is connected to the output of the first element of the OR group, and the second, third, ..., (P + 1) -th inputs of the encoder are connected to the outputs of the corresponding prohibition elements groups, each information input of the block is connected to the first input of the corresponding OR element of the group and the direct input of the corresponding element of the ban of the group, the prohibition input of which is connected to the output of the next OR element and to the second input, respectively Leica Geosystems elements or groups. 3. A device for rotating a vector, containing two registers, two shifters, four adders, a pulse generator, a memory block, a subtraction block, a group of threshold elements, a priority block, an incremental increment register, an accumulating adder and a digital-to-analog converter, the input and output of which are connected respectively to the output of the accumulating adder and the subtracting input of the subtraction unit, the summing input, the sign and information outputs of which are connected respectively to the analog input of the device, the input increment n kaplivayuschego adder and inputs the threshold elements of the group information input d. the output of the accumulating adder is connected respectively to the output of the incremental increment register and the information output of the device, the outputs of the threshold elements of the groups are connected to the corresponding information inputs of the priority block, the output of which is connected to the information input of the incremental increment register, the first information inputs of the first and second registers are connected respectively to the first and second information inputs of the device, the second information inputs of the first and second registers are connected to by the first and second adders respectively, the output of the first register is connected to the first information inputs of the first and third adders and the first output of the device coordinate code, and the second register output to the first information inputs of the second and fourth adders and the second output of the device coordinate code, the second information inputs of the third and the fourth adders are connected to the outputs of the first and second adders, respectively, the information inputs and outputs of the first and second shifters are connected respectively to the outputs of the third and fourth adders and the second information inputs of the second and first adders, characterized in that, in order to increase its speed, a counter, two encoders, a trigger, two And elements, a prohibition element, an adder modulo two and a zero decoder are introduced, the output of which is connected to the information input of the trigger, the installation input and output of which are connected respectively to the triggering input of the device and the first inputs of the first and second elements AND, the triggering input of the device is connected to the input of the installation 0 flow adder, direct input of the inhibit element, the first control inputs of the first and second registers and the input of the pulse generator, the first, second and third outputs of which are connected respectively to the second input of the second element And, the clock input of the trigger and the inverse input of the element, the output of which is connected to the second control the inputs of the first and second registers, the output of the second element And is connected to the clock inputs of the subtraction unit, the incremental increment register and the accumulating adder, the second input and output the first element And are connected respectively to the second output of the pulse generator and the counter clock input, the output of the incremental increment register is connected to the inputs of the first and second encoders, the clock input, the information input and the output of the counter are connected respectively to the third output of the pulse generator, the output of the second encoder and the input of the zero decoder, the first and the second address inputs and the first and second information outputs of the memory block are connected respectively to the output of the counter, the output of the first encoder, control inputs ervogo and second shifter and the first input of the adder of modulo two, the second input and whose output is connected respectively to the output of the subtracting unit landmark and the control inputs of the first and second adders.