SU1075269A1 - Versions of device for calculating walsh transform - Google Patents

Abstract

1. A device for calculating a Walsh transform containing the first cam, the first and second i registers,; The output outputs of which are connected respectively to the first and second information inputs of the arithmetic unit, the information output of which is connected to the information input of the PCS, the control input of which is connected to the output of the first bit of the first constant memory block, the output of the second and third bits clock inputs, respectively, of the first and second ipoB, the information inputs of which are the information inputs of the device, the output of the fourth bit of the first block is a constant n The memory is connected to the clock input of the counter of the first and second memory blocks, the fixed memory is connected to the information output of the meter, the clock input of which is connected to the output of the clock generator, the startup input of which is the input, the device startup, the second block of the permanent memory t, iteration counter, in contrast to the fact that, in order to expand the field of application by processing sequences of arbitrary length, the base register, the second switch, the adder and the sample length register are entered, the information output to connected to the control input of the second switch, the output is connected to the zeroing input of the address counter and the clock input of the iteration counter, the information output of which is combined with the information output of the address counter and the output of the first bit of the permanent memory and connected to the address input of the second block of the permanent memory, the first information output of which is connected to the information input of the address count and connected to the primary input of the adder, the output of which is connected to the control input of the first com Mutator, information input of which is shared with information outputs of the first and second registers and connected to the information output of the PMT unit, the third information output, output of the second unit, fixed memory is connected to the installation input of the address counter, the second input of the adder is connected to the information output of the register , whose information input is combined with the information input of the sample length register and the information inputs of the first and second registers, and the output of the first com mutation is ormatsionnym output device. 2, A device for calculating a Walsh converter, comprising a first switch, a first and a second register, whose information outputs are connected respectively to the first and second information inputs of an arithmetic unit, whose information output is connected to the information input of a memory block, whose control input is connected to the output of the first discharge of the first

Description

a fixed memory block whose outputs of the second and third bits are connected to clock inputs of the first and second registers, respectively, the information inputs of which are information inputs of the device, the output of the fourth bit of the first memory block is connected to the clock input of the address counter, address the input of the first block of permanent memory is connected to the information output of the counter, the clock input of which is connected to the output of the clock generator, the start input of which is the input of the start of the device The second block of permanent memory, an iteration counter, is different in that the base register, the second switch, the adder, and the sample length register, the information output of which is connected to the control panel, are entered into it to expand the scope of applications for processing sequences of arbitrary length. Let's enter the second KoiviMyTaTopa, the output of which is connected to the zeroing input of the address counter and the clock input of the iteration counter, whose information output is combined with the information output of the address counter and the output of the same bit the first block of permanent memory and is connected to the address input of the second block of permanent memory, the first information output of which is connected to the information input of the address counter and connected to the first input of the accumulator and the address input of the memory block, the output of the accumulator is connected to the control input of the first the switch, the information input of which is combined with the information inputs of the first and second registers and connected to the information output of the memory block, the second information output of the second block of the permanent memory is connected a mounting input address counter, the second input of the adder is connected to the information outlet base register, whose data input is combined with the data input of the sampling register length and data inputs of the first and second registers, and the output of the first switch is a device information vyh1e ohms.

3. A device for calculating the Walsh transform containing the first switch, the first and second registers, whose information outputs are connected respectively to the first and second 1 information inputs of the arithmetic unit whose information output is connected to the information input 4 of the memory block control input which is connected to the output of the first bit of the first memory block, the outputs of the second and third bits of which are connected to the clock inputs of the first and second registers, respectively, the inputs of which are the information inputs of the device, the output of the fourth bit of the first constant memory block is connected to the clock input of the address counter, the address input of the first permanent memory block is connected to the information output of the counter, the clock input of which is connected to the output of the clock generator, the launch input of which is the input of the launch of the device, the second block of the constant parity, iteration counter, i.e. with the aim of expanding the field of application by processing the sequence of arbitrary length, a sample length register is entered in it, the information output of which is connected to the control input of the first switch, the output of which is connected to the zero input of the address counter and the clock input of the iteration counter, the information output of which is combined with the information output of the address counter and the output of the same bit Yes of the first block of permanent memory and connected to the address of the input of the second block of permanent memory, the first information output of which is connected to the information input of the address counter and the address The second input of the memory block, the information output of which is connected to the information inputs of the first and second registers and is the information output of the device, the second information output of the second junction of the permanent memory block is connected to the installation input of the address counter, the information input of the sample length register is combined with the information inputs of the first and second registers.

The invention relates to computing technology intended for the hardware implementation of the Fast Walsh Transformation Algorithm (TPS), which is used in digital signal processing. . A device is known for implementing a fast Fourier transform containing two switches, an iteration register, an address counter, a constant transmitting device (ROM ;, a sumattor C.) The disadvantage of this REN is that this device is rigidly bound to the sample length when the length is changed the selection of the device circuit is required. The closest to the technical essence of the invention is a device for performing a fast Fourier transform, containing the first switch, the first and the second register The information outputs of which are connected respectively to the first and second information inputs of the arithmetic unit, the information output of which is connected to the information (at the input of the memory block, the control input of which is connected to the output of the first digit of the first Apple permanent memory, the outputs of the second and The third bits of which are connected to the clock inputs of the first and second registers, respectively, whose information inputs are the information input of the device, the clock input of the address counter is connected to the fourth bit of the first memory block, the address input of which is connected to the information output of the counter, the clock input of which is connected to the output of the clock generator and pulse, the start input of which is the device startup input, the second block of the permanent Ps1m, iteration counter C2. However, the known device is hardware-oriented to a specific sample length, which is a consequence of the use of memory as a RAM with sequential access, L-JL "l 4 / V" iiiAV t J J (shift registers). In the case where the sample length does not match the memory capacity, the efficiency of ycTpottV is sharply deteriorated, and the deterioration depends on the ratio, where V is the memory capacity, 2 is the sampling length and is approximately equal to

The aim of the invention is to expand the field of application of the device by transforming sequences of arbitrary length.

The goal is achieved by the fact that in the first embodiment the device containing the first switch, the first and second registers, whose information outputs are connected respectively to the first and second information inputs of the arithmetic unit, the information output of which is connected to the information input 5

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The goal is achieved by the fact that, according to the second variant, the device contains the first switch, the first and second registers, whose information outputs are connected respectively to the first and second (SMI information inputs, tic block, information output of which is connected to the information input of the memory block, controlling the input of which is connected to the output of the first bit of the first memory block, the outputs of the second and third bits of which are connected to the clock memory block, the control input of which is connected to the output of the first In the first bit of the constant memory, the outputs of the second and third bits of which are connected to the clock inputs of the first and second registers, respectively, whose information inputs are the information inputs of the device, the fourth bit output of the first memory block is connected to the clock input address counter, the first input of the first memory block is connected to the information output of the counter, the clock input of which is connected to the output of the clock generator, the start input of which is The device start input, the second Permanent Memory block, the iteration counter, entered the base register, the second switch, the adder and the sample length register, the information output of which is connected to the second switch, the output of which is connected to the address counter zero and clock the iteration counter input, the information output of which is combined with the information output of the address counter and the output of the fifth bit of the first memory block and is connected to the address input of the second memory block The first information output of which is connected to the information input of the address counter and connected to the first input of cytvwaTopa, the output of which is connected to the control input to the first switch, whose information input is combined with the information output of the first and second registers and connected to the information output of the memory block, the second the information output of the second block of the permanent memory is connected to the set input, the address counter, the second input of the adder is connected to the information output of the base register, in .V b V K-4i «. mf l PE "| G.P fm-, mm formation input of which is combined with the information input of the sample length register and information inputs of the first and second registers, and the output of the first switch is the information output of the first and second registers, the information inputs of which are the information inputs of the device, the output of the fourth discharge of the first block of the permanent memory is connected to the clock input of the address counter, the address input of the first block of the permanent memory is connected to the information output meters, the clock input of which is connected to the output of the clock pulse generator whose start input is the device start input, the second block of permanent memory, the iteration counter are entered into the base register, the second switch, the adder and the sample length register, the information output of which is connected to control to the input of the second switch, the output of which is connected to the input of the zeroing address counter and the clock input of the iteration counter, the information output of which is combined with the information output of the address counter and output In addition, the first memory block is connected to the address input of the second memory block, the first information output of which is connected to the information input of the address counter —and connected to the first input of the accumulator and the address input of the memory block, the cyivwaTopa output is connected To the control input of the first switch, the information input of which is combined with the information inputs of the first and second registers and connected to the information output of the block, the second information output of the second, block of the permanent memory It is connected to the address input, the second input of the adder is connected to the information output of the base register, whose information input is combined with the information input of the sample length register and the information inputs of the first and second registers, and the output of the first switch is the information output of the device. The goal is achieved by the fact that, in the third variant, a device containing the first switch, the first and second registers, whose information outputs are connected respectively to the first and second information inputs of the arithmetic memory block, the control input which is connected to the output of the first bit of the first constant block memory, the outputs of the second and third bits of which are connected to clock inputs of the first and second registers, respectively, the information inputs of which are information inputs The output of the fourth bit of the first memory block is connected to the clock input of the address counter, the address input of the first memory block is connected to the information output of the counter, the clock input of which is connected to the output of the clock generator, the start input of which is the start input device, the second block of permanent memory, iteration counter, entered the sample length register, the information output of which is connected to the control input of the first switch, you-. the course of which is connected to the input of the zeroing of the address counter and the clock input of the iteration counter, informational. The on-line output of which is combined with the information output of the address counter and the output of the fifth digit of the first block of permanent memory and connected to the address input of the second block of permanent memory, the first information output of which is connected to the information input of the address counter and the address input memory card, information output. Which is connected to the information inputs of the first and second registers and is the information output of the device, the second information output of the second block of permanent memory is connected to the ny .The inputs of the counter adre- ca, data input register length-i us sample is combined with the data inputs of the first and second registers. The presence in the switchboard of a specific technical implementation is determined by the specificity of the organization of the cockal or the trunk of the satellite computer. For example, for a trunk in which the data and address busbars are divided into two sub buses, there is no need to transfer address data over one common bus, therefore, there is no need for this switch, and if you have passed the same data, then the switch is needed . The second information input of this switch is connected to the output of an autonomous memory unit, and the output of the RAM block must be either with three states or with an open collector load, because this output together with the device input forms a microchannel device to which information inputs are connected processor, sampling register and base register. In solving the device as a whole, options are possible. In the second variant, the capacity of the memory unit can be significantly reduced, depending on the lengths of the samples. The second option may have ups a valuable solution. The device according to the third variant, i.e., the possibility of using the memory block of a satellite computer as a working memory and is able to work only with its own memory block. Figure 1 shows the functional block diagram of the device; Fig.2 is a functional block diagram of the second embodiment; FIG. 3 is a functional block diagram of a third module variant; and FIG. 4 is a graph of the Walsh-Hadamard fast transform algorithm with substitution; FIG. 5 is a block diagram of the process; FIG. B is a time diagram of the operation of the processor j in FIG. 7, a block diagram of the device in conjunction with a computer. The dts Walsh transform calculation unit contains an address counter 1, a sample length register 2, a switch 3, an iteration counter 4, a fixed memory block 5, a base register b, an adder 7, a memory block (RAM / 8 processor 9, which consists of 9.1 and 9.2, arithmetic unit 9.3, clock generator 9.4, counter 9.5 and stationary memory 9.6, switch 10, information input 11 and information output 12 of the device. Arithmetic unit 9.3 of processor 9 is focused on performing the basic operation - consists from cleverly resident and adder. Let's work on the device using the example of the first option as the most common case. The work of private options does not differ from the first option in the corresponding modes. First, consider the device operation with external memory, which is used as a satellite main memory. perform the Walsh transform over the array 2, which is located in the computer RAM, starting with the address K at the address K + 2%. At the initial access to the module, the module is adjusted to the working memory field and to Line sample (array). For this, the initial address K is loaded into the base register B, and the length of the sample E is transferred to the register. The processor is transferred to the processor 9. From this moment on, the device becomes active and exchanges data with the RAM in direct memory access mode. The cycle consists of two cycles. In the first cycle, the device exposes the address of the RAM cell to the trunk, in the second cycle the data is transmitted (or received J. The device exposes the main to the trunk from the output of the adder 7 through the first input of the switch 10, and the data is exposed in the general case from the output of block 8. The essence of the fast Walsh transform is that the basic operation is cyclically performed, the result of which is sent to the address of operand A, which we will call the upper operand, and the result of the subtraction is sent to the address of the operand B (lower operand). Addresses of the operands are formed according to the algorithm graph (Fig. 41. First we show the operation of the device on one basic operation, and then we show how the device proceeds to the next operation inside the iteration, as well as from iteration to iteration. Running one The basic operation consists of three cycles of operation of the device.In the first cycle, a cycle of accessing the computer's RAM to select the upper address A is formed. For this, the processor 9 sets for the block 5 the sign of the upper address, according to which the block 5 at the input of the adder 7 ropuskaet current counter value 1, for example i. This address is an absolute address, in the second and fourth variants it is directly fed to the address bus of an autonomous unit 8, and in those variants that work with a computer memory, it is arithmetically summed from the address of the base on register 6 and from the output of the adder 7 through the switch 10 is fed to the trunk. The data at this address is selected from the computer RAM and input 11 is entered into the internal register 9.1 of the processor 9. This completes the first clock cycle. In the second cycle, the lower operand is selected. But in this case, block 5, based on the basis of processor 9, forms an absolute address in the form of a sum over trios 2 of the current value of counter 1 (the address of the upper operand) and the unitary code of the iteration number, i.e. at the j iteration, the lower-case operand is represented as i ® 2. The lower operand is entered into register 9.1 of processor 9. But this clock is completed by sending the result of the subtraction to the address of the lower operand, i.e. In this tick, RAM runs in the Input-Pause-Output mode. In the third cycle, the .9 processor recovers the sign of the upper operand, which is used to record the sum of the operands. At the end of the basic operation, the processor 9 increments the value of the counter 1 by one and. proceeds to the next operation. Due to the fact that the upper and lower operands are elements of the same array and these elements at the iteration must participate only once in the basic operation, the linear order of choice of operands from the array is violated, and the length of the group of upper (respectively, lower) operands, located in consecutive memory cells, depends on the iteration number. This feature of the location of the operands is well seen on the algorithm graph. (Fig. 4), therefore, the need to reset the counter 1 arises, the essence of which is that the counter 1 enters the address of the lower table of the basic operation, after which the situation occurs to reset the counter 1, only after that counter 1 is incremented by unit We now show how the transition from iteration to iteration begins, hack as a solution to this moment is one of the essential distinguishing features of the proposed solution. In the prototype, the transition to the next iteration is performed when the overflow signal of counter 1 is created, according to which the iteration counter 4 changes its state. But in order to control the moment of transfer, which depends on the sample length, the sample length register 2 and switch 3 are entered. At that, the transfer signal from counter 1 to counter 4 pro -... goes through switch 3. And since the information the inputs of the switch 3 are connected to the outputs of the bits count Phage.}

/ 2 ticks 1 whose numbers correspond to the sample length by opening the corresponding channel of the switch 3, the output of which signal overflows not only the value of the counter “i but also clears the counter 1 itself, it is possible to control the transfer moments and, therefore, to effectively use the device on transformations of arrays with different number of elements (but a multiple of degree 2. Selection of the channel of switch 3 is carried out by the value of register 2, in which the sample length is located. In the proposed case, when counter 1 is equal to 2, the output A switch appears in the switch, for which the iteration counter 4 is incremented by 1 and the counter is cleared.Thus, the introduction of these blocks and connections will allow the device to expand its functionality by working on an array of different lengths.

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Claims (3)

1. A device for calculating the Walsh transform, containing the first switch, the first and second registers, the information outputs of which are connected respectively to the first and second information inputs of the arithmetic unit, the information output of which is connected to the information input of the Hatch memory, the control input of which is connected to the output of the first discharge of the first a permanent memory unit, the output of the second and third bits of which are connected to the clock inputs, respectively, of the first and second register (ditch, information inputs which are the information inputs of the device, the fourth-digit output of the first block of read-only memory is connected to the clock input of the address counter, the address_input of the first block of read-only memory is connected to the information output of the counter, the clock input of which is connected to the output of the clock generator, the trigger input of which is the device start input , the second block of read-only memory, an iteration counter, which means that, for the purpose of expanding the field of application by processing sequences arbitrarily length, the base register, the second switch, the adder and the sample length register are entered, the information output of which is connected to the control input of the second switch, the output of which is connected to the input of zeroing the address counter and the clock input of the iteration counter, the information output of which is combined with the information ·! the output of the address counter and the fifth-digit output of the first read-only memory block and is connected to the address input of the second read-only memory block, the first information output of which is connected to the information input of the address counter and connected to the first input of the adder, the output of which is connected to the control input of the first switch, the information input which is combined with the information outputs of the first and second registers and connected to the information output of the memory block, the second information, the output of the second block, constant Amyati ·: is connected to the installation input of the address counter, the second adder input is connected to the information output of the base register, the information input of which is combined with the information input of the sample length register and the information inputs of the first and second registers, and the output of the first switch is the information output of the device. 2. A device for calculating the Walsh converter, comprising a first switch, first and second registers, the information outputs of which are connected respectively to the first and second information inputs of the arithmetic unit, the information output of which is connected to the information input of the memory unit, whose control input is connected to the output of the first discharge of the first .SU. „1075269 block of read-only memory, the outputs of the second and third bits of which are connected to the clock inputs of the first and second registers, respectively, information whose inputs are information inputs of the device, the fourth-digit output of the first read-only memory block is connected to the clock input of the address counter, the address input of the first read-only memory block is connected to the information output of the counter, the clock input of which is connected to the output of the clock generator, the trigger input of which is the trigger input devices, the second block of read-only memory, iteration counter, characterized in that in order to expand the scope by processing sequences of processes of arbitrary length, the base register, the second switch, the adder and the sample length register are entered into it, the information output of which is connected to the control input of the second switch, the output of which is connected to the input of the address counter zeroing and the clock input of the iteration counter, the information output of which is combined with the information output of the counter address and the output of the fifth category of the first block of read-only memory and is connected to the address input of the second block of read-only memory, the first information output of which is connected to the information ^! the input counter of the address and is connected to the first input of the adder and the address input of the memory block, the output of the adder is connected to the control input of the first switch, the information input of which is combined with the information inputs of the first. th and second registers and is connected to the information output of the memory block, the second information output. the second permanent memory block is connected to the installation input of the address counter, the second adder input is connected to the information output of the base register, the information input of which is combined with the information input of the sample length register and information inputs of the first and second registers, and the output of the first switch is the information output of the device. 3. A device for calculating the Walsh transform, containing the first switch, the first and second registers, the information outputs of which are connected respectively; with the first and second information inputs of the arithmetic block, the information output of which is connected to the information input of the memory block, the control input of which is connected to the output of the first the discharge of the first block of read-only memory, the outputs of the second and third bits of which are connected to the clock inputs of the first and second registers, respectively, information input which are the information inputs of the device, the fourth discharge output of the first read-only memory unit is connected to the clock input of the address counter, the address input of the first read-only memory unit is connected to the information output of the counter, the clock input of which is connected to the output of the clock generator, the start input of which is the device start input, the second block of read-only memory, an iteration counter, revealing that, in order to expand the scope by processing sequences of arbitrary lines, a sample length register is entered into it, the information output of which is connected to the control input of the first switch, the output of which is connected to the input of the address counter zeroing and the clock input of the iteration counter, the information output of which is combined with the information output of the address counter and the fifth digit output of the first read-only memory block And connected to the address input of the second block of read-only memory, the first information output of which is connected to the information input of the address counter and the address input of the memory block , the information output of which is connected to the information inputs of the first and second registers and is the information output of the device, The second information output of the second permanent memory unit is connected to the installation input of the address counter. The information input of the sample length register is combined with the information inputs of the first and second registers.