SU1069176A1 - Multi-channel communication system - Google Patents

Abstract

A MULTI-CHANNEL COMMUNICATION SYSTEM containing a clock pulse generator, a first and second elastic memory blocks and an adder on the transmitting side, and a clock pulse generator whose input is connected to the input of a channel separation unit and the first and second elastic memory blocks on the receiving side reception, the inputs of which are connected to the corresponding outputs of the channel separation unit, characterized in that, in order to increase the capacity of the communication channel, serially connected The first prohibition element, the first key, the second prohibition element and the second key, the output of which is connected to the first input of the adder, the second input of which is connected to the first input of the second prohibition element, the second input of which is connected to the output of the first prohibition element, the first input of which is connected to the third input the adder, the second input of the first prohibition element is connected to the output of the clock pulse generator, the second input of the first key is connected to the output of the first block of elastic memory, and the second input of the second key is connected to the output the second block of elastic memory, and at the receiving side, a follower "S but connected third and fourth (L barring elements, the output of the receiving clock pulse generator is connected to the first input of the third barring element, the second input of which is connected to the corresponding output of the channel separation unit, The control input of the second receive elastic memory block is connected to the output of the fourth prohibition element, the second input of which is connected to the input of the first from the receive elastic memory block, the control input of which Go is connected to the output of the third element of the ban. but

Description

The invention relates to telecommunications and can be used in multiple access systems for combining asynchronous multi-priority message flows presented in binary form.

A multichannel communication system is known, which includes buffer storage units, speech detectors, cy and apop and channel separation unit 1.

A disadvantage of the known multi-channel communication system is the incomplete use of the communication channel capacity.

The closest technical solution to the invention is a multichannel communication system, comprising a clock generator on the transmission side, a first and second elastic memory blocks and an adder, and on the receiving side a clock pulse generator, whose input is connected to the input of the channel separation unit, and the first and second elastic receive memory blocks, the inputs of which are connected to the corresponding outputs of the channel separation unit .121.

A disadvantage of the known multi-channel communication system is the low efficiency of use of the communication channel capacity due to the necessity of introducing an increased clock frequency,

The purpose of the invention is to increase the capacity of the communication channel.

The goal is achieved by the fact that a multichannel communication system containing, on the transmitter side of the clock generator, the first and second blocks of elastic memory and an adder, and on the receiver side a clock pulse generator, the input of which is connected to the input of the channel separation unit, and the first and second elastic receiving memory blocks, the inputs of which are connected to the corresponding inputs of the channel separation unit, are in series connected on the transmitting side the first prohibition element, the first key, the second element nt prohibition and the second key, the input of which is connected to the first input of the adder, the second input of which is connected to the first input of the second prohibition element, the second input of which is connected to the output of the first prohibition element, the first input of which is connected to the third one in the stroke of the adder connected to the output of the clock, the second input of the first key

connected to the output of the first block of elastic memory, and the second input of the second key is connected to you: the second block of the elastic memory, and the third and fourth prohibition elements are connected in series on the receiving side, the output of the generator of clock pulses connected to; the first entry of the third element of the ban,

the second input is connected to the output of the channel separation unit, the control input of the second receive elastic memory unit is connected to the output of the fourth prohibition element, the second input of which is connected to the input of the first elastic memory unit, the control input of which is connected to the output of the third element ban.

FIG. 1 shows the structural electrical circuit of the transmitting part of the multichannel communication system of FIG. 2 is a structural electrical circuit of the receiving part of the multi-channel communication system.

The multichannel communication system on the transmission side (Fig. 1, the clock pulse generator 1, the first elastic memory block 2, the second elastic memory block 3, the first prohibition element 4, the first key 5, the second prohibition element 6, the second key 7, the adder 8, and at the receiving side (Fig. 2) - the generator 9 clock pulses of reception, block 10 channel separation, the third element

.11 prohibition, the first block 12 of the elastic memory of reception, the fourth element 13 of the ban, the second block 14 of the elastic memory of reception.

The multi-channel communication system works in the following way.

On the transmitting side, the generator 1 clock pulses generates a sequence of pulses with a period equal to the duration of the elementary symbol of the channel of the highest priority. These clock pulses arrive at the first input of the first element 4, to the second input of which signals of the highest priority channel are supplied, which also go directly to the first input of the adder 8. The first element 4 eliminates the clock pulses corresponding to the active (single) messages of the highest priority channel and its output is formed by a sequence of pulses applied to the control input of the first key 5 and to the first input of the second element 6 of a lower priority channel. At the moments of action of the control clock pulses, the first key 5 passes the signals of the second priority channel, which are removed from the output of the first block 2. These signals are directly fed to the second input of the adder 8, as well as to the second input of the second element b, which is from the sequence of clock pulses from the output the first element 4 eliminates the clock pulses corresponding to the active (single) parcels of the channel of the second priority. The sequence of clock pulses thus formed is fed to the control input of the second key 7. At the moments of action of these control pulses, the second key 7 transmits signals of the third priority channel, which are removed from the output of the second block 3, the signals from which are fed to the third input of the adder 8.

At the receiving side, the received group information flow is fed to the input of block 10 and synchronized to the input of generator 9. Thus, the clock pulses generated by the generator 9 are phased by the received signal and fed to the first input of the third element 11

Block 10 selects the active sendings of information channels based on distinctive features and distributes them to independent outputs. The signals of the highest priority channel are directly connected to the output of the device, since the position of the active sendings of this channel corresponds to their true position, and the pause between them are passive (zero bursts). At the same time, the active parcels of the channel of higher priority are fed to the second input of the third element 11 to eliminate the corresponding clock pulses. At the output of the third element 11, clock pulses appear corresponding to the signals of the passive pauses (zero bursts) of the highest priority channel. These clock pulses are applied to the read control input control unit 12 and the first input of the fourth element 13, and since the active signals of the second priority channel are active at the input of the first block 12, the second priority channel information is formed at the output of the first block 12. the read control pulses from the first block 12 retrieve active (single) premises, and in their absence, passive (zero) messages are retrieved. The second input of the fourth element 13 is supplied with the active sendings of the second priority channel, at the moment of which in the fourth element 13 the clock pulses acting on the first input are eliminated. The clock pulses thus generated from the output of the fourth prohibition element 13 are fed to the read control input of the second channel block 14 of the last (third) priority. To the input of the second block 14, the active sendings of the channel of the third priority are fed, and the output of this block forms the information of this channel. The principle of forming this information is similar to how it was done in channels of higher (second) priority.

The use of the invention allows the most efficient use of the bandwidth of the communication channel as a result of using all the passive time slots to transmit information.

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Claims (1)

A MULTI-CHANNEL COMMUNICATION SYSTEM containing a clock pulse generator, first and second elastic memory blocks and an adder on the transmitting side, and a reception clock generator, the input of which is connected to the input of the channel separation unit, and the first and second elastic reception memory blocks, on the receiving side the inputs of which are connected to the corresponding outputs of the channel separation unit, characterized in that, in order to increase the throughput of the communication channel, the first electrical inhibit, the first key, the second inhibit element and the second key, the output of which is connected to the first input of the adder, the second input of which is connected to the first input of the second inhibit element, the second input of which is connected to the output of the first inhibit element, the first input of which is connected to the third the adder input, the second input of the first inhibit element is connected to the output of the clock generator, the second input of the first key is connected to the output of the first block of elastic memory, and the second input of the second key is connected to the output of the second block of electronic of the primary memory, and on the receiving side the third and fourth inhibit elements are connected in series, the output of the receive clock is connected to the first input of the third inhibit element, the second input of which is connected to the corresponding output of the channel separation unit, the control input of the second elastic reception memory unit is connected to the output of the fourth prohibition element, the second input of which is connected to the input of the first block of the elastic reception memory, the control input of which is connected to the output of the third element nt ban. Q