SU1056130A2 - Numerical controller - Google Patents

Abstract

DIGITAL DOWNLOAD by auth.St. 1G, which is also distinguished by the fact that, with the aim of expanding 11i functionality, a nonlinear converter has been introduced into it, the output of which is connected to the second input of the tenth element And, the input. reset, the first and second sync inputs are respectively with the first, second and sixth outputs of the synchronization unit, the first and second control inputs are respectively with the first outputs of the third and fourth triggers, n (} and the first and second information inputs of the nonlinear converter are connected to the corresponding digital controller inputs.

Description

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00 The invention relates to automation and can be used in control systems of various dynamic objects, for example, in automatic control systems by the technological processes at power plants. St. ff a digital controller is known that contains a setting block consisting of the first and second registers, the sign unit, the first And element, the second And element, the synchronized block in series, the third element And the first trigger, the fourth And element, the first block of the additional code , first adder, second adder, third register, delay element, second block of additional code, fifth ele. And, the first element OR, the fourth register, the sixth element AND, are successively connected to the seventh element AND, the second trigger, the eighth ele. And the third block of the additional code, the third trigger, the ninth AND element, the second OR element, the fourth trigger, the tenth AND element, the third OR element, the fifth register, the second input of which is connected to the second inputs of the first, are connected in series the second, third, fourth registers and the sixth output of the synchronization block, the first output of which is connected to the reset inputs of the first, second adders, first, second, third blocks of the additional code with the second inputs of the first, second, third three second exit with the first input of the seventh element And the third exit with the first input of the third trigger, the fourth exit with the second input of the fourth trigger, the fifth exit with the third input of the sign unit, the second output of which is connected to the second inputs of the first and second blocks additional code, the third output - with the second input of the third block of the additional code, the second input with the output of the second adder, the second. whose input is connected to the output of the second OR element, the second input of which is connected to the output of the first element AND, the first input of which is connected to the output of the delay element, the second input to the second output of the third trigger, the output of the third register cor is single with the second input In addition, the first output of the fourth trigger is connected to the second input of the fifth And element, the second output to the first input of the second And element, the third input of the ninth And element and the second input of the sixth And element, the output of which is connected to the second input of the firstelement OR exit | expensively connected to the second input of the third element, AND, the output of the second element, AND connected to the second input of the third element OR, the output of the third block of the additional code is connected to the second input of the first adder, the output of the first register is connected to its first. the input and the second input of the fourth element And, the output of the second register t, is connected to its first input and the second input of the eighth element And, the output of the third element OR is connected to the second input of the seventh element And, the output of the fifth register is connected to the second input of the second element And, the first the output of the synchronization unit is connected to the first input of the fourth trigger, the second output of kdTOporo is connected to the third input (the first element I G1. i The disadvantage of the known digital controller is limited functionality, because it has only the linear laws of regulation are established. The aim of the invention is to expand the functionality of the digital-to-controller. This goal is achieved by introducing a non-linear converter into the digital controller, the output of which is connected to the second input of the tenth And element, the reset input, the first and second synchronization inputs — with the first, second, and sixth outputs of the synchronization unit, respectively; the first and second control inputs — with the first outputs of the third and fourth triggers, respectively, the first and second The information inputs of the non-linear converter are connected to the corresponding modes of the digital controller. Fig. 1 shows a structural cxeMi digital controller; in fig. structural diagram of one of the possible options for the implementation of the block of the symbol and the synchronization block; FIG. 3 is a structural diagram of one of the possible options for implementing a non-linear conversion unit. The digital controller contains a setup block 1 consisting of two registers 2 and 3, three registers-6, two sum maters 7 and 8, a block of 9 characters, a synchronization block 10, three blocks 11–13 of an additional code, four triggers a nonlinear converter 18 , 5 three elements OR, ten elements AND 22-31, element 32 delay.

The digital controller has the info 4 MOHHue tires: input 33 and 3 and one output 35, as well as sign buses: input- About 36 and 37 and one output 38. Registrars 2-6 have a fieldbus and data entry groups, respectively.

The sign unit 9 (FIG. 2 I contains two two-digit registers and 5 rdvig, four-bit register t, five elements EXCLUSIVE OR, four elements AND 52-55, two elements OR 5b and 57, input bus 5B and two output buses 59 and 60, bus groups 61-20 63 for controlling and entering data into registers -46 respectively. Tires 36-38 of character block 9 are respectively the first, second sign input tires and the output tire of the sign 25 of the digital controller.

Synchronization unit 10 (Fig. 2) contains a 6k clock pulse generator, the first divides frequency 65 and 65, delay element 66, t igger 67 with a counting input, second frequency divider 68, output buses 69-73.

The nonlinear converter 18 (FIG. 3) contains three registers, adder 77, trigger 78, five switches 79-83, two 8V and 85 delay elements, two AND 86 and 87 elements, HE 88, two buses 89 and 90 controls. , output bus 91, control group 92-9t, for entering data into registers, respectively.

The digital controller works in the following manner.

 Regulatory impact for each. When the iTO control loop is formed, it is formed according to the recurrence relation

-, BZb2CYi. Y XirXziVfn

where the value of the first and second input values of the digital controller, respectively, in each

1st control loop; Yj. the value of the converted mismatch on the 1-1 and l-2nd control cycles;

Z, ZjM values of regulating action on i, i-1 and i-2nd control cycle;

A, B, C, and D are constant coefficients, the values of which depend on the type of control law, pitch, time quantization, gain, and constant time.

Adjustment of the digital regulator is realized by setting the constant coefficients A, B, C, and D and the initial conditions Zf,, Z,, -, and Y, which, in particular, can be zero.

A preliminary calculation of the constant A, B, C, and D coefficients for frequently implemented control laws is performed according to the formulas given in the table, where K is the gain factor; T -1 T, T,, Td - constant time; h is the quantization step in time chosen from the conditions of a given accuracy.

The digital controller operates with binary variables, for which relation (1) takes the following form n-1.

 (in- / V2 .- j, "J

v, E: 2-

.y..i

 jrl

where the index j denotes the; -th bit of the two-variable variable of the corresponding value, for example, Zj: j is a binary variable of the j-ro bit of 2c

The number of bits of the representation of the quantities is Vi-1 bit, the n-th bit is sign.

The digital controller setting is performed as follows.

Registers 2 and 3 of tuning block 1, each containing 2p bits, are written over tires 35 and AO, respectively, for example, from a digital centralized management computer or from a digital task controller in a control room, binary U-bit codes for the absolute values of the coefficients A, B , C and D, respectively, which correspond to the required linear integral-differential control system (table). To record information into registers 2 and 3, the output signals of the synchro 10 block (unification) are used. Signs of the coefficients A, B, Cyr are recorded on a group of buses 63 in a four-bit register +6 of the E-character block. In the case of non-zero initial conditions, register k, which contains n | | bits and is supplemented with delay element 3 to n bits, is written in group T OR OR additional code, if 2 .. O, the binary code of the initial condition 2 | „; In registers 5 and 6, containing 2n-1 bits each, write n-1 bit codes of the absolute values of the initial conditions. | Z | .2}) respectively In register 7 nonlinear converter 18 write n-1 bit binary code of absolute value and initial conditions (Y.lno group of tires 92 of registers 7 and 76 of the nonlinear converter 18 contain bit and are complementary elements 84 and 85 to delay Correspondingly .venno prazr rows. A register 75, containing n bits, and a register 7b of a nonlinear converter 18 are reset on a group of buses 93 and 9, respectively. . Significantly in the zero state, the Signs of the beginning; 1 of the Z conditions and are written over the bus group B1 into a two-bit register k of the block 9 signs of the Sign of the initial conditions. And. | .2 are written over a group of buses B2 into a two-bit register 45 of the block 9 characters. The need to set initial conditions arises in the case of transfer of control to the digital controller from the digital computer of the centralized control. In case of autonomous use of the digital controller, its implementation is only setting the absolute values of the coefficients in block 1 settings and the signs of the coefficients in the block 9 characters. The clock signal generator 64 of the synchronization unit 10 generates a sequence of frequency pulses at its sixth output, which is fed to the synchronization inputs of registers 2-6, and is also divided by divider b5 n times and then delayed by delay element 66 by one period of the clock frequency. i; i. at the output of divider 65 (the first output of the synchronization unit 10 / sets the device operation cycles, and the pulse sequence at the output of the set-up unit 66 (the second output of the synchronization unit 10) synchronizes the first device operation cycles with the h / f period. Trigger b7 performs division into two frequencies of the output sequence and pulses of the delay element 66, forming a sequence of pulses of frequency f / 2p at the third output of synchronization unit 10 This sequence is divided by divider 68 into --I times, at the output of which the fourth output of unit 10 synchronization, a sequence of pulses of frequency f / 2p (p-1) is formed, the period of which determines the time of one control cycle. In the initial state, the triggers 1} -J7 are in the zero state. The control signal generation cycle begins after the trigger is set 17 into one state by the pulse of the fourth output of the synchronization unit 10 The direct output signal of the trigger 17 opens the elements AND 29 and 31 and the signal of its inverse output closes the elements 22, 23-, 28 and 30. The binary code of the initial condition Z | razr a, is shifted from register 4 through delay element 32 by one cycle, block 13 of additional code per bus 35 and through elements 31 and OR 21 to register 5, in which in this time the binary code of the initial condition Zfr2 is shifted from the highest bits to n The 1 least significant bits, B.POK 13 of the additional code, is controlled by the signal of the second output of the block of 9 characters so that the direct code passes without change, and the additional code of register 4 is converted into the direct code. Thus, in n, the high bits of register 5 are written in the binary code of the absolute value of the initial condition | 2 I. The signal of the lower bit of the value Z:;. I from the output of the element OR 21 enters the input of the element AND 25i to another input which receives a pulse of the second synchronization unit 10, In cny-ichae a single low-order signal of magnitude | 2: I element And 25 triggers, and the pulse of the second output of the synchronization unit 10 sets trigger 15 to one state. The binary code of the initial condition fy.) Is shifted, starting with the low-order bit, from the output of the register 74 of the nonlinear converter; 18 and, through the delay element 84, the And 29 elements

and or 20 is written in the high order bits of the register 6 "In register 6, this is the time of the binary code of the initial

.conditions | y, 2 shifts from the higher bits to n-1, the lower bits,

The signal of the lower bit of the magnitude | V. | From the output of the element OR 20 is fed to the input of the element And 2, In the case of a single signal of the lower bit of the magnitude | 5 -1 element AND 2 pulses the second output of synchronization unit 10, and the trigger 16 is set to one,

. The triggers 15 and 16 in the single state open the elements AND 26 and 27, respectively, through which the binary codes of the coefficients L and C, respectively, are shifted sequentially from the outputs of the registers 2 and 3 of the setting block 1 sequentially, starting with the least significant bits.

The coefficient L enters through the block 11 of the additional code to the first input of the adder 8 in the forward or additional code, depending on

in addition, the product AZ, the signal of which acts on the second output of the block 9 characters. Signal Signal Value

, A2 is formed by the EXCLUSIVE OR 8 element, to the inputs of which signals of the first bits of registers k and 46 are received, where the signs of the values 2 and A are stored, respectively

The signal sign of the magnitude from the output of the EXCLUSIVE OR element enters through the AND 52 and OR 56 elements to the bus 59 of the second output of the block 9 characters.

Coefficient C is fed through block 12 of the additional code to the second input of the adder 8 in the forward or supplementary code, depending on the product's sign CY, the signal of which is formed by the EXCLUSIVE OR 50 element, to the inputs of which the post goes the signal of the sign of Y with the output of the first bit. register 5 and the sign signal of the coefficient C from the output of the third bit of the register k6 of the block 9 characters .:

The sign signal of the value of the CV.-j e-output element is EXCLUSIVE or 1E 50 or more. the element And 5 open signal inverse output of the trigger 67, and the element OR 57 is supplied to the third output of the block 9 characters.

Thus, the inputs of a serial one-bit binary adder 8 are received in a forward or additional code sequentially in time, starting with the least significant bit, the binary codes of the coefficients A and C, the algebraic sum of which goes to the second input of the sequential one-bit binary adder 7 At this time, the signal at the first input of the adder 7 is a logical zero signal, since the elements 22 and 23 are closed by the signal of the inverse output of the trigger 17,

The algebraic sum of the coefficients A and C from the output of the one-bit sequential adder 7 is written, starting with the least significant bit, into the registry j,

At the end of each rt-ro clock, the signal of the first output of synchronization block 10 blocks the carry chains of adders 7 and 8, and also resets blocks 11-13 of the additional code to the initial state.

After p clock runs after setting the trigger 17 to the one state, the flip-flops are reset to the zero state by the pulse of the first output of the synchronization unit 10. The trigger 17 in the zero state closes And 29 and 31 elements with a direct output signal and opens And 22, 23, 28 and 30 elements with an inverted output signal. Elements 28 and 30 connect the outputs of registers 5 and 6 to their inputs, respectively. Circulation circuits of codes in shift registers 5 and 6 are closed through elements 28 and 30, respectively.

Element And 23, open signals inverse outputs of the triggers 1A and 17, connects the output of the register C through the element 32 delay to the first input summat of the matrix 7, which ensures during the following cycles the receipt of the binary code of the algebraic sum of coefficients (A + SK

L,

In the next clock cycle, after trigger 17 returns to the zero state, the outputs of registers 5 and 6 shift the bits of the magnitude | z.2 and | Y, respectively,

In the case of single codes in the lower bits of the values | 2-.2} and (And 25 and 2 elements are triggered by the second output pulse of the synchronization unit 10, which sets the triggers 15 and 16, respectively, to the single state. The signals of the direct outputs of the triggers 15 and 16 open elements AND 26 and 27, respectively, through which the settings of registers 2 and 3 of block 1 shift the binary codes of the coefficients B and D, respectively. The binary codes of the Vir coefficients are converted by the corresponding blocks 11 and 12 of the additional code and follower is coming However, starting with the low-order bit, in a direct or additional code to the inputs of the adder 8, the conversion is controlled, by the additional code blocks 11 and 12, using the signals of the second and third outputs of the block 9 characters, respectively. The sign signal is generated by the element EXCLUDED OR 9 The inputs of which receive the outputs of the second bits kk and 6 registers of the block of 9 characters, where the signs of the values of 2.2 are stored, respectively. From the output of the ISK / EXT element OR if9, the sign signal of the value goes through the elements 53 and OR 5 to the bus 59 About the output of block 9 of the sign. The signal of the sign BY.o is formed by the element EXCLUSIVE or 51 by the signals of the outputs of the second and fourth bits of the registers 45 and d 46. block 9 of the sign o From the output of the element EXCLUSIVE | ITS OR 51 through the elements 55 and 57 to the bus 60 of the third output of block 9 of the sign “Direct or additional code of the algebraic sum of the coefficients B and and from the output of the adder 8 goes to the second input of the adder 7, to the first input of which from the output of the register 4 through the delay element 32, elements And 23 and ILK 19 shift is the binary code of the algebraic sum of the coefficients L and Co With the output of the adder 7 the binary code of the algebraic sum of the coefficients A, B, C J) is written into the register 4 ". Thus, for 2 cycles after the start of the cycle, register 4 accumulates the algebraic sum of the coefficients A, B, C and B, after which the trigger is set to one state by the pulse of the third output of the synchronization unit. The trigger 14 in the single state opens the element I 22 by a direct output signal and blocks the element 23 by an inverse output signal. By the time the second paap is shifted and the algebraic sum of the coefficients A, B, C and B from the register 4 output, the I 22 connects the output Register 4 to the first input of the adder 7-B. this time from the outputs of registers 5 and 6, the second bits of the value of | 2 are shifted. j and SU I respectively o In the case of single codes in the second bits of the magnitudes | 2 1.1 and | U.-, the elements AND 5 and 24 are triggered, the output signals of which set the triggers 15 and 16 to one state. The binary codes of the coefficients A and C on the binary. Variables of the second bits of the values 2) and | Y.} are respectively converted into a direct or additional code by blocks 11 and 10 respectively. Then these codes are summed by the adder 8, the sum signal of which is summed by the adder 7 s the binary code of the algebraic sum of the coefficients A, B, C, and I) shifted from the output of register 4, starting with the second bit. Therefore, setting trigger one to 14 causes the accumulated sum of coefficients in register 4 to be shifted by one bit, ensuring that the EMT performs a multiply operation by two. After p clock ticks after the trigger 14 is set to one, the signal of the first output of the synchronization unit 10 returns the trigger 14 to the zero state, in which the register output 4 is enabled by the output 23 of the register 4 via the clock delay element 32 to the first input of the adder 7 at this time the second input of the adder 7 from the output of the adder 8 receives the binary code of the algebraic sum of the product of the coefficients B and p and the binary variables of the second bits of the values | 2 2 I) -2 f. accordingly, which is formed in the same way as in the previous G cycles, the algebraic sum of the product of the coefficients A and C into binary variables of the second bits of the |) IY values was formed. the corresponding Adder 7 sums the sum of the coefficients in register 4 with the algebraic sum of the product of the coefficients B and D by the binary variables of the second pai. of the values of the values | E; C; I and correspondingly, and the result of summation is recorded In pej-4P 4 o In the future, the formation of the regulatory action is performed in a similar way. Every 2n, cycles in the ring, registers 5 and 6, containing 2 (p-1I bit,

there is a shift. output signal relative to the output signals of the synchronization unit 10, which leads to the coincidence at the inputs of the elements And 25 and 2 with the pulse of the second output of the synchronization unit 10 the following bits of the sizes lZ | .., l, | Y.J,} 2-j | .. Switching the register of A codes from the bits of the trigger circuit with a trigger for 1 hour (from the output of the delay element 32 to the. –1 bit (from the register output) provides a shift of information in the register A by one bit) Regarding the output signals of the synchronization unit 10 ,

v

After 2n (n-1 I clock after the beginning of the cycle of forming the control signal in register 4 is accumulated in Fyum or additional code and high-order bits of the output value Z,

/ sign h-th bit with output. yes adder 7 comes in second

the stroke of the block 9 of the sign (bus 58) and shifted by the signal acting on the bus 72 of the block 10 of synchronization, in; the first bit of the shift register, from the first bit of which at this time to the second bit is shifted, the sign is.

masks Z.; ...

By the beginning of the second cycle of forming the control signal, in P-1, the higher bits of registers 5 and 6 contain binary codes of values

.,) and | Y. respectively,

The generation of the control signal in the second and all subsequent cycles is performed in a similar way, but with new initial conditions that are automatically generated in the previous cycle,.

A nonlinear converter in each control cycle from binary codes: absolute values of the input values Ve / Lychin | X; - | and, which arrive successively in time, nam-, nal from lower-order bits, to tires 33 1 and 3, respectively, form the binary code of the absolute value of the product | Y, ({X 21 I as follows;

In the first: n control cycle cycles, when the t7 trigger is & .

: single state, switches 8t and 82 connect busses 33 and 3 to informational inputs of registers 75 and 76, respectively. Under the action of them, the pulses of the sixth output of the synchronization unit 10, which act on the bus 73, binary codes of the input quantities and | X2, - | are shifted to the registers 75 and 76, respectively. At this time, the bus 89 has a signal of the logical unit of the direct output of the trigger C, which, through the NOT 88 element, blocks the AND 87 element, the Trigger 78 is in the zero state and blocks the AND 86 element, the Switch 79, by the action of the logical unit signal on the bus 90, which is acted upon by the direct output signal of the trigger 17, connects the input of the adder 77 to the bus logical zero ,

Thus, a binary code is entered into register 75 for n bits, X.,) b, and in register 76 current-1 bit, which is supplemented by a delay element 85 per cycle up to n bits, the CAMERA code | X2il is entered.

In the following steps, the And and 17 triggers are in the zero state. The logical zero signal of the direct output of the trigger 17, acting on the bus 90 switches the switches and 82 in such a way that the switch 79 connects the output of the switch 80 to the input of the adder 77, the switches 81 and 82 connect the information inputs of the registers 75 and 76 respectively to the output of the register 75 and the output of the switch 83, respectively. The logical zero signal of the direct output of the trigger 14 ,. acting on the bus 89, removes through the element NOT 88 the blocking of the element AND 87 and switches the switches 80 and 83 in such a way that the switches 80 and 83

connect their outputs to the outputs of the elements 84 and 85 of the delay, respectively. This state of the switches 79t 83 provides the following: connecting the information input of the register 74 to its output via the adder 77, switches 79 and 80 and the delay element 84, connecting the information input of the register 75 to its output via the switch 81, connecting the information input of the register 76 to its output through switches 82, 83 and delay element 85. Such switching of circuits of binary codes from the outputs of registers 74-76 to their inputs provides a dynamic mode of information storage. If in the lower order of a value.} X.2,) | contains 4 unit codes, the logical unit signal at the output of the switch 82 opens the element AND 87 at the moment of the pulse, the second output of the synchronization unit 1310 The trigger trigger 78 on the bus 70 in a single state by the output signal of the element 87 at time P; that com. The direct output signal of the trigger 7B opens the element AND 86, through which the input of the adder 77 is shifted, beginning with the least significant bits, to the binary code of the value JX I from the output of the register 75 In n cycles the binary code. The values | X I are rewritten from the output of the register 75 through the switch 81, the element 86 and the adder 77 into the register, the register 7 in the next steps on the bus 89 sets the signal of the logical unit of the direct output of the trigger 14, which blocks through the element 88 , element 87 and connected via switches 80 and 83 outputs of registers 7 and 76 to inputs of switches 79 and 82, respectively. The circulation cycle of codes in registers 7 and 76 is shortened by one cycle, which ensures a shift of codes by one bit in registers 74 and 76 with respect to the code in register 75, the code circulation cycle, in to torus still is n cycles. Thus, the signal of the logical unit on the bus 89 direct output of the trigger 14, acting in odd n cycles every 2p cycles, provides a shift of information in registers 74 and 76 with respect to the information in register 75. During even n cycles, every 2 clock cycles on the bus 89, the logic zero signal of the trigger 14, which removes the blocking of the element AND 87 through the element HE 88, acts at the inputs of the element 87 and coincides with the second output pulse of the synchronization block 10, acting on the bus 70 second order I, coming from the output of the switch 82. The trigger 78 is set to one state on the clock by the output signal of the element And 87 and removes the lock of the element 86, through which the input of the adder 77 from the output of the switch 81 arrives at the lower level, binary The code of the value | Xii | "At this time, the other input of the summator 77 through the switches 79-80 and the delay element 84 is shifted from the output of the register 74 to the binary code of the value X, starting from the second bit, since during the previous h cycles the information in the register 7 has been shifted relative to inf Formations in register 75 Serial binary adder 77 summarizes the binary codes arriving at its inputs, and the result is shifted to register 7. Further calculations in block 18 of nonlinear transformations are carried out similarly. Thus, in register 7, during one control cycle of 2ti h-.1 | cycles accumulates the binary code of the higher bits of the product.), (., which in the first G1 clock cycle of the next control cycle is shifted from the output of the register 7 through the delay element 84 and through the bus 91 goes through the elements AND 29 and OR 20 to the information input of the register 6, where the most significant bits are written to its h At this time, the binary code of the value jY- is shifted to the lower bits in register 6, -formed by the nonlinear L1M converter 18 in the previous control cycle. In the first cycle of each control cycle, the characters are input The Xl ,. and X2 values entered on buses 36 and 37 into a character block 9 are converted by the EXCLUSIVE OR 47 element into a product sign signal, an EXPOSIVE signal acting on the bus 72 of the synchronization unit 10 is shifted to the first bit of the register 45, from which in the second bit, the sign code is the product of Denis U., formed on the previous control cycle. The binary code of the absolute value of the regulating action 12 f and the s | - its sign act on tires 35 and 38, respectively, at the beginning of each control cycle. In addition to a wide range of linear and differential first- and second-order control laws, this digital controller performs non-linear transformation on the input signals, which allows for the implementation of adaptive control laws and thereby improves the quality of control. For example, if a mismatch signal arrives at the first information input of the digital controller, and a signal proportional to the disturbance acting on the object of regulation, or the load on the object of regulation, to the second input, digital controller 15, 10 implements an integro-differential control law with a variable coefficient . gain control. If both of the information inputs of the digital controller give a misalignment signal, the digital regulator implements the integro-differential law of control over the square of the error signal, which improves the quality of control with significant error signals. If the error signal is fed to one input of the digital control, and the signal from the digital software-time device to the second input, the switchable gain of the digital controller takes its value according to the changes in the digital software-time signal signal. 0–16 The digital controller can be used to form linear and non-linear control laws of any order. In this case, several digital controllers are connected in series so that the output buses 35 and 38 each / joro of the previous digital controller are connected to one of the input bus groups 33 and 36 or 3 and 37, respectively. The remaining free input buses 33 and 36 or 3 and 37 digital controllers are used to adaptively change the parameters of the control laws, or they are connected to the buses of a logical zero or one. Thus, the wide functionality of the digital controller greatly expands its scope, which leads to obtaining a certain technical and economic effect.

Claims (1)

DIGITAL REGULATOR If 974336, distinguished by the fact that, in order to expand the functionality, c. he introduced a nonlinear converter, the output of which is connected to the second input of the tenth element And, the reset input, the first and second inputs of the clock * nieatsii - respectively, with the first, second and sixth outputs of the synchronization block *, the first and second control inputs - respectively, with the first outputs third and fourth triggers, the first and second information inputs of the nonlinear converter are connected to the corresponding inputs of the digital controller. Sae Oh>