SU1035608A1 - Three-channel majority reserved device - Google Patents

Description

The invention relates to digital computing technology and can be applied in the construction of highly reliable digital organizers. A three-channel major-but-redundant device is known that contains in each channel redundant blocks connected to the input of the control element and the first input of the NAND elements, the second inputs of the AND-NOT elements are connected to the output of the control elements 3 and the output of the NAND elements are connected to the information the inputs of the major elements, the control inputs of which are connected to the output of the control element 1P, the disadvantage of the device. And is a significant complication of the circuit (the presence of the control element in each bit and the complication of the majority ele. 1ta, and as a result, a decrease in the reliability of the device as a whole.Also known is a three-channel majority-redundant device containing indicators of channel failures, majority elements connected via serially connected first element OR, HEf element second element OR, and second element NOT to the input source Fishing. The disadvantage of this device is that the failure of two of the three channels leads to a complete failure of the entire device. The closest to the technical essence of this invention is a major-redundant device containing comparison elements, the first inputs of which are connected to the output of the majority element, the second inputs - with the source of the signal (redundant unit), and the outputs with the corresponding the indicator inputs, the switch inputs are pairwise connected to the input sources (redundant blocks), the outputs are connected to the inputs of the majority element, and the control inputs are connected to the outputs of the corresponding comparison elements 2 J. The drawback of the device is that if the second channel fails, the entire device is only operable with a probability. The purpose of the invention is to increase the reliability of trouble-free operation by ensuring the device's ability to work at any failure atom. The goal is achieved by the fact that a three-channel major-redundant device containing a major block and in each channel is the first comparison element and a redundant block whose information outputs are bitwise connected to the first inputs of the switch of the given channel and the switch outputs of each channel bitwise the bottom is connected to the corresponding inputs of the majority block; the first convolution block contains the second element of the comparison, the majority element of the control bit and and in each channel member and the second block convolution vhodb, which are connected bitwise {rezerviru- information outlets. the given block of the given channel, and the output to the first input of the first element of comparison of the given channel, the second input of which is connected to the output, the control of the discharge of the reserved block, and the output to the first input of the And element, the output of which is connected to the control input of the switch, and the second input - to the output of the second comparison element, the first input of which is connected to the output of the major element of the check bit, whose inputs are connected to the outputs of the check bits of the reserved block of each channel, the second input of the second element The sensor is connected to the output of the first convolution unit, the inputs of which are bitwise connected to the outputs of the major unit. Figure 1 shows the block diagram of the device; Fig. 2 is a schematic diagram of the majority element; fig.Z switch diagram. The device (FIG. 1) contains in each channel a redundant unit 1 with check bit 2 modulo the second convolution unit 3, the first comparison element k, the switch 5, the AND 6 element and the majority block 7 common to the three channels, the first convolution unit 8 , the second comparison element 9, the majority element 10 of the check bit. The marketing unit 7 (figure 2 of the soderite AND majority elements 11, each of which is made on the elements AND-OR, Switch 5 ((lig. 3) also contains switches T2, made on the elements AND-OR. Information outputs of the reserved block 1 in each channel is bitwise connected to the first inputs of switch 5 on this channel and to the second inputs of switch 5 on the next channel {the next channel for the first channel is the second channel, the third channel for the second channel, the first channel for the third channel, the switch outputs 5 each channel the bit is connected to the inputs of the majority block 7. The inputs of convolution block 3 of this channel are connected to the information outputs of the reserved block 1 of this channel, and the output is connected to the first input of the comparison element of its channel, the second input of which is connected to the output of the control bit of the reserved block 1 of its channel. The output of the element of comparison of its channel is connected to the first input of the element I 6 of its channel, the output of which is connected to the control input of the switch 5 of its channel, and the second input to the output of the second element This comparison is E, the first input of which is connected to the output of the majority control checkpoint 10, the inputs of which are connected to the outputs of the check bits 2 of the reserved block 1 of each channel, the second input of the second comparison element i is connected to the output of the second convolution unit 8, the inputs of which are bitwise connected to the outputs of the major block 7 The device operates as follows. When all the reserved blocks 1 are operational, the switch 5 is in the initial state, and the corresponding inputs of the major block 7 are the signals from the same-name reserved block 1 fail. The signals at the output of the cBepTj H 3 block in each channel coincide with the signal at the output of the check bit 2 of the reserved block 1, the signals at the output of the out-of-channel convolutional block 8 coincide with the signal of the majority element of the check bit 10, at the outputs elements of comparison and 9 holds signal O, elements AND 6 are closed and keep switch 5 in the initial state, if one of the redundant ones fail, blocks 1 or several faults in opposite bits of two or three of the reserved blocks 1, the signals at the inputs of the comparison elements are not equal, the output signal of the comparison element k gives the enable signal to the AND element of the corresponding channel, however, the AND element is closed, since the signals at the inputs of the comparison element 9 are identical and from the output of the comparison element 9 to the AND 6 element a prohibitive signal is issued. In case of malfunctions in the same bits of the reserved blocks 1, the signals at the inputs of the comparison element 9 also differ, the inputs of the And 6 elements of the corresponding channels will be the enabling signals, the switches 5 will switch the major element 7 to the operation of one healthy channel through two of the three inputs. The technical and economic effect of the application of this invention is to increase reliability, in particular in extending the service life of the system.

ABOUT

h about

fig

12

.J

:

Claims (1)

A THREE-CHANNEL MAJORITY RESERVED DEVICE containing a majority block and in each channel a first comparison element and a redundant block, the information outputs of which are bitwise connected to the first inputs of the switch of this channel and to the second inputs of the switch of the subsequent channel, the outputs of the switch of each channel are bitwise connected to the corresponding inputs of the majority block. the fact that, in order to increase the reliability of the device, it contains the first convolution unit 8, the second comparison element 9, the majority control discharge element 10, and in each channel, the And element and the second convolution block 3, the inputs of which are bitwise connected to the information outputs of the reserved block of this channel, and the output is to the first input of the first comparison element of this channel, the second input of which is connected to the control time output -; a row of the reserved unit, and the output is to the first input of the And element, the output of which is connected to the control input of the switch, and the second input to the q output of the second comparison element, the first input of which is connected to the output of the majority element of the control discharge, the inputs of which are connected to the outputs of the control bits of the reserved block of each channel, the second input of the second comparison element is connected to the output of the first convolution block, the inputs of which are bitwise connected to the outputs of the majority block. * 1035608>