SU1034008A1 - Time interval synthesizer - Google Patents

Abstract

SYNTHESIZER BPEMEHffiJX intervals soderzhaishy series-connected reference oscillator, a frequency multiplier and multidigit schetchyk preset and predetermined recognition state, as well as forming the input block to the input of soy .dinenny Oloka control, the first output of which is connected to the second input of the counter, the discrimination output which is connected to the input of one of the two output drivers; pulses and a second input of the control unit, different teM, that, in order to increase the resolution, a frequency mixing unit of the reference oscillator, a second frequency multiplier, a phase matching extractor and a second counter with presetting and identifying the set state were entered into it the input of the second multiplier is connected to the output of the reference generator via the frequency offset signal block of the reference generator, the phase matching block is connected to the outputs of the multipliers, and the output to the ph The second input of the control unit, the first and second Bxojw of the second counter are connected respectively (L to the output of the second and the second output of the control unit, and the identification output is connected to the fourth input of the control unit and the input of the second output driver amp & with pulses.

Description

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The time interval synthesizer is related to Hivmy / ibcHHM radio engineering devices and is designed to generate two signals with a given time delay, during calibration and calibration of time interval meters, oscilloscopes, and also for use in measurement systems. A known time interval synthesizer contains a reference frequency multiplier, a counter 5 unit for controlling the counter with presetting and identifying a given state, an input forming unit and two formers of output pulses fl}. The disadvantage of this synthesizer is its limited resolution, equal to the period of the reference signal, and low accuracy due to the fact that the maximum random error reaches the value of the period of the reference signal, and the systematic error is determined by the frequency instability of the reference oscillator signal. Also known is a time synthesizer containing a series-connected reference oscillator, a phase-controlled oscillator (a PLL oscillator) and a preset counter whose output is connected to an analog delay unit connected to an output pulse shaper, the input shaping unit is connected to a control unit that is controlled by a phase-controlled oscillator and the second driver output pulses. The disadvantage of the synthesizer is the low resolution and the limitation of the maximum value of the formed time interval. The purpose of the invention is to increase the resolution of the formation of time intervals. The goal is achieved by the fact that the time synthesizer contains serially connected reference oscillator, frequency multiplier and multi-bit counters with presetting and identifying the set state, as well as the input shaping unit connected to the input of the control unit, the first output of which is connected to the second counter input, the identification output of which is connected to the input of one of the two output pulse drivers and the second input of the control unit, has been introduced a signal frequency offset unit a reference oscillator, a second frequency multiplier, a phase matching block, and a second counter with presetting and identifying a predetermined state; the second multiplier input is connected via a frequency offset block to the output of the reference oscillator; the phase matching block is connected to the outputs of the multipliers, and the output to the third input of the control unit, the inputs of the second counter are connected respectively to the output of the second multiplier to the second output of the control unit, and the identification output to the fourth input Lok and control input of the second pulse shaper output. The drawing shows a block diagram of the proposed device. The circuit contains the reference oscillator 1, the frequency offset signal block 2 of the reference oscillator, multipliers 3 and 4 frequencies with a multiplication factor, a selection 5 - matching phase of the signals i vI, the control unit b, counters 7 and 8 with presetting and identifying the set state shapers 9 and. The output pulses and input forming unit 11 are connected to the reference generator 1 by a frequency generator 2 bias signal and a multiplier 3. Multiplier 3 and a multiplier 4 connected to the output of frequency bias 2 by their outputs are connected to a signal phase matching section 5; multipliers. Unit 5 with its output is connected to control unit b. The outputs of multipliers 3 and 4 are connected to the first inputs of the counter 7 and 8, respectively, and the outputs of the control unit 6 are connected to the second inputs of the counters. The identification outputs of the counters 7 and 8 are connected to the inputs of the control unit 6 and the corresponding driver 9 and 10 output pulses. The input forming unit 11 is also connected to the input of the control unit 6. The essence of the operation of the device is to obtain an output interval in the form of a difference of two intervals formed by two counters filled with different reference sequences. If there are two highly stable; And close in frequency signal so that. then when they are mixed, a difference signal arises with a period of fc / t, it (ti-fc / j /. Q QL The moment of crossing the zero of the difference signal corresponds to the equality of the phases or pro-phase of the compared signals. If we consider He: the time axis, the position of the x: x points along after the same number of periods of both sequences, starting from the moment of coincidence of the phases, then after the first period they are separated by & 4: after two periods of -2fflt, after three periods - 3 ut, etc. After the K periods expire, the difference between them amount to -t. yr this

: .K - fci (ut C-t; Simultaneously

K-ti4VC-) fc, Ci)

 what is meant by new - coincidence of the phases of the signals.

The required time interval can be represented.

-Nii2;

where 1 N 2 is an arbitrary 3 integer integers

From the expression (2) determine b / and, making the substitution, get

,) taking into account (1)

T 4H4 - «i) V & tHl (5). (3)

Thus, by starting both counters at the moment of coincidence of the phases of the signals at the moment of counting S. the pulses of the sequence with period b receive the first (synchronized) pulse, and at the time of the count Hf of the pulses of the sequence with perich 14 the second and the first time interval.

The time resolution of the | 1st interval is not limited by the technical implementation possibilities. The value of Ы can be selected from 1 to the maximum capacity of the first-counter meter, i.e. There are no maximum limits.

The minimum value of N is also equal to 1, and its maximum value is limited to the value of K:,. With a choice of, for example, 100 not, t ,, 5 ns, which corresponds to frequencies 1 10 MHz, and jj; 10.05 MHz, time intervals of 0.5 not

up to 10 s at, up to 100 s at HH 10, etc. with a resolution of 0.5 n.

If the required time interval is to represent Tu - xxxhhhuu. u not

tBIad-, xxxxxx Mc-M, hence

l (jjr xxxxxx + N2.

In the case of 00.0, it is necessary to accept KU K, and M XXXXXX + (WlTi). Determining the values of N, M and entering the codes in the counters 7 and 8. can be done using a microprocessor ..

Since the maximum value, the maximum delay of the appearance of the first (synchronizing) pulse after phase coincidence will make up K-fca. Considering that the external trigger pulse arrives at an arbitrary time, the maximum value of the delay before the phases of the signals coincide (and the device starts working) make up kt 2. Thus, the maximum total delay of the synchronizing pulse is relative. ; the external trigger can be 2K-B / 2 or 39.8 μs for the given example.

This delay of the synchronizing pulse when calibrating time interval meters has no practical significance. In many other tasks, its effect can be eliminated by using a synchronizing pulse as a trigger pulse for the system and, if necessary, correcting the value of the generated delay.

. Thus, the proposed device allows to increase the resolution and the limits of the time interval setting.

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Claims (1)

SYNTHESIS OF TIME INTERVALS, containing in series a reference generator, a frequency multiplier and a multi-bit counter with pre-setting and recognition of a given state, as well as an input forming unit connected to the input of the control unit, the first output of which is connected to the second input of the counter, the recognition output of which is connected to the input one of the two formers output; pulses and the second input of the control unit, characterized in that, in order to increase the resolution, a frequency mixing unit for the signal of the reference generator, a second frequency multiplier, a phase matching unit and a second counter with preset and recognition of a predetermined state are introduced, the input the second multiplier through the frequency offset block of the signal of the reference generator is connected to the output of the reference generator, the phase matching unit with inputs is connected to the outputs of the multipliers, and. an output - to the third input of the control unit, the first and second inputs of the second counter are connected respectively to the output of the second multiplier and the second output of the control unit, and the identification output is connected to the quarter, the input of the control unit and the input of the second driver of output wells & pulses .