SU1019425A1 - Data input device - Google Patents

Abstract

DEVICE FOR INPUT IN FORMATION, containing serially connected keyboard, encoder register, element OR, first trigger first integrating element and first element NOT, inputs of the first OR element connected to outputs of the encoder, output of the first trigger connected to the first integrating element, and output of the first element NOT Connected to the control input of the register recording resolution, characterized in that, in order to increase the reliability of the device, a second integrating element, a second and a third elements NOT, a first and the second element AND-NOT, the second trigger, the element AND, the second element OR, the output of the first element OR is connected through a serially connected second integrating element, the second element NOT and the first element AND-NOT to the first input of the first trigger and to the first input of the second element AND -NON, the second input of which is connected to the output of the first integrating element, the output of the second element AND-NOT is connected to the input of the first element NOT, the first input of the second trigger and the first input of the AND element whose output is the control output of the device The second input of the second flip-flop is connected to the control input of the device, the output of the second flip-flop is connected to the input, resetting the register, the outputs of which coe-jt are connected to the inputs of the second OR element and the information output of the device with the second input of the I-element and the input of the third element — fj is NOT, the output of which is connected to the second input of the first trigger and with the second input-1 of the first AND-NOT element. f

Description

The invention relates to automation and computer technology and may be used to enter information into an electronic information processing system.

A device for entering information containing a serially connected keyboard, an encoder, a register, a trigger and a delay element Cl is known. However, this device has low reliability due to the presence of two pairs under each key of the keyboard mechanically controlled from the contacts. .

The closest to the technical solution of the invention is a device / containing a serially connected keyboard, an encoder with a register and a chain of serially connected OR elements, a trigger, an integrating circuit and a NOT element, the inputs of the OR element are connected to the outputs, and the output of the element is NOT connected to the resolution input register information input 2.

A disadvantage of the known device is its low reliability, due to the fact that the device allows recording of signals of any duration, including interference, the duration of which in the device is increased to a duration equal to the charge and discharge times of the integrating circuit capacitor (since first, the capacitor is charged up to the trigger trigger threshold, returned to its initial state, and then discharged to the release threshold of the NOT element, which generates a signal to reset the information in the register).

The aim of the invention is to increase the reliability of the device.

This goal is achieved by the fact that in a device containing a serially connected keyboard, an encoder, a register, an OR element, the first trigger, the first integrating element and the first NO element, the inputs of the first OR element are connected to the outputs of the encoder, the output of the first trigger is connected to the first integrating element, and the output of the first element is NOT connected to the register write enable control input, the second integrating element is entered, the second and third elements are NOT, the first and second elements are NAND, the second trigger, the second element is AND, the second The OR element, the output of the first element OR is connected via a serially connected second integrating element, the second element NOT and the first element NAND to the first input of the first trigger and to the first input of the second element NAND, the second input of which is connected to the output of the first integrating element, output The second element is NOT connected to the input of the first element, the first input of the second trigger and with

The first input of the AND element, whose output is the control output of the device, the second input of the second trigger is connected to the control input of the device, the output of the second trigger is connected to the register reset input, the outputs of which are connected to the inputs of the second OR element and are the information output device, the output of the second element OR is connected to the second input of the element AND and the third element input NOT, the output of which is connected to the second input of the first trigger and with the second input of the first AND-NOT element.

Figure 1 presents the scheme of the device; in fig. 2 - time diagram of his work.

The device contains a keyboard 1, an encoder 2, a register 3, the first element OR 4, the second element OR 5, the first integrating element b, the second integrating element 7, the first trigger 8, the second trigger 9, the first element NOT 10, the second element NOT 11 , the third element is NOT 12, the first element is AND-NOT 13, the third element is AND-NOT 14, and element 15.

The first integrating element contains a capacitor 16 and a resistor 17, the second integrating element contains a capacitor 18 and a resistor 19.

The keyboard 1 is connected to the encoder 2, the output buses of which are connected to the register 3 and through the first element OR 4, the second integrating element 7, the second element NOT 11 to the first input of the first element NAND 13. The output of the first element NAND 13 connected to the first input of the first trigger 8 and the first input of the second element H-NO 14, the output of the first trigger 8 through the first integrating element 6 is connected to the second input of the second AND-14 element. The output of the AND-14 element is connected to the first input of the second trigger 9 , the first input element And 15 and through the first element nt NO 10 - to the input of the register write enable 3. The second input of the second flip-flop 9soedinen a control input device and an output of second latch 9 - with the reset input of register 3. The register 3 outputs are data output devices. The output of the element 15 is the control output of the device. The outputs of the register 3 through the second element OR 5 are connected to the second input of the element 15 and through the third element NOT 12 to the second inputs of the first element NAND 13 and the first trigger 8.

The device works as follows.

In the initial state, when neither one of the keyboard 1 keys is turned on, the output voltage of the encoder 2 receives a low voltage level, the output of the first element OR 4 is low and the capacitor 18 of the second integrating element is discharged, respectively, at the output of the second element NOT 11 high level. The second trigger 9, which was set to its initial state at the end of the previous cycle by a short-term low voltage on the control input of the device (reset circuit), keeps the register 3 at a low level on the reset state. A low voltage level at the outputs of the register 3 through the second element OR 5 is fed to the input of the third element rv 12 and to the input of the element and 15, forming at the device control output a low level of the output voltage of the strobe signal followed by the output code signals of the register 3, - High voltage levels at the first and second inputs of the first element AND-NOT 13, respectively, coming from the second element NOT 11 and the third element NOT 13, at the output of the first element AND-NOT 13 cause a low level of voltage, which, after In addition, the second connected element IS-NOT 14 and the first element NOT 10 by the low voltage level to the control input of the register recording resolution 3., prohibits, in the initial state, entering information into the register 3.: Besides, the low level at the output of the first element AND-NO 13, arriving at the first input of the first trigger 8, sets it to the initial state and forms at its output a high voltage level that charges the capacitor 16 of the first integrating element 6. Thus, the register 3 in the initial state is in reset state ca and input of information is forbidden in it. The control input of the device (reset circuit) in its initial state has a high voltage level. When pressing any key of the keyboard 1 on the output buses of the encoder 2, the parallel binary code of the key appears in the form of high levels of voltage, resulting from the bounce of the contacts of the switching elements like pulse trains (Fig. 2a) This signal goes to register 3 and through the OR 4 element - to the second integrating element 7. A capacitor 18 (Fig. 2 b) occurs. When the voltage reaches the threshold of accumulation, a low level of voltage is produced at the output of the second element NOT 11 (Fig. 2c). Accordingly, at the output of the first element I- A high voltage level is NOT generated (Fig. 2d), which, when it enters the first input of the second element 14, forms a low voltage level at its output (Fig. 2g). A high voltage level is formed at the output of the first element NOT 10 (Fig. 2h), which permits the entry of information into the register 3. At the same time, the low level from the output of the second element NAND 14, arriving at the first input of the second trigger 9, forms at its output a high voltage level (Fig. 2i), which, entering the reset input of register 3, permits the memorization of the information entering it. Thus, the permission to enter information and its storage in the register are formed with a delay / equal to the charging time of the capacitor 18 of the second integrating element 7 to the threshold (Actuation of the second element NOT 11 at time t-, (Fig. 26). At the output of the register 3, which is the information output of the device, a parallel binary key appears, and accordingly, a high voltage level appears at the output of the second element OR 5; it arrives at the input of the And 15 element. However, at the output of the And 15 element, your supervisor The device gate signal for the tracking signal is only after the level appears; the high voltage at the output of the second element is NOT 14 (fig.2m). The output signal of the second element OR 5 is fed through the third element at the NOT level of low voltage (Fig. 2L) to the second input of the first trigger 8, switches it (Fig 2L), Capacitor 16 of the first integrating element 6 begins to discharge and when the voltage on it is equal to the voltage of the release threshold at a time of ± 2 (Fig. 2e), at the output of the second element AND-HE 14, a high level voltage is formed (Fig. 2g), which, at the input of the element 15, permits the formation at the control output of the device of the strobe signal of the tracking code signals of register 3. Thus, the strobe The signal is formed with a time delay relative to the register code signals (Fig. 2m) and (Fig. 2k), respectively. At the same time, the high voltage level at the output of the second element AND-HE 14 causes a low voltage level at the output of the first element NOT 10, which prohibits further input of information into the register 3. Thus, high reliability of information input is achieved at the minimum possible recording time in the register , since the input of information is completed only after the information is recorded in register 3, plus an additional period of time determined by the discharge time of the capacitor 16 of the first integrating element 6. Mini The short resolution time for recording information in a register with its high reliability also allows to significantly reduce the possibility of accidental interference with register 3. The subsequent input of information into register 3 is possible only when the key is released and the register is reset. If one of these conditions is not fulfilled, the output of the first IS-NE 13 element remains at a high voltage level (Fig. 2d). The first trigger 8 maintains a low voltage level at the output and the first integrating element b along the circuit — the second element AND 14 — the first element NOT 10 at the recording resolution input of the register 3 maintains a low voltage level that prohibits the input of information ( register 3. After receiving the information, the external device through the circuit. Resetting to the control input of the device gives the low voltage level (fig.2n), which, entering the second trigger 9, switches it to the initial state (fig.2i), being formed the output of the second trigger level 9 low n Arriving at the reset input of the register 3, resets the recorded information in register 3. After releasing the keyboard 1 key, the output of the first element OR 4 also causes pulse bursts due to contact bounce (Fig. 2a). The capacitor 18 of the second integrating element 7, time whose discharge is chosen longer than the bounce time of the switching contact /, the moment of time is discharged before the voltage of the release threshold. t3 (Fig. 26), and a high voltage level appears during the second element NOT 11 (Fig. 2c) As a result, the low voltage level (fig. 2d) is formed at the output of the first AND-HAND 13 element after the contact bounce breaks off, which switches the first register 8 to its initial state — a high voltage level at its output (fig. 2e). This prohibits re-entry of information from contact bounce when opened. The device in its initial state is ready for the next input of information, since the charging time of the capacitor 16 of the first integrating element b (Fig. 2e) i. It is significantly less than the charge time of the capacitor 18 of the second integrating element 62 t-, upon the next input of information. Expansion of functionality is achieved by the fact that the device generates a binary code at the output of the register that exists during the time specified by the response circuit of the reset to the control input of the device, i.e. the register, besides suppressing contact bounce, is also used as a buffer. In addition, the output code signals of the register are accompanied by a strobe signal delayed by to-t time. The device also provides information security if you accidentally press a few keys, because after the information entry is prohibited, any other key is pressed when the first key is on (and also if the first key released and then pressed second) does not lead to distortion of information at the output of the device, since the prohibition of entering information continues until the key is pressed and the information is reset in the register. Finding the register in the initial state, resetting and prohibiting the entry of information into it, and the high accuracy of entering information into the register at the lowest possible time for input B to interrupt due to the limitation of the input feedback duration, along with the prohibition of input short-term signals and interference, provides vtssoky noise immunity of the device.

Claims (1)

DEVICE FOR INPUT FORMATIONS, containing a keyboard, encoder, register, OR element, a first trigger * the first integrating element and the first NOT element in series, the inputs of the first OR are connected to the encoder outputs, the output of the first trigger is connected to the first integrating element, and the output of the first element is NOT connected to control input permissions register entries, characterized in that, in order to increase. the reliability of the device, the second integrating element, the second and third elements NOT, the first and second AND-NOT elements, the second trigger, the AND element, the second OR element, the output of the first OR element are connected through the second integrating element, the second element NOT connected in series, and the first AND-NOT element with the first input of the first trigger and the first input of the second AND-NOT element, the second input of which is connected to the output of the first integrating element, the output of the second AND-NOT element is connected to the input of the first NOT element, the first input the second trigger and with the first input of the AND element, the output of which is the control output of the device, the second input of the second trigger is connected to the control input of the device, the output of the second trigger is connected to the reset input of the register, the outputs of which are connected to the inputs of the second OR element and are the information output of the device, the output of the second OR element is connected to the second input of the AND element and the input of the third element NOT, the output of which is connected to the second input of the first trigger and to the second input of the first AND element.