SK316991A3 - Wide-angle tv image-forming set - Google Patents

Abstract

The system includes a video display having a specific format display ratio. A mapping circuit maps an adjustable picture display area on the video display. Two signal processors generate the first and second selectively interpolated video signals from input video signals. A switching circuit selectively couples video signal sources as the input video signals. A selecting circuit selects as an output video signal between one of the first and second processed video signals and their combination. A control circuit controls the signal processors and other circuits to adjust in format display ratio and image aspect ratio each picture represented in the output video signal.

Description

Widescreen television imaging Sousa ^ ^ va

Technical field

The present invention relates to a television imaging system, in particular a widescreen imaging system, which interpolates image data to produce a variety of display formats, both direct viewing and projection display systems.

BACKGROUND OF THE INVENTION

Most of today's television systems have an aspect ratio of the picture, i. j. a ratio of horizontal width to vertical height of 4: 3. The widescreen view is more likely to fit the display format of movies, such as 16: 9. Televisions with a 4: 3 aspect ratio, often referred to as 4x3, have limited viewing capabilities from single and multiple video sources. Television broadcasts broadcast by commercial broadcasters are, except for experimental broadcasts, broadcast in 4x3 format. However, many viewers find the 4x3 display format less satisfactory than the wider display format common to movies. Television with a wider display format not only provides a more pleasing display, but is also capable of displaying widescreen sources in the corresponding widescreen display format. Movies are displayed in their original format and not in cropped or distorted form. The video source does not need to be cut off, even if the film is converted to a video signal, for example by means of a film sensor or processor in a television.

The widescreen aspect ratio can be applied at both basic or standard line decomposition rates and multiples thereof, as well as both interlaced and non-interlaced lines. For example, standard NTSC video signals are displayed by interleaving consecutive consecutive image frames, wherein each image is generated by raster scanning at a basic or standard line scanning rate of approximately 15,734 Hz. The basic degradation rate of the video signals is referred to as various, either fn, lh or lH. The actual frequency of the signal 1f _H will vary depending on the different video standards. In an effort to improve the image quality of television sets, systems for displaying video signals in a gradual manner without interleaving have been developed. Progressive scanning requires that each image displayed be deinterleaved in the same time period as is allocated to decompose one or two stripe interlace formats. Flicker-free AA-BB displays require each frame to be unfolded in succession twice. The line decomposition frequency must in any case be twice the standard line frequency. The scanning rate for such successive scan or flicker-free displays is referred to as 2, f »or 2H. For example, according to US standards, the scanning frequency is approximately 31,468 Hz.

Widescreen TVs are also adapted to provide multiple displays of both conventional and widescreen display signals, as well as combinations thereof in a multiple display system. However, the use of widescreen TV displays presents numerous problems. Main areas of these problems. consists in alternating the three-dimensional display of multiple signal sources, producing identical timing signals! from asynchronous but simultaneously imaging sources 1, producing high resolution images from densified data signals! and switching between multiple sources! to generate multiple display systems.

SUMMARY OF THE INVENTION

These problems are solved by a wide-screen television display system according to the invention. SUMMARY OF THE INVENTION The present invention is characterized in that the imaging system comprises imaging means of a first aspect ratio to the display format, means for mapping the adjustable imaging region in said imaging means, means for processing the first and second video signals from the input video signals. about one of the differences of the Other! Display format, switching means for selectively pooling video sources! as said input video signals, means for selecting said first or second video signal or a combination thereof as output video signal, and means for controlling said mapping means, processing means, and selecting means to adjust the aspect ratio of the display format and the ratio of the grape of each image transmitted output video signal.

One of the other differences mentioned! The display format side may be the same as the first display format ratio.

In a preferred embodiment, said processing means is adapted to selectively trim said input video signals.

Said mapping means comprise means for creating a screen for the screen.

In another preferred embodiment, said mapping means comprises means for forming an address matrix for the liquid crystal display unit.

In a further preferred embodiment, said display area is adjustable in only one dimension.

Preferably, said display area can only be adjusted in a vertical direction.

In another preferred embodiment, said processing means is adapted for horizontal interpolation of said video signals.

In another preferred embodiment, the imaging system of the invention further comprises means for converting interlaced video signals to an non-interlaced image format.

In another preferred embodiment, said video signal sources comprise channel selectors and video connections.

Said processing means may further comprise respective interpolation means for said first and second input video signals.

With only a vertically adjustable display area, said processing means can be adapted for only analysis interpolation of said input video signals.

In another preferred embodiment, said mapping means comprises horizontal and vertical deflection circuits to form a raster, wherein the raster is vertically adjustable and said processing means are adapted to only horizontally interpolate said input video signals.

Said processing means may be adapted to interpolate said input signals by selective stretching or these input video signals.

In a further preferred embodiment, the imaging system according to the invention comprises second means for selecting between said output video signal and an external video signal for displaying said mapping means and said display means.

The display system of the invention may further comprise means for synchronizing said processing and mapping means.

The widescreen television imaging system of the present invention provides high resolution capability, allows displaying single and multiple images from single and multiple sources having similar or different format ratios, wherein the aspect ratio ratios are optional and have all the necessary features and capabilities of the widescreen systems described in the prior art.

image compression

BRIEF DESCRIPTION OF THE DRAWINGS FIG

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be explained in more detail with reference to the drawings in which: FIG. 1 (a) to 1 (i) different widescreen display formats, FIG. 2 is a block diagram of a widescreen television imaging system according to the invention adapted for operation in line decomposition. 3 is a block diagram of the widescreen processor shown in FIG. 2, FIG. 4 (a) is a block diagram of a widescreen television display system according to the invention adapted to operate in line decomposition 1fn; FIG. 4 (b) is a block diagram of a widescreen television display system according to the invention adapted for operation with a liquid-crystal display unit; FIG. 5 is a block diagram

D of the widescreen processor shown in FIG. 4, FIG.

a block diagram with further details of the widescreen processor common to the diagrams of FIG. 3 and 5, FIG.

a block diagram of an image creation processor in the image shown in FIG. 6, FIG. 8 is a block diagram of a gate array shown in FIG. Fig. 6, with the sides of the main, auxiliary and output signals, FIG. 9 and 10 are diagrams of the time schedule of the display format shown in FIG. 1 (d) with fully truncated signals, FIG. 11 (a) is a block diagram illustrating in more detail the path of FIG. 11 (b). 11 (c) the shape of the main signal of FIG. 11 (a) when the video signal is expanded, FIG. 12 is a block diagram with a more detailed illustration of the path of the auxiliary signal of FIG. 8, FIG. 13 7, 15, 16 and 17 of the block signal according to FIG. 8, the main signal according to the timing and control portion 18, a table of values using the decimation portion shown in FIG. 14; 15 to 17, FIGS. 19 (a) and 19 (b) are block diagrams full of programmable universal decimation circuits for controlling the horizontal and vertical compression ratios; FIG. 20 is a block diagram of an interleaved conversion circuit; Fig. 2, Fig. 21 is a block diagram of the noise attenuation circuit shown in Fig. 20, Fig. 22 of the block sc combination. 2 and FIG. 23 illustrate the waveforms of the vertical movement of the image; FIG. 24 (a) to 24 (c) display formats according to the waveforms shown in FIG. 23, FIG. 25 is a block diagram of the RGB interface shown in FIG. 2, FIG. 26 block diagram of RGB to converter

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Y, U, V shown in FIG. 25, FIG. Fig. 27 is a block diagram of an internal signal 2ih generation circuit when converting 1fn to 2fn; 28 shows a different block diagram of a portion of the auxiliary signal path shown in FIG. 8, FIG. Fig. 29 is a five-line memory diagram with stage attendance order of arrival to avoid collisions of the read / write pointer; 30 is a block diagram of a simplified circuit serving as an auxiliary path synchronization circuit in a gate array; FIG. Figure 31 is a diagram of the time dependence between the setting of the field indicator and the image line; 32 to 34 are diagrams of a method of maintaining interleaving integrity of presently displayed interrelated video signals; FIG. 35 (a) to 35 (c) waveforms of the signals processed by the circuit shown in FIG. 36, FIG. 36 is a block diagram of an integrity maintaining circuit 31-35; FIG. 37 is a schematic diagram of an arbitrary approach associated in the image; FIG. 38 the interleaving output switching of FIG. FIG. 3 shows an image processor with an image processor, a block diagram of a control circuit between a main and an auxiliary video signal; FIG. 39 and 40 are block diagrams of individual data reduction and recovery circuits performing the function of the discriminating processing circuits of FIGS. 6 and 8; FIG. 41 and 42 are block diagrams of a two-bit circuit, data reduction and recovery to supplement the resolution processing circuits of FIG. 6 and 8, FIG. Fig. 43 is a table of values constituting a rotation diagram for improving operation of data reduction and recovery circuits; 44 is a schematic table explaining another alternative embodiment of the resolution processing circuit of FIG. 6 and 8, FIG. 45 and 46 are diagrams explaining the operation of the automatic envelope detector; FIG. 47 is a block diagram of an automatic envelope detector; FIG. 48 is a block diagram of an alternative embodiment of an automatic envelope detector circuit; FIG. Fig. 49 is a block diagram of a circuit for adjusting the vertical dimension of an image including an envelope detector; Figs. 50 (a) to 50 (f) of the waveforms of the color components of the main video signal when converting from analog to digital; FIG. Figures 51 (a) and 51 (b) of the waveforms explaining the slope of the luminance and color components as the main signal passes through the gate array; Figs. 52 (a) and 52 (b) of the path portion of the luminance and color components of the main signal when the image is compressed; Figures 53 (a) to 53 (1) of a waveform explaining the compression of the color components relative to the luminance components; 54 (a) and 54 (b) of a portion of the path of the luminance and color components of the main signal when the image is expanded, FIG. 55 (a) to 55 (1) of a waveform explaining the expansion of the color components relative to the luminance components; FIG. 55 and 57 illustrate the operation of the two-step interpolation filter variables usable in the interpolators of FIG. 8, 11 (a) and 12, FIG. 58 is a block diagram of a two-stage compensated variable interpolation filter; FIG. 59 is a block diagram of a two-stage compensated variable filter arranged for zooming; FIG. 60 is a block diagram of an eight-branch two-stage interpolation filter circuit; FIG. 61 is a block diagram of a 1/16 or 1/32 distribution interpolator; FIG. 62 shows a table of K and C values for the interpolator shown in FIG. 61, FIG. 63 is a block diagram of a circuit for determining C values from K values; FIG. 64 is a table of values calculated by the circuit of FIG. 63, FIG. 65 is a block diagram of an alternative embodiment of a circuit for determining C values from K values; FIG. 66 is a block diagram of another alternative embodiment of a circuit for determining C values from K values; FIG. 67 waveforms. the frequency responses of a conventional two-stage four-point interpolator, FIG. 68 and FIG. Fig. 69 is a graph showing the frequency response of an eight-point interpolator; 70 is a block diagram of an eight-point interpolator with km / t. FIG. 68 and 69.

DETAILED DESCRIPTION OF THE INVENTION

The individual parts of FIG. 1 illustrate! some, but not all, of the various combinations of simple and multiple image formats that may be performed by various configurations of the display system of the invention. The selected illustrations are intended to facilitate the description of the individual circuits included in the widescreen television display system of the invention. For the sake of simplicity of illustration and description, a conventional 4 x 3 aspect ratio for the image source or signal is a conventional aspect ratio, while the wide aspect ratio is generally 16x9. However, particular embodiments of the imaging system of the present invention are not limited to these ratios.

Fig. 1 (a) shows a television for direct viewing, or projection, of a conventional 4x3 display format. If a 16x9 display format image is transmitted as a 4x3 signal, black bars appear at the top and bottom of the screen. This is commonly referred to as the envelope format. In this case, the observable image is quite small relative to the total display area available. Another possibility is that the 16x9 display source is converted before the transmission so that the image fills the entire vertical viewing area of the 4x3 display unit. In this case, however, much information is cut off on the left and / or right side. Another alternative is that the envelope format image can be expanded vertically but not horizontally, but the resulting image will be noticeably distorted by vertical overload. None of these three options are appropriate.

Fig. l (b) shows a 16x9 screen. The 16x9 display format image source is displayed completely, without cropping or distortion.

An image in a 16x9 page format, which itself is converted by a 4x3 signal, can be progressively decomposed by doubling or adding lines to create a larger image with satisfactory vertical resolution. The widescreen television display system of the present invention can display such a signal in a 16x9 aspect ratio format, whether from a main source, an auxiliary source, or an external color signal source.

Fig. 1 (c ') shows a 16x9 main signal display in which an image in a 4x3 page format is embedded. If both the main and the auxiliary video signals are sources of 16x9 display formats, the embedded picture can also display the 16x9 aspect ratio. The embedded image can be displayed in various positions.

Fig. 1 (d) shows a display format in which the main and auxiliary video signals are displayed with the same dimensions. Each of the image areas has an 8x9 display format that is quite different from both 16x9 and 4x3 formats. In order to display a 4x3 display source in such a picture area without distorting it horizontally or vertically, the signal on the left and / or right side must be cropped. The greater part of such an image may be displayed (with less cropping) if some distortion of the ratio of the horizontal compression is permissible. The horizontal compression has an angle s of fig.

as a result of vertical extension of the objects. in "picture. The widescreen television of the present invention is capable of providing any combination of crop and bias ratio, from maximum crop without distortion of the grape ratio to maximum distortion of the grape ratio.

The constraints imposed by data sampling in the processing of the auxiliary video signal make it difficult to produce a high-resolution image having the same dimension as the display of the main image. These difficulties can be overcome in various ways.

(e) shows a display format in which a 4x3 picture is displayed in the center of a 16x9 screen. On the right and left side are visible vertical dark stripes.

Fig. l (f) shows a screen on which one large 4x3 image and three smaller 4x3 images are simultaneously displayed. A smaller picture outside the perimeter of a large picture is sometimes referred to as a picture outside picture rather than picture in picture. The term picture-in-picture is used herein for both display formats. If a widescreen television is provided with two tuners, either internal or one internal and one external, for example in a connected video recorder (magnetoscope, video recording device), two of the displayed images can display real-time movement in accordance with the source. The remaining images can be displayed in still image format. Obviously, by adding additional tuners and auxiliary signal processing circuits, more than two moving images can be produced. Further, it will be appreciated that the large image and the three small images may also be switched to the position shown in FIG. leagues).

Fig. 1 (h) shows an alternative in which a 4x3 picture is placed in the center of the screen and six smaller pictures are arranged in vertical columns on each side, also in 4x3 format. As with the previous arrangement, a two-tuner wide-screen television can provide two moving images. The remaining eleven images will be in the form of still images.

Fig. 1 (i) shows a screen with an array of twelve images in 4x3 display format. Such an arrangement is particularly advantageous as a guide for selecting channels where each of the images is. at least a still image associated with a particular channel. As with the arrangements described above, the number of moving pictures will depend on the number of tuners and signal processing circuits available.

The various formats shown in FIG. 1 are illustrative, not limiting, and may be shown by a widescreen television shown in the other drawings and detailed and described below.

In FIG. 2 shows an overall block diagram of a widescreen television imaging system 10 according to the invention adapted for operation with line decomposition 2f-i. The television display system 10 generally comprises an input circuit 20, video signals, a chassis or television microprocessor 216, a widescreen processor 30, a 40f _H / 2fH converter, a deflection circuit 50, an interface 60, a color. a YUV / RGB converter 240, a display driver 242, a direct observation or projection-type display 244 and a power supply 70. The grouping of the different circuits into different functional blocks is done to facilitate the description and does not define the relative physical position of these circuits.

The video signal input circuit 20 is adapted to receive several complete video signals from different sources. The video signals may be optionally switched to be displayed as sig13 main or auxiliary signal. The radio frequency switch 204 has two antenna inputs ΝΤΙΝΤΙ and ANT2. Introduce these! inputs for both external antenna and cable reception. The radio switch 204 determines which antenna input is connected to the first tuner 206 and which to the second tuner 208. The output of the first tuner 206 is the input of the single-chip circuit 202, which performs a number of functions related to tuning, horizontal and vertical deflection and fading of the video signal. In particular, the chip shown is TA7730. In the single-chip signal circuit of the first tuner 206, it generates a baseband VIDEO OUT video signal, which is fed both to the video signal switch 200 and to the TV1 input of the widescreen processor 30. Other inputs of industrial 202 are from baseband to labeled AUX1 and AUX2 decocamers, laser video switch 200s. These can be used for compact discs, video player players, video games and the like. The video switch output 200, which is controlled by the television microprocessor 216, is labeled SWITCHED VIDEO and is an additional input to the widescreen processor 30.

As further evident from FIG. 3, the wide screen processor switch SW1 selects TV1 and SWITCHED VIDEO signals, outputting a SEL COMP OUT video signal applied to the Y / C input of decoder 21. The Y / C decoder 210 may be an adaptive row comb filter. The other two sources S1 and S2 of the video signals are also inputs of the Y / C decoder 210. Each of the inputs S1 and S2 represents a different S-VHS source and consists of separate luminance and chrominance signals. The switch, which is implemented as part of a Y / C decoder from adaptive row comb filters or as a standalone switch, responds to TV signals may be 210 in some microprocessor 216 and selects one of the brightness and color signal pairs, designated as Y_M and C outputs. IN. The selected pair of luminance and chrominance signals is then considered the main signal and is processed in the paths of the main signal path. Signal designations containing _M or MN refer to the path of the main signal. The color signal CIN is redirected back to the single-chip circuit 202 to produce differential color signals UM and VM. In this respect, U is the equivalent designation for (R-Y) and V the equivalent designation for (B-Y). The signals Y_M, UM and VM are then converted into a digital form by the widescreen image processor 30 for further processing.

The second tuner 208, which is functionally delimited as part of the widescreen processor 30, forms the baseband video signal TV2. The switch SW2 selects between the signals TV2 and SWITCHED VIDEO as the inputs of the second Y / C decoder 220. The second Y / C decoder 220 can also be implemented as an adaptive row comb filter. The switches SW3 and SW4 make a choice between the brightness and color outputs of the decoder 220 and the bright and color signals of the external video source designated Y_EXT and C: _EXT. The Y EXT and C EXT signals correspond to the S-VHS input S1. The decoder 220 and the switches SW3 and SW4 may be combined, for example, in adaptive row comb filters. The output of the switches SW3 and SW4 is then considered as an auxiliary signal and is further processed in the auxiliary signal path circuits. The selected brightness output is indicated by Y..A. Signal designations containing A, AX, _AUX refer to the path of the auxiliary signal. The selected color signal is converted to color difference signals U_A and VA. The signals Y A, U A and V A are then converted to digital form for further processing. Us15 organizing a device for switching video sources! the main and auxiliary signal paths ensure maximum flexibility when selecting the source! for different parts of different display formats. The complete sync signal COMP SYNC, corresponding to the YM signal and generated by the widescreen image processor 30, is fed to the sync signal separator 212. The horizontal synchronization component H and the vertical synchronization component V are inputs of the vertical subtraction circuit 214 which produces a VERTICAL RESET signal fed to the widescreen processor 30. The widescreen processor 30 generates an internal vertical reset output signal INT VERT RST OUT routed to the RGB interface 60. The switch in the RGB interface 60 selects between the internal vertical reset output signal and the vertical sync component of the external color signal source. The output of this switch is a selected vertical synchronization component SEL VERTSYNC fed to a deflection circuit 5 '). The horizontal and vertical sync components of the auxiliary video signal are formed by the sync mixture separator 250 in the widescreen processor 30.

The converter 40 a signal f 1 _if the 2f H signal converts the interlaced video signals to progressively scanned non-interlaced signals, e.g., those in which each line is displayed twice, or those in which the interpolated lines it sousedních fields of that, an additional assembly line. In some cases, the use of the preceding line or interpolated line will depend on the level of motion detected between adjacent poles or frames. The generation of 2fu timing signals is shown in more detail in FIG. The converter circuit 40 operates in conjunction with a RAM image type 420. This memory may be used to store one or more field images to allow sequential display. The converted image data such as Y_2fn and U2fh and V2fh signals are fed to the RGB interface 60.

image frequency decomposition is to RGB

The RGB interface 60, detailed and illustrated in FIG. 25, allows a choice between the converted image data or external RGB image data to be displayed by the input circuit 20 of the video signals. An external color signal is considered to be a widescreen signal adapted for

2γη · The vertical synchronization component INT VERT RST OUT of the main signal is guided from the widescreen interface processor 60, allowing the selected vertical synchronization component (fy or fvext) to be routed to the deflection circuit 50. The widescreen function allows user to select an external color signal by generating an INT EXT control signal. . However, the selection of an external color signal input can lead to a vertical rupture of the screen and damage the screen or projection screen in the absence of such a signal. Therefore, the RGB interface 60 detects an external synchronization signal in order to prevent a non-existent external color signal from being input. The colors and time interval of the external color signal are also controlled by the widescreen image microprocessor 340.

The widescreen processor 30 includes a picture-in-picture processor 320 that processes the auxiliary video signal. The term picture-in-picture is sometimes abbreviated as PIP or pix-in-pix. The gate array 300 combines the master and auxiliary video signal data into a variety of display formats, some of which are shown in FIG. l (b) to l (i). The image-in-picture processor 320 and gate array 300 are controlled by a widescreen image microprocessor 340. The widescreen microprocessor 340 is coupled to the TV microprocessor 216 via a serial bus. The serial bus contains four signal lines for data, clock pulses, opening signals and reset signals. The widescreen processor 30 further generates a complete vertical blanking and resetting signal in the form of a three-level sandcastle signal. Alternatively, the blackout and reset signals can also be generated as separate signals. The complete blanking signal is passed through the video signal input circuit 20 to the RGB interface 60.

In the deflection circuit 50, which is shown in detail in FIG. 22, a vertical reset signal from the widescreen processor 30, a selected horizontal synchronization signal at a frequency of 24h from the RGB interface 60, and additional widespread processor control signals 30 are provided. These additional control signals relate to phasing, adjusting the vertical dimension east / west. The deflection circuit 50 generates 2f h feedback pulses fed to the widescreen processor 30, the converter 40 for the 1f h to 2f converter, and the YVJV / RGB converter 2.40.

The operating voltages for the entire widescreen television imaging system are provided by a power supply 70 that can be connected to an AC network.

The widescreen processor 30 is shown in more detail in FIG. 3. The main components of the processor 30 are a gate array 300, an image-in-picture circuit 301, analog digital and digital analogue converters, a second tuner 208, a widescreen microprocessor 340, and a widescreen output coding circuit 227. Further details of the widescreen processor 30, which are common to both horizontal and horizontal settings, as well as to 2ίκ, e.g. The picture-in-picture circuitry is shown in FIG. 6. The PIP 320 that forms a substantial portion of the PIP 301 is shown in more detail in FIG. 7. The gate array 300 is shown in detail and in FIG. 8. Some of the components shown in FIG. 3 and forming portions of the main and auxiliary signal paths have been described in detail.

The second tuner 20j3 is coupled between the frequency stage 224 and the audio stage 226 and operates in conjunction with the widescreen microprocessor 340. The microprocessor 340 includes an input / output circuit 340A and an analog output circuit 3.Ί0Β. The input / output circuit 340A generates color control and time interval signals, an INT / EXT signal to select an external color signal source, and control signals for switches SW1 to SW6. The input / output circuit 340A also monitors the EXT SYNC DET signal from the RGB interface to protect the deflection circuit and the screen (s). Analog output circuit 340B provides control signals for vertical adjustment, east-west adjustment, and horizontal phasing through respective interconnects 254, 256 and 258.

The gate array 300 combines video information from the main and minor video signal paths to form a composite wide-screen image, for example, some of the images shown in different parts of FIG. The clock pulses are generated for the gate array 300 by a phase-locked feedback loop 374 that is in conjunction with the low-pass filter 376. The main video signal is fed to the widescreen processor 30 in analogue and YUV format as Y_M signals,

For M and V M. These main signals are converted from analog to digital by analogue to digital converters 342 and 346, which are detailed and illustrated in FIG. 4th

The chrominance signals have common U and V denominations that can be assigned to either the RY or BY signals, or the I and Q signals. The bandwidth of the sampled brightness signal is limited to 8 MHz because the system clock frequency is 1024 fh, which is approximately 16 MHz . A single analog-to-digital converter and analog switch can be used to sample color component data because the U and V signals are limited to 500 kHz or 1.5 MHz for band I. The selected UVMUX line for the analog switch or multiplex circuit 344 is the frequency of 8 MHz, derived by dividing the clock frequency of the system by two. A single-clock pulse trigger SOL pulse sets this signal at the beginning of each video line synchronous to zero. The UV MUX signal then changes its status in every hour cycle. Since the line length corresponds to an even number of clock cycles, the triggered state will continuously flip between 0 and 1 without interruption. Y and UV data streams from the analog or digital converters 342 and 346 are shifted because each of the analog-to-digital converters has a delay of one hour cycle. In order to compensate for this data shift, a similar delay of the clock gate information from the control circuit 349 of the main signal path interpolator 304 must be delayed. If the clock gate information was not delayed, the UV data would not be correctly paired when it was knocked out. This is important because each UV pair represents one vector. The element U of one vector cannot be paired with the element V of another vector without causing a color shift of 20. Instead, the sample V of the previous pair is discarded together with the sample pair of the new pair. This method of multiplexing the U and V components is referred to as 2 = 1: 1, since for each pair of color component samples U, V, respectively. two brightness samples. The Nyquist frequency for both U and V is effectively mixed to half the Nyquist frequency of luminance. Thus, the Nyquist output frequency of the analog-to-digital converter is 8 MHz for the luminance component, while it is 4 MHz for the color component.

The image-forming circuit 301 and / or gate array 300 may also include means to improve the resolution of the auxiliary data even when compressed. A number of data reduction and recovery circuits have been developed, including e.g. compressing the pairs of pixels and correction codes. In addition, different data reduction correction sequences including different bit counts and different methods of compressing pairs of pixels at different bit counts are contemplated. One of these data reduction and recovery schemes may then be selected for a widescreen image microprocessorine 340 to achieve maximum display resolution for each particular kind of display format.

The gate array 300 includes interpolators that interact with the ratchet memories 356 and 358 in the order of arrival. Interpolators and memories are used to resample the main signal. Another interpolator can resample the auxiliary signal. The clock and sync circuits arranged in the gate array 300 control data handling of both the main and auxiliary signals, including combining them into a single video output signal having components Y-MX, U MX and V_MX. These output components are converted into an analog or digital form to the transducers 360, 362 and 364.

The signals Y, U and V in analogue form are fed to a converter 40 for a 1 f conversion to 2 f _H where they are converted to non-interlaced lines. The Y, U, and V signals are also encoded by the encoder 227 into Y / C format to produce a wide-format Y-OUT-EXT / COUT EXT output signal, which is available on the panel doors. The selection of the synchronization signal for the coding apparatus 227 is made by the switch SW5, either the C-SYNC-MN gate array signal 300 or the C SYNC AUX circuit 301 for picture-in-picture generation. SW6 then selects between YM and CSYNC AUX as the sync signals for the widescreen panel output.

The individual parts of the horizontal synchronization circuit are shown in detail in FIG. The phase comparator 228 is a phase locked loop component comprising a low pass filter 2.30, a voltage-controlled oscillator 232, a divider 234, and a capacitor 236. The voltage-controlled oscillator 232 operates at a frequency of 32fh generated by the ceramic resonator 238 or a similar stop. The output 32f of the REF of the resonator 238 is the input of the converter 40 to convert lf _H to 2γη. The output of the voltage-controlled oscillator 232 is divided by 32 to produce a second input frequency signal at a suitable frequency for phase comparator 228. a widescreen image processor 30 and a converter 40 for converting 1f to 2f. The timing signals 32fu REf and 1fn REF are fed to a splitter 400 where they are divided by a value of 16. The output 2f _ri is then fed to a pulse width modulation circuit 402. The control of the splitter 400 by the REF signal ensures synchronization of the splitter operation with the phase locked loop feedback input circuit 402 of the video input signal modulation section of the pulse width modulation provides a suitable pulse width of the 2fn REF signal for proper operation of the phase comparator 404 such as CA1391 a second phase locked feedback loop comprising further a low pass filter 406 and a voltage-controlled oscillator 408 at a frequency of 2ίκ. The voltage-controlled oscillator 408 generates an internal timing signal at a frequency of 2fh, used to drive the sequentially spaced image. Another input signal to phase comparator 404 is the deflection pulses of the deflection circuit 50 or the corresponding timing signal. The use of a second phase locked-loop feedback loop comprising a phase comparator 404 ensures that each deinterleaving period given by 2fh is symmetrical within each period 1f of the input signal. Otherwise, the image could have a raster interruption, for example one in which one half of the image line is shifted to the right and the other half of the image line is shifted to the left.

A block diagram of the interlaced image conversion circuit 900 for progressive-line images is shown in FIG. 20. Circuit 900 may be an integrated circuit and perform all signal processing functions necessary to convert interlaced picture signals into successive non-interlaced formats. In addition, for the signals in need, circuit 900 performs attenuation of noise in an adjustable range. The circuit shown may be used for the Y, U, and V signal components in conjunction with an image circuit 902 of an integrated circuit RAM, such as the HM53051P.

The color components of the U C and V C signal are by means of a single delay of the internal forced-force conversion to a voltage corresponding to logic zero. The analog multi23 plexer circuit 908, coupled to the outputs of the keying circuits 904 and 906, alternately samples each of the chrominance components at a frequency of 2 MHz. These samples are then converted to an 8-bit digital signal by a fast analog-to-digital converter 910 operating at a frequency of 4 MHz. The samples further pass the chrominance noise reduction circuit 912 to the accelerator memory 914. This memory stores only the active portion of each incoming image line of 53 microseconds, so that only 106 samples of each chrominance component are currently stored therein. Memory content is read at a rate that is twice as fast as the write speed, creating two identical lines *

color-carrying information. The signal is set to zero by the blanking circuit 916 during the interval when no samples are available at the memory output. The two color components are then separated in the demultiplex circuit 918 and converted into an analogue form by means of two digital-to-analog converters 920 and 922. The reference base for the digital-to-analog converters 920 and 922 is adjustable by means of a serial bus connected to circuit 924 It can be used to adjust the color saturation.

* The luminance signal YC is a keying circuit 926 during the rear pulse dwell of forced internal conversion to a level that can be adjusted via a serial bus control. This signal is converted from an 8-bit digital format using a fast analog converter 928 operating at a frequency of 16 MHz. Thereafter, this signal passes through circuit 930, which can be used to automatically adjust the black level if necessary. The luminance is filtered by a low pass filter 932, the characteristic of which is given by the following formula:

Η (z) = (1 + z * ') (1 - z z - ³ ) ~ / 16

This filtered signal is then additionally sampled in circuit 934 at 4 MHz. The additional sampled signal is interpolated by interpolator 936 back to a 16 MHz frequency using the same low pass filter characteristic and subtracted from the delayed version of the original luminance signal at summation point 938, producing a signal that contains only high frequency luminance components. The high-frequency luminance signal then passes through the non-linear deadband 940 circuit in which low-amplitude noises are removed. The breakpoints of the non-linear characteristic can be set by the serial control bus.

The additional sampled low frequency signal passes through the noise attenuation circuit 942 and is then interpolated by the interpolator 944 back to a 16 MHz frequency, then added to the noise-free high frequency signal at summation point 946. The luminance signal is then converted to a sequential or interleaved format by the accelerator memory 948. The memory stores only 53 milliseconds of the signal, which corresponds to 848 samples. The content of this luminance memory is read twice for each incoming image line. Another, smaller accelerator memory 950 includes information representing the difference 1 between interpolated bracing signals for the intermediate row and the incoming luminance signal. The smaller accelerator memory 950 contains only low frequency information of 212 patterns. When the luminance signal acceleration memory 948 is read for the first time, the difference signal from the second acceleration memory 950 is interpolated to full intensity by the interpolator 952 and added to the luminance signal at the summit point 970. This generates a signal having a low-frequency component that corresponds to the interpolated luminance signal and a high-frequency component that corresponds to the incoming luminance signal. When the contents of the memory 948 are read a second time, the difference signal is not added. The output is then a signal at twice the speed of the looker to the input.

Blackout by circuit 954 is inserted at a beautiful interval when no data from the accelerator memory is available. The level of this blanking can be adjusted by the chassis microcontroller using a serial control bus. Three signals are required: DATA, CLOCK and ENABLE. The accelerated digital signals are converted into an analogue form by a digital to analog converter 956. The reference base for the converter is adjustable by means of a bus control.

The line interpolation of the low-frequency luminance information is performed complete at a reduced sampling rate (4 MHz) using motion adaptive processing. The 1 Mbit RAM outer picture memory 902 used as the frame memory stores two frames of an 8-bit low-frequency luminance signal and one frame of a 3-bit motion signal. The connection to the RAM image 302 is made by the frame memory interface 964. Each of the fields stored in the memory represents a maximum of 256 active Image lines, each containing 212 active samples. When a low-frequency luminance signal with reduced noise is passed through the delay circuit 958 1 fn, spatial interpolation (used in motion areas) is generated, whereupon the delayed and non-delayed signals are averaged in circuit 960. For example, in a field without one half of the line later, this output is recalled as a field delayed signal. This generates a time-interpolated signal for the stationary areas.

The field delay video signal is again stored in frame memory 982 and recalled after a further 26 frames, reduced by one-half of the row. The result is a net delay of one frame. The frame delay signal is then compared with a sample-by-sample delay signal in the motion detector 962. Here, a three-bit motion signal is generated representing eight different levels of motion. The motion signal is also stored in the frame memory 902, from which it is recalled by one field, enlarged by one half of the row, later.

The delayed field motion is compared to the non-delayed movement, and in the circuit 978 a signal representing a higher level of movement is selected. This motion signal is used to control a soft switch or punch 966 which selects between spatial interpolated and temporal interpolated signals in eight different gray gradations.

The non-delayed low-frequency luminance signal at the summit point 968 is subtracted from the output of the transponder 966, thereby creating a signal representing the difference between the interpolated and the incoming low-frequency luminance signal. The difference signal is then stored in a separate acceleration memory 950 as described above.

The noise damping circuit 942 may be implemented as shown in the block diagram of FIG. 21. The input signal at subtraction point 980 is subtracted from the output signal delayed by the delay 986. If the delay value is selected, the input of most signals is nearly equal to the correct circuit, the delayed output and the difference is small. This difference is then unrestrictedly gain gain of 982 to the input passes through limiter 382, and this (do not limit, has a limiter 7/8). When adding the circuit limiter output at summing point 984, most of the input signal is suppressed, replacing it with a delayed output signal. This suppresses small changes, especially noise. If the input is significantly different from the delayed output, perform trim. The resulting output is then almost the same as the input. The threshold at which the limitation occurs is adjustable by means of a serial control bus, and the noise attenuation rate can be varied from zero (zero threshold) to any desired value.

To reduce the noise of the low-frequency luminance signal, the delay in the circuit described above is equal to one frame. Thus, the sum of the still images is attenuated by the temporary low-pass filter.

The noise attenuation circuit is a cascade consisting of two of these circuits, one of which is delayed equal to one sampling interval (0.5 microseconds) and the other has a delay equal to one raster line (64 microseconds). The first circuit filters noise in the horizontal direction, while the second circuit filters in the vertical direction.

The circuit 900 may comprise a converter 40 for converting the f H 2f _t i <shown in more detail in FIG. 27. The reference numerals used in FIG. 27 are therefore shown in FIG. 20, in the lower left corner. The timing signals used in the circuit are derived from an oscillator 238 which operates at 32 MHz and is synchronized by a phase lock with 1024 times the horizontal deflection frequency of the display unit. These signals are supplemented by a deflection circuit return signal to input 2f, i. The center frequency of oscillator 238 is controlled by the outer LC circuit 974, while the outer loop RC filter 406 controls the phase locked loop characteristic. Phasing of internal timing signals (staples, blackout, etc.) can be adjusted relative to input 2fi via the serial bus.

The press input must also determine which of the pulses at the frequency of 2f _r appears at the beginning of the incoming line and which in the center of the incoming line.

The vertical pulse input, e.g., f, is used to detect the beginning of the field so that the correct rows are stored in the frame memory. The number of lines that elapses between the vertical pulse direction and the start of memory operation is adjustable via the bus command. A system of circuits for forming the interior The signal of frequency 2γη for excitation of the horizontal deflection system has already been described. Phase 2fh output relative to input lf-_ri it can be set using the serial bus.

The deflection circuit 50 is shown in detail in FIG. 22. The circuit 500 is designed to adjust the vertical dimension of the grid, in accordance with the necessary amount of vertical overshoot needed to produce various image formats. As schematically illustrated, the current source 502 provides a constant amount of current Irahf. The transistor 506 is connected in parallel to the capacitor 504, and it discharges it periodically in response to the vertical reset signal. If no adjustment is made, the maximum available vertical grid size is generated by the Irahf stream. This may correspond to the extent of the vertical overshoot needed to fill the wide screen display unit with an extended 4x3 aspect ratio signal source as shown in FIG. l (a). If a smaller vertical grid size is desired, the adjustable current source 508 will remove from the current I p.a f; f the variable amount of current Iadj. so that the vertical flip capacitor 504 charges more slowly and at a lower peak value. The adjustable variable current source 508 operates in response to a vertical dimension control signal, e.g., in an analog shape, formed by the vertical dimension control circuit 1030 shown in FIG. 49. The vertical dimension adjusting circuit 500 is independent of the manual adjusting of the vertical dimension 510, which may be a potentiometer or an adjustment knob in the rear panel. In both cases, an excitation current of the appropriate size is fed to the deflection coil or coils 512. The horizontal deflection is provided with a phase adjustment circuit 518, an east-west correction circuit 514, a phase locked feedback loop 520 at a frequency 2f ·; and a horizontal output circuit 516.

The color interface 60 is detailed and shown in FIG. 25. The signal to be displayed is selected between the output of the converter 40 for converting 1 fh to 2fh and the input of the external color signal. For the purposes of the described wide-screen color television according to the invention, the external input of the color signal is assumed to be a source of progressive deinterleaved widescreen video signal. The external color signals and the complete blanking signal from the video signal input circuit 20 are inputs of the converter 610 after the RGB signals are converted to the YUV signal, which is shown in FIG. 26. The external complete synchronization signal at frequency 1fn for the external color signal is input to the external synchronization signal separator 600. The selection of the vertical sync signal is performed by the switch 608. The selection of the horizontal sync signal is performed by the switch 604. The selection of the video signal is performed by the switch 606. Each of the switches 604, 606 and 608 is controlled by an internal / external impedance control signal. The choice of internal or external image sources is made by the user. However, if the user further selects an external color signal source 618, 620 and is not connected or plugged in, or if the external source fails, the vertical screen will collapse and the screen or screens may be seriously damaged. Therefore, the presence of an external synchronization signal is controlled by an external synchronization detector 602. If the necessary signal is not present, each of the switches 604, 606, and 608 is sent a blocking control signal to prevent the choice of an external color signal source. The converter 60 for converting the RGB signal to the YUV signal also receives control signals from the widescreen microprocessor 340.

The converter 610 is shown in detail and in FIG.

26. The synchronization components of the color signals are separated by the respective circuits 612, 614 and 616. The algebraic signals are combined! in summation circuits and 622, where R-Y (U) signals are generated,

B-Y (V) and Y. The transmission rate multipliers 628 and 634 beat the phase of the R-Y and B-Y signals so that the effective color of the signals changes even if the phase is not entirely suitable for the R-Y and B-Y phasers. Multipliers 640 and 638 then change phase to alternate the effective color tone regardless of the deflection of the R-Y and B-Y signals from the correct phase angle. The color and tone control signals may be generated by the Widescreen image microprocessor 340 controlled by the TV microprocessor 216. This allows easy control of the color and tone characteristics of the external color signal without the need for additional circuits or adjustment of the external color signal source alone.

For the Y signal, the difference is 7.5 IRE relative to the correctly defined black level. Compensation is performed by a correction blanking circuit 648 which inserts a 7.5 IRE offset. The KEY signal is a control signal formed in the front delay of the video signal behind the rear of the vertical sync signal and before the start of the active image. The KEY signal determines kdv to be keyed in circuit 646. The delay circuits 624 and 626 determine the exact phase relationship of the R-Y, B-Y, and Y signals despite subsequent changes as a result of the color control instruction and the color tone.

An overall block diagram of a widescreen television 11 according to the invention, adapted for operation with the line decomposition at the frequency ilf ', is shown in FIG. 4. Tern components of television! 11, which basically correspond to their counterparts! in the television 10 shown in FIG. 2, the same reference numerals are assigned. The television 11 generally comprises an input circuit 21 for receiving video signals, a TV microprocessor 216, a widescreen image processor 31, a horizontal deflection circuit 52, a vertical deflection circuit 56, a matrix circuit 241, a screen driver 242, a direct observation or projection type screen 244 and a power supply 70. The lfn to 2fh converter and RGB interface are not used. Accordingly, measures are provided for displaying an external color signal having a widescreen display format at a scanning frequency 1fn. The grouping of the different circuits into functional blocks is made to facilitate the description and is therefore not intended to limit the relative physical position of these circuits.

The input circuit 21 for receiving video signals is adapted to receive a plurality of complete video signals from different sources. The video signals may be selectively switched to be displayed as main and auxiliary video signals. The radio frequency switch 204 has two antenna inputs ΝΤΙΝΤΙ and ANT2. These also represent inputs for both outdoor and cable reception. High-frequency switch

204 determines which of the antenna inputs is routed to the first tuner 206 and which to the second tuner 203.

The output of the first tuner 206 is an input to a single-chip circuit 203 which performs a number of functions related to tuning, horizontal and vertical deflection, and video signal control. In particular, the illustrated single-chip circuit bears the industrial type designation TA8680. The baseband VIDEO OUT video signal formed in the single chip circuit 203 from the signal at Any of the first tuner 206 is the input of the video signal switch 200 and the input of the TV1 of the widescreen processor. Other baseband video signal inputs to the video signal switch 200 are designated AUX1 and AUX2. These inputs can be used for camcorders, VCRs and similar devices. The output of the video switch 200, which is controlled by the TV microprocessor 21, is labeled SWITCHED VIDEO, which is the current additional input of the widescreen processor 31.

As shown in FIG. 5, the widescreen processor switch SW1 selects TV1 and SWITCHED VIDEO signals, the output being a SEL COMP OUT video signal applied to the Y / C input of the decoder 210; the encoder can be implemented as an adaptive line comb filter. Another source of SI video signal is also input to the Y / C decoder 210. Source SI is an S-VHS source and consists of separate luminance and chrominance signals. The switch, which can be implemented as part of a decoder 210, in some of the adaptive row comb filters, or as a standalone switch, responds to the TV microprocessor 216 signals and selects one of the luminance and chrominance signal pairs, designated as Y M and C IN outputs. The selected pair of luminance and chrominance signals is then considered to be the main signal and is processed in the paths of the main signal path. The decoder / demodulator arranged in the widescreen processor 301 generates color difference signals U M and V M. The signals Y.M, UM and V M are then converted to the digital form in the widescreen processor 31 for further processing in the gate array 300.

The second tuner 208, which is functionally defined as part of the widescreen processor 31, generates a baseband video signal TV2. The switch SW2 selects between the signals TV2 and SWITCHED VIDEO as Y / C inputs of the second decoder 220. The second decoder 220 may be an adaptive row comb filter. The switches SW3 and SW4 make a choice between the luminance and chrominance outputs of the decoder 220, the luminance and chrominance signals of the external video source indicated by Y EXT / C EXT and the Y M, C IN signals. The YEXT / CEXT signals correspond to the S-VHS input S1. The decoder 220 and the switches SW3 and SW4 may be combined, for example, in adaptive row comb filters. The output of switches SW3 and SW4 is then considered as an auxiliary signal and is further processed in the auxiliary signal path circuits. The selected luminance output is indicated by Y A. The selected chrominance signal is converted to color difference signals U_A and V A. The signals Y A, U A and V A are then converted to digital form for further processing. The arrangement of the apparatus for switching the video signal sources into the main and auxiliary signal paths provides maximum flexibility in making the source selection for different parts of the different display formats.

The widescreen processor 31 includes a picture-in-picture processor 320 that processes the auxiliary video signal. The term picture-in-picture is sometimes abbreviated as PIP or pix-in-pix. Gate field

300 combines main and auxiliary video signal data into a variety of display formats, some of which are shown in FIG. l (b) to 11c). The image-in-picture processor 320 and the gate array 300 are controlled by a widescreen microprocessor 340. The microprocessor 340 is in communication with the TV microprocessor 216 via a serial bus. The serial bus contains four signal lines for data, clock pulses, opening signals and adjustment signals. The widescreen processor 31 further generates a complete vertical blanking and adjustment signal in the form of a three-wave sandcastle signal. Alternatively, vertical blanking and adjustment signals can also be generated as separate signals. The complete blanking signal is then routed through an input section for receiving video signals to the RGB interface.

The horizontal and vertical sync components of the main signal are formed in the separator 286 of the sync signal that forms part. a demodulator 288 arranged in a widescreen processor 31. The horizontal synchronization component is the input of the feedback loop Phase Curtain 290 with a frequency of 1 f_i; . The horizontal and vertical synchronization signals of the auxiliary video signal are produced in the synchronization signal splitter 250 arranged in the wide-screen processor 31. The horizontal deflection circuit 52 cooperates with the single-chip circuit and responds to the east / west adjustments and the horizontal phase control signals of the widescreen microprocessor 340. The vertical deflection circuit 56 is controlled by the vertical dimension control circuit 54. The vertical dimension control circuit 54 responds to the vertical dimension control signals transmitted by the widescreen image microprocessor 340 and works similar to the vertical dimension control circuit described above. The 2 f c processor for a widescreen television is shown in more detail in FIG. 5. The main components of the widescreen processor 31 are the gate array 300, the picture-in-picture circuitry 301, analogue digital and digital analogue converters, a second tuner 208, a widescreen microprocessor 340, and a widescreen output encoder 227. Further details of the widescreen image processor 31, which are common to both the imaging and imaging circuits, such as the imaging circuit in the image, are shown in FIG. 6. The PIP 320 that forms a substantial portion of the PIP 301 is illustrated in more detail in FIG. 7. The gate array 300 is shown in more detail in FIG. 8. A series of components shown in FIG. 3 and constituting portions of the main and auxiliary signal processing pathways described in detail above. a number of other components, such as a second tuner 208, a widescreen image processor 340, interconnection outputs, analogue digital and digital analogue converters, gate array 300, an image-in-picture circuit 301 and a phase-locked feedback loop 374 operate substantially as explained Referring to FIG. 3, so that their detailed description is not repeated.

The main video signal is fed to the widescreen processor 31 in an analogue form as YM and C_IN signals. The signal C IN is decoded by demodulator 288 to the color difference signals UM and the W A. The main signal is then converted from analog to digital form the analog ^_ čis1icovými converters 342 and 346, which are shown in more detail in FIG. 6. The auxiliary image data is also in analogue format and in YUV format as marked signals

YA, UA and V A. In the PIP 301, these auxiliary signals are converted to digital form, then the data is compressed and stored in a field memory for synchronization with the main signal and then passed to the gate array 300 where they combine ! The operation of the PIP 301 is explained in more detail with reference to FIG. 6. The image-in-picture circuit 301 and / or gate array 300 may also include means to improve the resolution of the auxiliary data, even when compressed. The analogue signals, designated Y, U, and V, are routed to encoder 227 to produce YOUT EXT / C OUT EXT signals in widescreen format, which in this case are inputs to single-chip 203. The encoder receives only C signal from gate array 300. SYNC MN. Switch SW5 selects between the Y M and C signals of SYNC AUX as inputs of analog-to-digital converters. The single-chip circuit 203 generates YUV signals for the RGB matrix circuit 241, which generates RGB signals for the display drivers 242 from the Y OUT EXT and C OUT EXT signals.

Fig. 6 is a block diagram illustrating further details of widescreen image processors 30 and 31 common to 1 and 2, as shown in FIG. 3 and 5, Signals Y.A, UA, and VA are inputs of the image-in-image processor 320 that may include a resolution control circuit 370. The widescreen television of the invention can compress and stretch the image. These particular effects represented by the various associated display formats shown in FIG. 1, are generated by an image-in-picture processor 320 that can receive resolved data signals RP, U RP, and V RP from the 370 &apos; zeni rozlíšení. Distinguishing processing may not always be used, but only during selected display formats. The picture-in-picture processor 320 is illustrated in detail in FIG. 7. The main components of the processor 320 are the analog-to-digital converter section 32, the input section 324, the quick-change section and the bus section 326, the timing and control section 328, and the digital analogue section 330. The timing and control section 328 is shown in more detail in FIG. 14th

The PIP processor 320 may be designed as an improved variation of the CPIP base chip. It allows a number of special functions or effects, the following of which are illustrative. The basic special effect is a large image, part of which is covered by a smaller image, as shown in FIG. l (c). Large and small images may be formed from the same video signal or different video signals, and may be interchanged or moved. Generally, the audio signal is always switched to match the large picture. The small image may be moved to any position on the screen or it may advance through a number of predefined fields. The zoom function allows the size and size of a small image to be increased and reduced, for example, to any series of predetermined sizes. At some point, for example, the format shown in FIG. l (d), have a small and large image of substantially the same size.

In the single-image mode, for example, the formats shown in FIG. l (b), l (e), or l (f), the user can zoom in on a single image content, for example in steps of 1.0: 1 to 5.0: 1, while in zoom mode, the user can view which nine images give or pan the content of the image, while the shadowed image can move through different areas of the image. In both cases, a small image, a large image, or a zoomed image may be displayed as a still image (still image format). This function allows the stroboscopic format to be repeated on the screen. The frame rate can be varied from thirty frames per second to zero frames per second.

The picture-in-picture processor 320 used in the widescreen television of the present invention is somewhat different from the basic embodiment of the CPIP type chip. If a CPIP base chip was used on a 16x9 TV without using an image acceleration circuit, the embedded images would have a distorted porter as a result of a 4/3 fold horizontal stretching resulting from the wider screen degradation.

The objects in this image would be horizontal elongated. If it was used external, it would distort the ratio of grazing, did not fill the screen.

Existing picture-in-picture processors, which are based on a basic CPIP-type chip and used in conventional television apparatus, have certain undesirable characteristics. The incoming video signal is sampled using clock pulses at a frequency of 640fi, which are coupled to the horizontal synchronization signal of the main video source. In other words, the data stored in the RAM-type image memory, merged with the CPIP-type chip relative to the incoming auxiliary source sampled orthogonal. This is a fundamental limitation of the field synchronization using the basic embodiment of the CPIP chip. The unorthodox nature of the input pattern accelerator circuit, but the image would not be a forge velocity signal results in parallelogram distortions of the sampled data. The limitation is a consequence of the RAM image memory used with the CPIP chip, which must use the same clock pulse for writing and retrieving data. If data from RAM image memory, such as RAM image memory 350, is displayed, parallelogram distortions appear as random jitter along the vertical edges of the image and are generally considered to be completely unacceptable.

The picture-in-picture processor 320 of the present invention, distinct from the basic embodiment of the CPIP chip, is adapted to asymmetrically compress the image data in one of a variety of selectable display modes. In this operating mode, images are compressed in a 4: 1 ratio in the horizontal direction and in a 3: 1 ratio in the vertical direction. This asymmetric compression mode creates images of distorted porn that are stored in RAM image memory. The objects in the pictures are horizontally compressed. However, these images are taken out of memory normally, for example by channel scanning, for subsequent display on a 16x9 display format screen. The picture fills the screen and the ratio of its sides is not distorted. Asymmetric compression according to this aspect of the invention allows the creation of special display formats on a 16x9 screen without the need for an external set of acceleration circuits.

Fig. 14 is a block diagram of a timing and control circuit 328 of an image-in-picture processor 320, for example a modified version of the above-described CPIP. The timing and control section 328 includes a decimation circuit 328C that performs asymmetric compression as one of a number of selectable display modes. Auxiliary images of different sizes can be performed with the remaining display modes. Each of the 40 horizontal and vertical decirculators comprises a counter that is programmed for a compression coefficient selected from a table value driven by a widescreen microprocessor 340. The value range may be 1: 1.2: 1, 3: 1, and so on. The compression coefficients may be symmetrical or asymmetrical depending on the table design. Control of the compression ratios can also be accomplished with full programmable universal decimation circuits controlled by a widescreen microprocessor 340. The decoder circuit 328C is detailed! shown in FIG. 15 to 18.

Fig. 15 is a block diagram. a circuit for performing horizontal compression. The circuit comprises a decirement circuit formed by a counter 850 denoted by MOD N CNTR.1. The numeric value at input N is the horizontal coefficient N, denoted by HOR N FACTOR. The horizontal coefficient N refers to the extent to which the size of the picture represented by the image data of the auxiliary signal will be reduced to be displayed as picture in picture or as picture out of picture. This coefficient is also a measure of the speed at which the pixels in a row are sampled. The numeric input for the input value is set to 0. The asynchronous output (RCO) is a horizontal line sampling opening signal. Fig. 16 is a block diagram of a circuit for performing vertical compression. The circuit comprises a decrement circuit formed by a counter 858 denoted MOD N CNTR2. The numeric value at input N is the vertical coefficient N, denoted by VERT N FACTOR. The vertical coefficient N also relates to the extent to which the size of the picture represented by the picture data of the auxiliary signal to be displayed as picture in picture or picture out of picture is reduced, but in this case it is a measure of the row pin selected for subsampling. The numeric input of the input value is determined by a numerical calculation based on the vertical coefficient N. The vertical coefficient N is added by 2, the sum is then divided by two and the division result is matched with the U / L FIELD TYPE signal to distinguish between upper and lower strings. The counter output 858 is a vertical line sampler opening signal.

The horizontal and vertical coefficients N are formed by the circuit 859 shown in FIG. 17. The input is the NFACTOR value, which ranges from ΰ to 7. Each pair of horizontal ratios as shown by the table to the value of N corresponds to a vertical compression, FIG. 18. N FACTOR values are generated by a widescreen image microprocessor 340. Circuit 859 includes multiplexing circuitry 862 and 864 and circuit 860 for comparison with the δ value. For each N FACTOR value other than 6, the horizontal and vertical compression ratios are symmetrical, due to the zero-input multiplexing circuits. if N FACTOR has a value of 6, the one inputs of the multiplexing circuits are keyed as outputs. These inputs result in asymmetric compression, 4: 1 in the horizontal direction and 3: 1 in the vertical sine.

Counters in decimation circuits are shown as integer decimators. However, the processing need not be limited to compressing the images in all other increments, provided that the horizontal compression coefficient is 4/3 times the vertical compression coefficient. Also, asymmetric compression is not limited to wide-format 16 x 9 format devices. If the ratio is less than 2: 1, the horizontal compression coefficient would be 1 3/2 times the vertical compression coefficient.

Control of the compression ratios can also be accomplished by full programmable universal decimation circuits controlled by a widescreen microprocessor 340, as shown in FIG. 19 (a) and 19 (b). The horizontal compression coefficients are formed by the circuit shown in FIG. 19ia), which consists of a summation point 866, an array 868 of eight OR-type gates, and an inverter 870. Each bit of the 8-bit output of the gate array 868 has a logic 1 state if the H RESET signal is supplied: field 868 equals the field input, which is the output of the summation point 866. The vertical compression coefficients are formed by the circuit of FIG. 19 (b), which consists of a summation point 872, a multiplexing circuit 874, and an inverter 876. In each circuit, the summing point transmission input C1 is coupled to a voltage for a constant level 1 logic signal. opening signal. In the circuit of FIG. 19 (b), the one input of the multiplex circuit is coupled to ground to obtain a constant level 0 logic signal. The horizontal and vertical compression coefficients may be supplied from a widescreen microprocessor 340.

In full-screen picture-in-picture modes, the picture-in-picture processor receives, in conjunction with the free oscillating oscillator 348, as a Y / C input of a decoder, such as an adaptive row comb filter, decodes this signal into YU V color components and generates horizontal and vertical sync pulses. These signals are processed in the picture-in-picture processor for various full-screen modes, such as zoom, still picture, or channel scanning. For example, in the channel decomposition mode, the horizontal and vertical sync components fed from the video input input section have many discontinuities because the sampled signals (different channels) have different sync pulses and are switched at seemingly random time frames.

Therefore, the clock sampling signal (and the clock signal for reading and writing in the RAM) is determined by a free oscillating oscillator. For still image or zoom modes, the clock sampling signal is coupled to a horizontal synchronization component of the incoming video signal, which in these special cases is the same as the clock frequency for display.

As again shown in FIG. 6, the Y, U, V, and C outputs of the SYNC (sync line) of the PIP 320 in analog form can again be encoded into Y / C components by a coding circuit 36, which is in cooperation with an oscillator 380 at a frequency of 3.58 MHz. This signal, labeled Y / CPIP ENC, may be connected to a Y / C switch (not shown) which allows the Y / C components of the main signal to be replaced by the encoded Y / C components from the coding circuit. From this moment, the encoded Y, U, V picture-in-picture signals and the synchronization signals are the basis for horizontal and vertical timing in the rest of the apparatus. This mode of operation is suitable for performing an in-picture zoom mode based on the operation of the interpolator and the attendant memory in the order of arrival arranged in the main signal path circuits.

In the multi-channel mode as shown in FIG. 1 (i), twelve small images of the twelve channels may be displayed simultaneously in accordance with a predetermined decomposition order, the image-in-picture processor 320 having an internal clock source, controlled by an oscillator 348 at 3.58 MHz. The incoming auxiliary signal is converted from analog to digital, and, depending on the special effect selected, it is loaded into the RAM image type 350. In the prior art, the compiled special effect is converted back into an analog form in the image-in-picture processor, then combined with the main signal data. However, in the widescreen television described, partly due to the limitation of the number of possible different clock frequencies, the auxiliary data is output by the RAM image memory 350 without being further processed by the PIP 320. Preferably, however, minimizing the number of clock signals reduces the noise that occurs in television circuits.

As further shown in FIG. 7, the image-forming processor 320 includes an analog-to-digital converter section 322, an input section 324, a quick-change and bus section 326, a timing and control section 328, and a 330-to-analog converter section. Generally, the PIP 320 digitizes the video signal to a luminance signal Y and color difference signals U, V, while additionally sampling the results and storing them in a 1 megabit RAM image memory 350, as explained above. The RAM image memory 350 associated with the processor 320 has a capacity of one megabit, which is not sufficient to store the entire field of image data in 8-bit patterns. Increasing memory capacity is costly and may require a more complex set of control circuits. A smaller number of bits per sample in the auxiliary channel, in turn, represents a reduction in quantization resolution or bandwidth relative to the main signal, which is processed exclusively in eight-bit samples. This effective bandwidth reduction is usually not a problem if the additional display image is relatively small, but can cause difficulties if the image is too low.

-. 45, for example, the same size as the main image. The resolution control circuit may optionally perform one or more schemes to improve the quantization resolution or effective bandwidth of the auxiliary image data. A number of data reduction and recovery schemes have been developed, including, for example, push

Reading pairs of pixels, adding and subtracting coded signals The circuit for adding coded signals would be functionally arranged behind the image memory.

350 of the RAM type, for example, in an auxiliary signal path in the gate array 300, as explained in more detail below. In addition, different sequences of encoded signals comprising different bit counts, and different methods of compressing pairs of pixels at different bit counts are contemplated. One of these data reduction and recovery schemes may then be selected by the widescreen image microprocessor 340 to achieve maximum display resolution for each particular type of display format.

The resolution control circuits are explained in more detail in connection with FIG. 56 to 70.

The luminance and color difference signals are six-bit components Y, U, V in proportion

1: 1st In other words, each component is quantized into six-bit samples, and there are eight luminance samples per pair of color difference samples. The processor 320 of the image forming in the image in an operating mode, in which the incoming video data is sampled frequency clock signal _{640F, and} which in this case is coupled to the synchronizing component of the incoming video signal. In this mode, the data stored in the RAM of the sample is orthogonal. If the data from the picture memory 350 of the PIP 320 is read, it is stored at 8 pulses coupled to the incoming video input signal using the same 640f clock rate. However, although these data are sampled and stored orthogonal and can be read orthogonally, they cannot be orthogonally displayed directly from the RAM 350 due to the asynchronous nature of the hiavnibo sources and the auxiliary video signal. Sources of the main and auxiliary video signals could be considered synchronous only if they displayed signals from the same video source.

Further processing is required to synchronize the auxiliary channel, which is the data output of the RAM 350, with the main channel. Again, as shown in FIG. 6, two 4-bit inverters 352A and 352B are used to recreate the 8-bit data blocks by combining the 4-bit video RAM output 350. The four-bit inverters also reduce the frequency of the data clock pulses from 128p to 640fh.

The display unit and the deflection assembly are generally synchronized with the main video signal. The main video signal must be accelerated to fill the wide screen as explained above.

The auxiliary video signal shall be vertically synchronized with the first video signal and the display unit. The auxiliary video signal may be delayed in the polished memory by a fraction of the polished period, and then expanded in the line memory. Briefly, the synchronization of the auxiliary image data with the main image data is performed using the RAM image memory 350 as a field memory and the line memory 354 with the attendant order of arrival of the signal. The auxiliary signal path interpolator 359 may correct the acceleration in the memory 354. The size of the handler memory 354 in the arrival order is 2048 x 8. Problems that may arise during the synchronization of the main and secondary signals consist of collision read and write pointers in the memory operator 354 according to the order of arrival in the auxiliary signal path and maintaining interleaving integrity. . A field synchronization system which avoids such collisions of read and write indicators and which maintains the integrity of the fields is explained by FIG. 26 to 36.

The gate array 300 is common to both widescreen processors, i.e. both the processor 30 and the processor 31. The main signal path 304, the auxiliary signal path 306, and the output signal path 312 are shown in the block diagram of FIG. The gate array 300 also includes a timing and synchronization circuit 320 and a widescreen microprocessor decoder 310. The data and address outputs of the widescreen microprocessor decoder 310, referred to as WSP DATA, are routed to each of the main circuits and paths listed above as well as to an image-in-picture processor 320 and a resolution control circuit 370. Obviously, whether or not certain circuits are defined as being part of the gate array is due largely to the need to facilitate explanation of the various embodiments of the invention.

The gate array 300 is configured to expand, compress, and trim the image data of the main image channel and, if necessary, to perform various forint images. The luminance component Y MN is stored in the operator memory row 356 in the arrival order for a time depending on the type of interpolation of the luminance component. The combined U / V MN color components are stored in a memory 358 with the operator in the arrival order. The luminance and chrominance components of the Y PIP, U PIP, and V PIP auxiliary signals are generated by the demultiplexing circuit 355 · The luminance component is subjected to a resolution processing in circuit 357 (if necessary) and then expanded as needed by interpolator 359, outputting a Y AUX signal .

In some cases, the additional image is the same size as that of the main signal, as shown in FIG. l (d). The capacity limitation of the RAM type of image RAM 350 associated with the PIP 320 may not provide a sufficient number of data points or pixels to fill such a large display area. In these circumstances, a resolution control circuit 357 may be used to restore the pixels of the auxiliary video signal to replace the pixels lost when the data is compressed or reduced. The resolution processing may correspond to the processing performed by the circuit 370 shown in FIG. For example, circuit 370 may be a circuit for adding coded signals and circuit 357 may be a circuit for reading coded signals. The auxiliary signal interpolation may be performed in the auxiliary signal path 306, which is shown in detail in FIG. 12. The picture-in-picture circuitry 301 shown in FIG. 6, they control a field memory for the 6-bit Y, U, V components stored in an 8: 1: 1 ratio, which is the image RAM of 350 RAM. The image RAM 350 always holds two bands of image data in a plurality of memory locations. Each memory location stores eight bits of data. One 8-bit Y sample (brightness), sampled at 640f, and 2 additional bits are stored in each 8-bit location. These two additional bits contain either fast switching data (FSW DAT) or a portion of the U or V sample (sampled at 80 µl). The FSW_DAT values in the following way indicate which type of file was written to the RAM:

FSW DAT = 0: no image,

FSW__DAT = 1: top (odd) field, a

FSW_DAT = 2: Bottom barrels.

The frames in the RAM image occupy spatial positions whose boundaries are defined by horizontal and vertical addresses, as shown in the memory location diagram of FIG. 37. The boundary at these addresses is defined by changing the quick switch data from the no-image position to the active-field position and vice versa. These quick switch data transitions define the perimeter of the picture embedded in the picture, also referred to as the clipboard or the picture-in-picture overlay. It will be appreciated that the aspect ratio of the objects in the image embedded in the image may be controlled independently of the aspect ratio of the clipboard format or the image-in-image overlay, e.g. 4x3 or 16x9. The position of the embedded image on the screen will be determined for each frame of the main signal by the starting address of the RAM reader at the start of scanning. Since two RAMs of data are stored in the RAM image memory, and the entire RAM image 350 is read during the display period, both frames are read during the display decomposition. The picture-in-picture circuitry 301 determines which image will be read out of the display memory by fast switching data and a read pointer start position. It may seem logical that if the imaging unit that is coupled to the main video source is just displaying the top image of the main image, then that portion of the RAM image corresponding to the top image of the auxiliary image would be read, and converted to analog data and display.

This would be feasible for about half of all possible phase relationships between the main and auxiliary video signal sources. Problems, however, arise. that the reading of the RAM is always faster than writing the pictures compressed into the RAM in the PIP mode. The memory read pointer may override the write pointer if the same type of field is read and written at the same time. The result would be a 50% probability of tearing the movement in some place of a small image. The image-in-picture circuit therefore always reads a strip of the opposite type to that currently being written in the strip to overcome the problem of tearing movement. If the type of image currently being read is opposite to the type of field that is being displayed, then invert the even field stored in RAM by deleting its upper row when it is read out of the memory. As a result, a small image maintains proper interleaving without jerking movement. The end result of this field sync is that the CPIP chip produces a signal called the PIP FSW. This is an overlay signal that the PIP produces an analog switch that switches the Y / C signals of the main and sub channel (brightness and modulated color image information).

Auxiliary image input data is also sampled at frequency

640 f h and stored in a RAM image 35. Auxiliary data read from this memory is labeled VRAM OUT. The picture-in-picture circuitry 301 is also able to reduce the auxiliary image by integer coefficients equal in horizontal and vertical directions as well as asymmetrically. As further shown in FIG. 12, the auxiliary channel data is buffered and synchronized with the main channel digital video signal by the four-bit inverters 352A and 352B, the auxiliary channel auxiliary memory 354, to properly display the arrival order, the timing circuit 369, and the synchronization circuit 371. Data The VRAM OUT with the demultiplexer 355 is sorted to Y (brightness), U, V (color components) and FSW-DAT (fast switching data). The FSW DAT indicates which type of frame 1 would be written to the RAM. The PIP FSW signal is received directly from the PIP and passed to the output control circuit. Here, encryption is performed to determine which of the fields read from the RAM is to be displayed. Finally, the data of the auxiliary video channel components to be output is selected by means of the three multiplexing circuits 315, 317 and 319 shown in FIG. 8. Instead of superimposing a small picture in the picture using an analog switch in the coupled or Y / C coupler circuit as in the CPIP chip, the widescreen microprocessor 340 performs in-picture digital in-picture overlay · However, as described below, the PIP FSW control signal is needed to control the digital overlap common to the FSW DAT signal.

The sub-channel is sampled at 640 γη, while the main channel is sampled at 1024 f n. The arrival memory 354 is 2048 x 8 and converts the data from the sub-channel sampling frequency to the main channel clock frequency. In this process, the video signal is subjected to an 8/5 (1024/640) compression, which is more than a 4/3 compression, which is necessary to correctly display the signal. The required range of expansion by the interpolator is 5/6. The expansion coefficient X is determined as follows:

X = (640/1024) x (4/3) = 5/6

Thus, a small picture can be properly displayed in a 4x3 format by setting the interpolator 359 to perform a 5/6 stretching (5 input samples, 6 output samples), regardless of how it is scaled down by the image-in-picture processor.

The FSW PIP data does not provide sufficient interpretation. Which half of the RAM image associated with the CPIP type chip should be displayed, since the PIP data is horizontal rasterized for the correct PIP ratio; preserved preservation Although the overlap of the picture in the picture would be dimensioned. The only overlay of the image is correct interleaving, the area would generally have a wrong horizontal horizontal case where the size of the area in the image was correct. would occur when stretched at a 5/8 ratio using interpolator 359. resulting in a small 16 x 9 image. For all other interpolator 359 settings, the overlap circumference would remain in 16 x 9 format while the embedded image would change horizontally. Signal a sufficient amount of image overlap dimension information in

PIP FSW contains neo horizontal picture. The data stored in the picture memory is read before the picture-in-picture circuitry completes the synchronization algorithm. Thus, the FSW DAT fast-switching data contained in the RAM is included in the VRAM-OUT data stream from the video, corresponding to the type of field written to the RAM. Although the image component data (Y, U, V) stored in the RAM is corrected to prevent jitter and correct interleaving, the FSW DAT signal is not modified.

In accordance with the present invention, the PIP circuit is of the correct size since the FSW DAT information is stretched and interpolated in common with the data components Y, U, V. The FSW DAT signal contains information to correctly determine the size of the overlay area but does not indicate which from the field is the right field to display. PIP FSW and FSW DAT signals can be used in common to overcome the interleaving integrity problem and the correct overlap size. In normal operation, when a CPIP-type chip is used in 4x3 TVs, the placement of the image in the RAM is arbitrary. Fields can be arranged vertically or horizontally or not at all. In order to be functional with the widescreen processor compatibility, it is necessary that the positions of the image-in-picture images are not stored in the memory on the same vertical lines. Other glory, picture-in-picture strips may not be programmed using the same addresses for upper and lower strips. From a programming point of view, it is desirable to store the picture frame images in the picture in the RAM image memory 350 vertically aligned, as shown in FIG. 37th

The PIPOVL signal controls the output control circuit 32i so that the auxiliary data is displayed when the signal is active, i.e., if it has a logic one level. A block diagram of the PIP OVL signal generating circuit is shown in FIG. Circuit 680 includes a JK type flip-flop 682 whose output Q is one of the inputs of the multiplexing circuit 688. The output of the multiplexing circuit 688 is an input of the D-type flip-flop 684 whose output Q is the second input of the multiplexing 688 and simultaneously one of the product 690. The FSW and SOL (PIP) signals are respective inputs J and K of flip-flop 682. The non-equivalence circuit 686 has two inputs for the FSW DATO and FSW DAT1 bits of the fast switching data. The values (1,0) and (0, 1), which are logically exclusive inputs, indicate a valid field as even or odd. Values (0.0) t

- 54 and (1,1), which are not logically exclusive, indicate the absence of valid data. The transition from one of the pairs (0.1) or (1.0) to one of the pairs (1.0) or (1.1), or vice versa, indicates a boundary delimiting or overlapping picture in the picture. The output of exclusive OR circuit 686, the second AND gate 690. vstupern vstupern third AND gate 690, the signal RD ENAX, a read enable signal for the auxiliary Parnet 354 _with service in the order of arrival. The output of the gate 690 is a PIP OVL signal. Circuit 680 introduces a one-line delay (one line of dowsing poles) from the moment the PIP FSW becomes active to actually access the overlap area. This is also counted in the image data path, as the operator's handrails 354, in the arrival order, also introduce a delay of one line of a field for image data in the image. The picture-in-picture overlay is therefore perfectly aligned with the picture data, although it is delayed by one line of the line to be programmed in the picture-in-picture circuitry. The RD EN AX signal allows the picture in picture to be overlaid only if valid auxiliary data has been read from the operator's memory 354 in the arrival order. This is necessary because the data from the memory 354 can be retained even after the reading is completed, which may cause the PIP overlay to determine that the overlay is active outside the valid PIP. Enabling picture overlay over the RD EN_ÄX signal ensures that picture-in-picture data is valid. In accordance with the invention, the overlay or small accessory receptacle is correctly positioned and sized, regardless of how the auxiliary video signal has been expanded, compressed or interpolated. This applies to small picture signal sources of formats

5.5

4x3 and 16 x 9 and many other formats.

The colorant components of U PIP and V PIP are. circuit 367 is delayed by a period of time depending on the kind of interpolation of the luminance component at which the outputs U UX! and V AUX. Relevant ingredients Y.

!

U and V of the main and annual signals are combined

in the respective multiplexing circuits 315, 317 and 319 arranged in the path, the loops are controlled

312 of the output signal such that the read signals of the memory 354, 356, and 358 are handled in the order of arrival. The multiplexing circuits 315, 317 and 319 are controlled by the control circuit 321

The multiplexer output control circuit 321 is controlled by a clock signal CLK, a line start signal SOL, a H COUNT signal, a vertical blanking adjustment signal, and an output of the PIC processor 320 and a widescreen microprocessor 340. Multiplexed luminance The color components Y MX, U_ MX and V MX are routed to the respective digital analogue transmitters 360, 362 and 364. After the digital analogue transducers, the low-pass filters 361, 363 and 365 shown in FIG. 6. The various functions of the PIP 320, the parallel array 300, and the data reduction circuit are controlled by the widescreen microprocessor 340. The widescreen microprocessor 340 responds to the signals of the TV-microprocessor 216 to which it is connected to the serial bus. The serial bus may be a four-wire bus as shown. having lines for data, clock signals, enable signals, and set signals. The widescreen microprocessor 340 is coupled to the various circuits of the data field 300 via a decoder 310.

In one case, it is necessary to compress the NTSC video signal and 4x3 format using a 4/3 coefficient in order to clog distortion of the porosity of the displayed image. In the latter case, the image may be stretched to perform horizontal zoom functions. usually accompanied by vertical zoom. Horizontal zoom up to 33% can be performed by reducing the compression to less than 4/3. A sample interpolator is used to recalculate the incoming video signal to new pixel positions, since the luminance bandwidth of the video signal f for the S VHS format is up to 5.5 MHz) consuming a significant percentage of the frequency by Nyquist translation. which for the clock signal 1024 f h is Θ MHz.

As shown in FIG. 8, the luminance data Y MN is conducted by an interpolator 337 arranged in a main signal path 304 that recalculates sample values based on image compression or stretching. The function of the switches or directional selectors 33 and 331 is to reverse the topology of the main signal path 304 relative to the relative position of the in-service memory 356 in the order of arrival and interpolator 337. These switches thus select whether interpolator 337 is in front of memory 356 as needed. compression, or whether the picture memory 356 preceding the interpolator 337, _making it is desired to expand. The switches 323 and 331 are controlled by a direction control circuit 335 which is controlled by a widescreen microprocessor 340. It should be remembered that in small-picture modes, the auxiliary video signal is depressed when stored in an image memory of 50 50 ΙΐΛΜ and pi> io i if only such stretching is required. Therefore, similar switches are not needed in the auxiliary signal path 306.

The main signal path 304 is detailed and shown in FIG. II (a). The switch 323 is formed by two multiplexing circuits 325 and 327. The switch 331 is formed by a multiplexing circuit 333. These three multiplexing circuits are controlled by a direction control circuit 335 which is controlled by a widescreen microprocessor 340. The horizontal timing and synchronization circuit 339 creates such write and read from memory. The clock signal CLK and the start signal SOL are formed by the timing and synchronization circuit 320. The control circuit 369 of the analog-to-digital converter control is controlled by the Y MN signal, the widescreen signal. microprocessor 340 and the highest valid bit of the UV MN signal.

The interpolation control circuit 349 generates values (K) of the intermediate positions of the pixels, the weighting (C) of the interpolation compensation filter, and the clock keying information CGY for the luminance bed and CGUV for the chrominance components. Leave hourly clocking information omitted! (decimating) or repeating data stored in operator memories in the order of arrival, allowing samples to not be written at some clock pulses (to create squeezes) or read multiple times (to create stretches).

Such compression is illustrated in FIG. 11 (b). The LUMA RÁMP IN line represents linearly rising luminance data written to the operator's memory in the order of arrival. The WR EN MN Y signal is active at the logical one level, which means that if the signal has a logical one level; data is written to memory. Every fourth sample is prevented from being written. The serrated line of the LUMA RÁMP OUT represents the rising luminance data as it would be 1 and read from the operator memory in the order of arrival if it was not interpolated first. The average slope of the luminance data readout characteristic is, as shown in FIG. 11 (b),% steeper than the pitch of the data being written. Need active

I

Ení the reading time is 33% shorter than the time needed to write data. This creates a 4/3 compression. Interpolator 337 recalculates luminance samples written to the operator's memory in the order of arrival so that the read data characteristic is smooth and not serrated.

Expansion can be carried out in exactly the opposite direction of compression. If pressed, the clock enable information in the form of blocking pulses is connected to the write enable signal. As the data is expanded, the clock keying information is coupled to the read enable signal. Thereby, delays are introduced between the data as it is read from the operator memory 356 in the arrival order, as shown in FIG. 11 (c '). The LUMA RAMP IN line represents the data before it is written to the memory 356, and the wavy LUMA RAMP OUT line represents the data as it is read from the 356, V interpolator, which includes the sampled data count from the undulating to a smooth shape characteristic after stretching. The data must be delayed when read from memory 356 and clocked in interpolator 337 in the event of stretching. This is different from the compression when clocking is continuous when passing through interpolator 337. In both cases, e.g. j. when compressed and expanded, the clock germination operations can be easily performed synchronously, i. j. using the leading edges of the clock pulses of the 1024 f system;

This luminance interpolation topology has a number of advantages. Hourly germination operations, i. j. omitting and repeating data, can be performed synchronously. If the switchable image data topology was not used to interchange the positions of the interpolator and the memory, the read or write clock pulses would eventually perform beyond the memory 356 or be duplicated, which means that in a single clock cycle they would have to be written or read from remember two data points. The resulting circuitry could not operate synchronously with the system clock pulses, since the write or read frequency would have to be twice as high as the clock frequency of the system. In addition, the switchable topology requires only one interpolator and one operator memory in the order of arrival, which performs both compression and expansion. If the described video signal switching was not used, double clocking could only be avoided by using two operator-handled memories in order to assure both compression and expansion. The expansion memory would have to be located in front of the interpolator and the compression memory downstream of the interpolator.

One of the conditions for proper operation of the circuit is that the number of data samples written to the operator's memory in the order of arrival must be equal to the number of samples read from the memory for that row for each horizontal row. If the number of written and read samples were not the same, the image of the main channel would be slanted as a result of the pointers being read and written row by row. This requirement is due to the fact that the in-service memory memories arranged in the main channel are reset once per field. First, the write pointer is reset by the vertical sync pulse of the main signal, and then the read pointer is reset one row later.

For read and write indicators, a different number of clock cycles may be required to move through the same number of locations, due to the fact that both image data is compressed and expanded. Make it count. of recorded data samples is always equal to the number. The read data samples, regardless of the mode, use three register values and two control signals to generate read and write enable signals in operator memories in the order of arrival for the Y and UV main signal components. The two values of the WR-BEG-MN and RD BEG MN registers created by the widescreen microprocessor 340 determine the horizontal line position at which to read and write, in conjunction with the H COUNT value of the number of pixels in the horizontal direction. The H COUNT value is a 10-bit read value used to determine the position of the pixel during the line period. The contents of the counter are cleared by a SOL start signal. The SOL signal is a pulse of one clock pulse and sets the horizontal counter H COUNT to zero at the beginning of each line. The SOL pulse is nominally aligned with the face of the horizontal synchronization component.

The third value of the LENGTH register is used to envy the upper eight bits of a 10-bit counter to determine the number of data samples that were actually written to or read by the operator in the order of arrival. The register value bit is inverted and the least two valid bits are brought to logical one, resulting in a _LENGTH-1 value. The symbol A preceding the signal designation indicates logical inversion. Thus, if the counter is overfilled, the transferred transmission is brought to logical one and the required number of samples is written or read. The actual number of written or loaded pixel samples is LENGTH x 4 because the register is loaded into the top eight bits of the counter. The effect of the clock keying is calculated by the keying of the counter access signal. In this way, the enable signal for the counter can also be used

- 61 as an enabling signal for operator memory in the order of arrival, ensuring that the number of written or read samples is always LENGTH x 4, regardless of the mode.

Fig. 11 (d) depicts one of the three identical circuits used to generate write and read release signals for operator memories in the order of arrival for storing the Y and UV components, and these release signals are designated WR EN FIFO Y (case 1), WR EN FIFO UV (case 2), RDENFIFO Y and RDENFIFO UV. When stretching, the RDENFIFOY and RD EN FIFOY UV signals may be the same and designated as RD EN FIFOY UV (case 3). Circuit 1100 is first explained for case 1. Circuit 1100 compares the WR BEG MN signal with the upper eight bits of the H COUNT value in the comparator 1102. The H COUNT value is a ten bit count value used to determine the pixel position in the row period. The counter is cleared by a SOL start signal. The SOL signal is a one-hour pulse and sets the horizontal counter H_COUNT at the beginning of each line to zero. The SOL pulse is nominally aligned with the horizontal synchronization component.

The output of the comparator 1102 is delayed by the circuit 1118 and compared in the NAND type 1.104 with an inverted but otherwise non-delayed version of itself. The NAND gate output 1104, which is an active LO signal of one clock cycle width, is a misleading input LDn to the 10-bit counter 1106. The LDn input is also used to feed the leading edge of the system clock signal to the 10-bit counter 1106. The LENGTH signal bits are inverted The LENGTH value is used to load the upper eight bits of the 10-bit counter to determine the number of data samples that were actually written to the operator memory in the arrival order. The output of the inverter array 1110 is routed to the highest bits of the counter 1.106 by the LOAD input. The least two valid bits are put into a logical upper level state. The effective value is LENGTH-1. In order to set aspect -1 of the LENGTH-1 value, counter 1106 is stopped by the transferring transmission signal RCO, which occurs one clock cycle before the length counter 1106 reaches zero. The clock keying information is then added to the converted RCO transmission signal in the NOR gate 1111. The same enable signal is inverted by the gate 1116 and used as the enable signal for the operator memory in the arrival order. This memory and counter 1116 are thus accessed in exactly the same way, thereby ensuring the correct number of samples to be written. In case 2, the signal WR BEG MU is also compared with H COUNT. However, the CGUV WR signal is used to generate the output signal WR EN FIFO UV. In case 3, the RD BEG MN signal is compared to the H COUNT and the CGY RD signal is used to produce the output signal RD ENFIFO Y UV.

The processing of the colorant components for the image of the main channel may be accomplished by several variations of the arrangement according to the invention. One alternative topology is the arrangement shown in FIG. 8 and 11 (a) and explained in connection with FIG. 52-55. Another topology for processing the chrominance components for the main channel image is shown in FIG. 13 and explained with reference to FIG. 51. The UV signal path 530 is shown in FIG. 13 is shown in block diagram form. Lane 530 is very similar to the optional luminance data topology in the main signal path 304 shown in FIG. 8 and 11 (a). The most important difference is the use of the adaptive delay circuit 540 by the hundred interpolator 337. The multiplexed circuits 534, 536 and 538 in the order of arrival precede the adaptive delay circuit 540, or the path in which the adaptive delay circuit 540 is intersected. 532 direction control. The output of multiplexing circuit 538 is divided into signals U OUT and V OUT by the demultiplexing circuit 35 3.

If the interpolation system performs image compression, data samples must be erased before being written to memory 358. This is a problem for multiplexed I / O data. If the Y data stream were phased out with the same clock click pulses as the Y data stream, the UV components would not be staggered in the order of U, V, U, V ... etc. For example, if only a sample U was discarded before being written to memory 358, the sequence would be U, V, U, V, V, U, V, and so on. Therefore, a second clock clocking signal is required. This signal is called CGUV (or CGUV if it is logically inverted). This signal is used only during compression, has only half the frequency of CGY pulses and always discards a pair of UV samples. The results of compression in the ratio 8/5 are shown in FIG. 51 (a) and 51 (b).

In this example, it is apparent how the CG write signals of Y (_CGY) and UV (CGUV) differ from each other. If the CGY and CGUV signals are in logical one, the samples are discarded. The CGUV signal always begins with sample U and ends with sample V. The UV pair is thus discarded in common, avoiding situations where the embossed component V of one pair would be common with the component U of the next pair. A comparison of how the UV and Y data is read from the respective handy memories 358 and 356 in the arrival order is shown in FIG. 51 (a) and 51 (b). Obviously, the UV data is skewed by up to one such cycle relative to the Y data. This is due to the fact that U / 'V indication data is not stored in the data stream of the handled memory in the arrival order. The skew of the UV data slightly worsens the color component. However, this deterioration is never worse than the 4: 1: 1 multi-color system that is commonly used in high end television systems. The effective Nyquist frequency of the UV components is due to the discarding of the pairs, which is still sufficient for the wide color sources. The result is

UV reduced to 2 MHz, fragrance components I maintain high quality color components of the signal even during UV pairing.

Compressing the image data requires that the clock-cached write-in signals in the in-service memory 356 and 358 are different for the Y and UV signal paths. In principle, samples U and V must be discarded in pairs, since once the sample is ejected, the status information of that sample (whether it was a U or V sample) is lost. For example, if the ninth bit was added to the memory 358 to transmit the UV state information, the samples would also be discarded as well as the individual samples U and V. When reading the data from the memory 358, the UV components would then be correctly interpreted. However, since this thirty information is not used, the result is. For example, the UV data must be discarded in pairs, and subsequent resolution after reading the contents of the memory 358 can be very simple.

Sorting the punched UV pairs requires only a one-bit counter. This counter is synchronously set to a U (zero) state, for a clock cycle that begins to read the memory 358 with the operator in the arrival order. This one-bit counter is accessed by the RDEN MN signal, which controls the reading of the main memories 356 ^and 358, respectively, in the order of arrival. In the press mode, the RD EN MN signal is continuously in logic 1 state from start to finish, in each horizontal line. The resulting UVSEL OUT signal is an alternating U / V component indicator that drives the deinult ipl external selector 353. Timto in the method, the UV samples are successfully sorted after reading from the memory 3581, and even if the sync information of the UV components could not be stored in the memory 358 for later retrieval.

In performing the stretching of the image, writing to the operator memory 356 and 358 is uninterrupted in the order of arrival from start to finish. Readings with these memories are delayed and samples are retained (repeated) as they are read from the memory. This retention or repetition of the samples is done using the read-through clock information that is part of the RD EN MN signal and its complement to RD EN MN.

Here it is necessary to point out an important difference compared to pressing. The status of the UV sample is known when it is read from the operator's memory 358 in the arrival order. The UV data is written to the memory 358 with constant alternation of items U, V, U, V. .atd. When the data is read from memory 358 and then interrupted by delays, a one-bit counter is also suspended, which generates a UVSEL OUT signal to account for the fact that the data from the memory has been retained. This ensures correct triading by the demultiplexing circuit 353.

The one-bit counter is paused at the right time because the RD EN MN signal is input to its opening. This ensures that when the memory 358 is stopped, the UV SEL OUT signal is also suspended. Expansion does not require that the Y and UV read permission signals for the on-arrival memories 356 and 358 are separate, as the clock read signal for bb data

The UV, which is the CGUV signal, is now the same as the read-read clock signal for the Y data, the CGY signal. Expansion is easier than compression. Moreover, the Nyquist frequency of the chrominance component does not deteriorate when stretched and the 2: 1: 1 signal quality is fully maintained.

The described topology of the multiplexed color component has a number of advantages. The method is efficient and ideally matched to operations in conjunction with a broadband luminance raster mapping system. Circuit complexity is minimized while maintaining a high level of color signal quality. These advantages are partly due to the following improvements. The UV pairs are discarded at the input of the UV component memory 358. This eliminates the need to keep the clock-wise information in this memory, which would require the operator memory in the arrival order to be 1 bit wider than the true accuracy of the UV data. The UV component interpolator, which would work analogously to the interpolator 337, is replaced by a delay adaptation circuit. This eliminates the very complex mathematical function. In addition, since the gate array is formed in an integrated circuit, approximately 2000 gates are saved. And the ultimate quality of the UV signal is not reduced even in the worst case under the 4: 1: 1 color channel arrangement, which remains at a 2: 1 ratio

In a further embodiment of the invention shown in FIGS. 8 and 11 (a), a delay adaptation circuit is not required. Instead, the operator memory in the order of arrival is controlled in a way that achieves the same results. Fig. 52 (a) and 52 (b) illustrate portions of the brightness and color paths in the gate array 300. FIG. 52 (a) represents an optional topology corresponding to the image compression {at which it is before the memory (Y, U, V) and after the spread.

356, an interpolator 337 is included. In the color path, FIG. 52 (b only the operator's memory 358 is shown in order of arrival.

Fig. 53 (a) to 53 (1) show an example of image compression. For the purposes of this example, it is assumed that the luminance and color components were correctly adjusted before the delayed conversion and that the interpolator has a 5 hour cycle delay, although the actual interpolator delay is 20 hours cycle and the luminance and color signal are not compared in time. The UV MUK line selector for the analog switch or demultiplexer 344 is an 8 MHz signal. derived by dividing the clock impulses of the system by two. As shown in FIG. 53 (a), at the beginning of a row having a one-hour pulse width, the i-pulse SOL sets the UV MUX signal at the beginning of each horizontal image line synchronously to zero, as shown in FIG. 53 (b). The UV MUX signal then flips to the horizontal with each hour cycle. Since the line length represents an even number of clock cycles, the state of the once triggered UV MUX signal will continue to interrupt without any interruption: 1 counts between levels 0 and 1. The UV and Y data flows from analogue number converters 346 and 342 are shifted because each of the analogue converters has a delay of one clock cycle. In order to compensate for this data shift, similar CGY clock keying information shown in FIG. 53 (e) and the CGUV shown in FIG. 53 (f), from the interpolation control circuit 349 (see FIG. 9). The UV FIFO IN data of the UV component shown in FIG. 53 (d) and stored in the operator's memory 358 in the order of arrival, ahead of the Y-FIFO IN data of the Y component shown in FIG. 53 (c) because the luminance data is passed through the interpolator

- 68 337 and the color components are not interpolated. The reading of the UVFIFO data from the UV bed memory 358 is as shown in FIG. 53 (h), delayed by 4 hours cycles to read Y FIFO data from the Y-bed memory 356 shown in FIG. 53 (g), adapted to the above displacement. There is thus a delay of four hours between the leading edge of the readout signal RD EN MN UV for the UV component memory shown in FIG. 53 C j), and the leading edge of the read enable signal RD EN MN Y for the component Y memory shown in FIG. 53 (i). The resulting data streams Y and UV are shown in FIG. 53 (k) and 53 (1). The most unfavorable non-adaptation of the Y and UV components is 1 hour cycle, which is the same result that can be achieved by a more complex system, for example one in which the relative positions of the operator's memory in the order of arrival and delay adaptation circuit can be confused.

It should be noted that the reading from the memory 358 of the U.V components in the exemplary embodiment is delayed by 4 hour cycles, although the interpolator delay is 5 hour cycles. The most preferred setting for the number of hourly cycles of the UV component read delay is an even value that is no greater than the interpolator delay. Expressed in computer language C and designating the delay as DLY RD UV,

DLYRDUV = (int) ((int) INTERP DLY / 2) * 2, where INTERP_DLY is the interpolator delay expressed in the number of clock cycles.

In practice, the interpolator may have a delay of 20 clock cycles (INTERP DLY = 20) and the luminance and chrominance components are not adapted. The luminance and chrominance signals can be offset in time in many ways. The chrominance components are usually delayed beyond the luminance signal due to demodula.ee. The raster mapping system of the present invention has the advantage that any non-adaptation of the Y and UV components can be overcome by delaying the interpolator. If the image is compressed, the DLY RD UV delay in reading the 358 UV component memory can be set from 0 to 31 hours. Since the luminance signal interpolator 337 has an intrinsic delay of 20 clock cycles and each clock cycle has a length of approximately 62 nanoseconds, the raster mapping circuit described herein can correct the chrominance delay relative to the luminance signal up to 1.24 microseconds (62 nanoseconds x 20). In addition, the raster mapping system can perform luminance signal delay corrections relative to the chrominance component up to 682 nanoseconds (62 nanoseconds x [31-20]). This provides an extraordinarily high degree of flexibility for connecting external analog video circuits.

The same different delay as is performed by the interpolator in the luminance channel when the image is compressed can also be realized when the image is expanded. Fig. 54 (a) and 54 (b) illustrate portions of the luminance and chrominance signal paths in the gate array 300. FIG. 54 (a) represents an optional image stretching topology, wherein the interpolator 337 is aligned with the operator's memory 356 in the arrival order. The path of the UV component, containing the steam 358 with the operator in the order of arrival, remains unchanged. In the example of stretching the image shown in FIG. 55 (a) to 55 (1). it is assumed that the interpolator has new cycles. SOL signal

The UV MUX, the Y IN input of the luminance data stream to the memory 356, and the UV IN input of the chrominance data stream to the memory 358 are shown sequentially in FIG. 55 (a) to 55 (d). In order to correctly time-equalize the Y and UV data, delaying the 5th row may occur, a signal that the write (DLY WR Y) may be delayed to the component Y memory 356 or the read (DLY RDJJV) from the UV component 35 may be delayed. Delayed reading from the UV component memory 358 is permissible in this case because this pair does not require interpolation coefficients K and C. In the image compression mode, the write could not be delayed as this would tune the alignment of the coefficients K, C relative to the clock keying information and the luminance portion of the interpolation would be violated. The correct setting of the DLY WR Y value, which delays writing to the Y component memory by 4 hours cycles, is indicated between the leading edge of the WR EN MN UV write enable signal shown in FIG. 55 (f), and the leading edge of the write enable signal WR EN MN Y writing to the component Y memory shown in FIG. 55 (g). The clock keying signal CG and the output signal Y_FIFO are successively shown in FIG. 55 (i) and 55 (j). The resulting time alignment of the Y and UV components is illustrated by the relative positions of the Y OUT and UV OUT data streams as shown in FIG. 55 (k) and 55 (1).

The ability of the raster mapping system to compensate for external non-matching of luminance and chrominance components is equally great for both stretching and compressing the image. This is a very important function of the raster mapping system, since it eliminates the need to use a variable delay line at the luminance channel input to adjust the luminance and chrominance component. The choice of a particular topology may be based on a number of factors, and other circuits may also be considered.

The auxiliary signal interpolation takes place in the auxiliary signal path 306. The picture-in-picture circuit 301 controls a field-shaped image storage box for storing the 6-bit component Y and the component U, in the incoming image data at a ratio of 8: 1: 1, which is already a RAM image type 350. The image memory 350 stores two frames of image data in a plurality of memory locations. Each memory location holds eight bits. give. One 8-bit brightness pattern Y (sampled at 640fh) and two additional bits are stored in each 8-bit memory location. These two additional bits contain either the fast-switching FSW DAT data or a portion of the U or V sample (sampled at 80 µi). The FSW DAT values indicate which type of file was written to the RAM. Since two RAMs of data are stored in the RAM 350, and the cell 350.RAM is read during the display period. both fields are read during image decomposition. circuit

301 for creating from fields will determine from picture in picture which memory is loaded for display using fast switch data. The picture-in-picture circuitry 301 always reads a strip of the opposite type to that currently being written to overcome the image tearing problem. If the strip being read is of the opposite type to the strip currently being displayed, it will convert the even strip stored in the picture by erasing the top row. The image maintains the correct movement.

The timing and synchronization circuit 320 generates read, write, and enable signals necessary for operation of the memory memories 354, 356 and 358 in the order of arrival. Operator memories in the order of arrival for the main and auxiliary channels are made available for writing

As a result, the interleaving when loading the RAM 350 is that little tearing is;

data of those portions of each are required for a subsequent line of image that is shown. Data is written either from the main channel or from the auxiliary channel, but not both, which is necessary to combine data from each source into the same line or lines of the image. Memory 354

The 72-bit signal is written with the operator in the order of arrival, arranged in the auxiliary channel, is written synchronously with the auxiliary video signal, but is read synchronized with the main components of the main video signal into memory 356 and 358 synchronized with the main video signal and read from the memory. also synchronous with the main video signal. The frequency of switching between the main and auxiliary channels is a function of the selected special effect.

The creation of various special effects, such as cropped images placed side by side, is accomplished by controlling the read and write enable signals for the line memories with the operator in the order of arrival. The procedure for this display format is shown in FIG. 7 and 8. For cropped images displayed side by side, the write enable control signal WR EN AX is for the memory 354 with a 2048 x 8 arrival order, arranged in an auxiliary channel approximately active after (1/2) x (5/12) ) = 5/12 or 41% of the active image line period (after acceleration) or 67% of the sub-channel active line period (before acceleration), as shown in FIG. 7. This corresponds to a crop of 33% (approximately 67% of the active image) of the 5/6 interpolation signal extension. In the main video signal shown at the top of FIG. 8, the WR ENMNY write enable control signal for memories 3 ^ 56 and 358 is operative in the order of arrival of 910 x 8 after (1/2) x (4/3) = 0.67 or 67% of the active image line period . This corresponds to a crop in the range of approximately 33% and a 4/3 compression ratio performed in the main channel image by the operator-handled memory in the order of 910 x 8.

In each of the attendant memories in the arrival order, the data is stored in the buffering method for loading at a particular point in time. The active time zone in which data from each memory can be read is determined by the display format selected. In the illustrated cropped image mode arranged side by side, the main channel image is displayed in the left half screen and the auxiliary channel image is displayed in the right half screen. As shown, the signals of the individual arbitrary image portions have different waveforms for the main and auxiliary channels. The RD EN MN read enable control signal in the 910 x 8 arrival order, arranged in the main channel, is active for 50% of the active image row period, beginning at the beginning of the active image immediately after the rear delay of the video signal. The RD EN AX readout control enable signal for the auxiliary channel is active for an additional 50% of the active image line period, beginning with the rear edge of the RD EN MN signal and ending with the front delay of the main channel video signal. The write enable control signals are synchronous with the respective input memory of the attendant memory in the order of arrival (main and auxiliary), while the read enable control signals are synchronous with the main channel video signal.

The display format shown in FIG. 1 (d) is particularly needed since it allows the creation of two tangential full images arranged side by side. This display is particularly effective and suitable for a widescreen screen format, such as 16x9. Most NTSC signals are in 4x3 format, which corresponds to a 12 9 ratio. The same 16x9 screen can accommodate two images transmitted in the NTSC format. NTSC standard and in 4x3 formats, either with 33% cropping or 33% squeezing and introducing distortion ratio, depending on the user's preference, any ratio can be set cropping images to distort the grape ratio in the range of 0 to 33%. The two images arranged side by side can be formed, for example, as a squeeze of 16.7% and a simultaneous crop of 16.7%.

The activity may be described by means of generally expressed pores of acceleration and trimming. The imaging means may be considered with a ratio of the width and height of the display format expressed as M: N, the source of the first video signal may then have a ratio of the side of the display format A: B and the source of the second video signal is considered with the side of the display format. The first video signal may be accelerated by the coefficient C in the first range, the approximate and selectable cropping in the range from approximately 0 to the video signal may be vood 1 to (M / N - A / Bj, the coefficient in the second [(M / N - A second blend accelerated by a coefficient in the third range, approximately from 1 to (M / N - C / D), and optionally cropped by a coefficient in the fourth range, approximately from 0 to [(M / N - C / D) D) -1].

The horizontal display time for a 16x9 format screen is the same as a 4x3 screen format because the nominal line length is 62.5 microseconds in both cases. Therefore, the video signal transmitted in the NTSC standard must be 4/3 to be maintained without distortion. The coefficient is accelerated by the coefficient of the right ratio

4/3 is calculated as the ratio of two display formats: 4/3 = (16/9) / (4/3)

Variable interpolators are used to accelerate the video signals in accordance with embodiments of the present invention. In the past, operator-operated memories having different clock frequencies on inputs and outputs were used to perform similar functions. If, for comparison, two 4x3 NTSC signals are displayed on a single 4x3 screen, each of the images (or combinations thereof) must be distorted or cut by 50%. There is no need for acceleration comparable to that required for wide-angle imaging.

A field image synchronization system for avoiding collision of read and write pointers and for maintaining interleaving integrity is explained in more detail with reference to FIG. 28 to 36. The image-in-picture processor operates in such a way that the image auxiliary data is sampled by clock pulses at 640f _H coupled to the horizontal synchronization component of the incoming auxiliary video signal. This function allows the orthogonal sampled data to be stored in a RAM image 350. The data from the RAM memory must be read at the same frequency of 640 f, i. Due to the general asynchronous nature of the main and auxiliary video signal sources, RAM data cannot be displayed orthogonally without being modified. To facilitate synchronization of the slave signal with the main signal, a row memory with independent read / write clocks is arranged in the slave path after the output of the video RAM 350.

As shown in more detail in FIG. 28, the RAM image output 350 is the input of the first of the two 4-bit inverters 352A and 352B. The VRAM OUT is arranged in four-bit data blocks. Four-bit inverters are used to combine the auxiliary signal into eight-bit data blocks. The inverters also reduce the clock pulse rate of the data from 1280 f μ to 640 fn. The eight-bit data blocks are written to the operator's memory 354 in the arrival order at the same frequency of 640 f · ,; clock pulses, which is used to sample the auxiliary image data when it is stored in the 350 RAM image memory. The size of the operator's memory 354 in the arrival order is 204Θ x8.

The reading of the 8-bit data blocks from the memory 354 is performed by a display clock signal having a frequency of 1024 fk, which is coupled to a horizontal synchronization component of the main video signal. A basic configuration that utilizes multiple line memory with independent clock read / write inputs allows orthogonal display of data that has been orthogonally sampled. The eight-bit data blocks in the multiplexing circuit 355 are divided into six-bit luminance samples and split samples. The data samples can then be interpolated as required for the desired aspect ratio in the display format and written as the output of the image data.

Since the reading and writing of data from the operator's memory in the order of arrival, arranged in the auxiliary channel, are asynchronous, there is a variety of read / write pointer conflicts. These collisions can occur when old data is read from the drive memory, rather than new data can be written to that memory. Pointer collisions can also occur when memory is overwritten with new drive data before old data could be read from it. It is therefore necessary to maintain the integrity of interleaving.

First of all, a sufficiently large memory must be selected to avoid collisions between the read and write pointers in the operator's memory in the order of arrival arranged in the auxiliary channel. When displaying a normal aspect ratio image, cropped by 33%, the operator's auxiliary memory in the order of 2048x8 is capable of storing 5.9 lines of image data, calculated as follows:

N = (2/3) x (0.82) x (640) = 350 L = 2048/350 = 5.9 where N is the number of rows, taking into account the 82% active row period, and L is the length of each row. It has been found that it is not advisable to use higher advance speeds than 2 rows per strip. Thus, a five-row operator with an order of arrival, sampled according to the invention for the auxiliary channel, may be sufficient to avoid collisions with the read / write indicators.

The use of operator memory in the order of arrival in the auxiliary channel may be illustrated as shown in FIG. 29. FIG. 30 is a block diagram of a simplified circuit formed by Type D flip-flops for generating line delays (Z-i) and reset pulses for reading in an access memory 354 arranged in an auxiliary signal path. At the beginning of a new main signal field, the write pointer is set to the starting point of the operator memory in the arrival order. This reset pulse, designated WRRST AX, is a combination of the V SYNC MN signal sampled by H SYNC AX. In other words, the pulse WR RSTAX occurs at the first horizontal synchronization pulse of the auxiliary video signal, which is provided after the vertical synchronization pulse of the main signal. Two horizontal rows of the main signal later set the read pointer to the starting point of the operator's memory 354 in the arrival order. The corresponding reset pulse is designated RD RST AX and occurs at a third horizontal sync pulse of the main video signal which is provided after a vertical sync pulse of the main signal or, in other words, at the second horizontal sync pulse of the main signal.

that occurs after a WR RST AX pulse.

Since the main and auxiliary video signals are asynchronous, there is some ambiguity in where the write pointer is exactly when the read pointer is reset to zero. It is known that the write pointer overrides the read pointer by at least two rows. However, if the horizontal synchronization signal of the auxiliary channel is higher than the frequency of the horizontal synchronization signal of the main channel, then the read indicator will have a timing out of the two line index shown. Consequently, the collision of the indicators is avoided for all signals with an advance rate of less than 2 rows per pole. The attendant memory 354, corresponding to the auxiliary channel, is divided into five row sections by means of suitable timed read / write reset signals.

In this scheme, read / write pointers are initiated at the beginning of each of the displayed fields so that they are separated from each other by at least two rows.

If the operator's memory in the order of arrival were not five lines long, the system would sacrifice the memory distance from the write pointer to the read pointer. This is the case with different compression modes, for example by '16%:

N = (5/6) x (0.82) X 640 = 437 L = 2048 (5 x 437) = 4.7

In these cases, the length of the operator's memory in the order of arrival is less than five lines. When pressed by 16%, the actual memory length is 4.7 lines. A factor of 0.8 in the equation for N when compressed by 33% is a functional limitation of the CPIP chip.

Since the read and write reset signals of the attendant memory are separated by at least two rows of the active image, the sacrifice is always performed at the cost of allowing the read pointer to catch up with the write pointer. In addition, only 60% of the image line is considered active because the image-in-picture processor is not able to store it in the image memory. 350 RAM type more than 512 image samples. In practice, however, a good active image line is still ensured. In these cases, the advance rate is sacrificed for more visible image content. In addition, the auxiliary image is more distorted. In the worst case, it may be in between. the source of the main and auxiliary video signal is tolerated in one line per line. This is still more than necessary for most video sources, and the advance rate tolerance is sacrificed in those additional modes that are expected to be used at least.

Another problem of the asynchronous reading and writing of the handled memory in the arrival order is to maintain the interleaving integrity of the auxiliary channel image. Since the screen is coupled to the main video channel, it is of the type currently displayed in the field, the upper or lower field. determined by the main signal. The type of field that is stored in the RAM image 350 and is ready to be read at the beginning of the main channel field may or may not be the same as the type of field image being displayed. Thus, it may be necessary to change the type of auxiliary field stored in the RAM image memory 350 in order to adapt it to the main channel image.

The picture-in-picture processor 320 and the gate array 300 quantize 262.5 lines of NTSC signal bands to 263 lines of upper bands (sometimes called even bands). This is due to the fact that the vertical synchronization component is sampled by the pulses representing the horizontal syn80 synchronization component, as illustrated by the diagram in FIG. 31. The upper and lower field indicators are 1 for the upper fields and 0 for the lower fields. The upper fields contain odd rows 1 to 263. The lower fields contain even rows 2 to 262. In FIG. 32 is a first U / L MAIN SIGNAL pole display indicator of a main picture channel frame type. The HSYNC AX signal represents the horizontal synchronization components for each row of the auxiliary channel.

The U / L indicator (A) of the pollen type represents the pollen type stored in the 350 RAM image memory when each auxiliary channel line was written normally. The term normally used herein means that odd lines 1 to 263 are remembered. 350 RAM write! when the top field is being received and decoded. The U / L indicator (B) of the dome type represents the dome type stored in the RAM image 350 if it is not written to the memory during the dense hormone uptake of the first line of the dome. Instead, the first line is in fact appended to the last line (number 262) of the bottom line. This effectively efficiently inverts the image type, since row 2 will be the first row shown and row 3 will be the second row displayed. The received upper field now becomes the lower field and vice versa. The U / L indicator (C) of the dome type represents the dome type stored in the RAM image memory 350 when the last line of the upper dome is added to the memory 350 while receiving the lower dome. This is again an effective reverse type of dowser, as row 263 will be the first row shown and row 1 will be the second row shown.

Adding and subtracting rows in modes B and C does not deteriorate the image of the auxiliary channel, as these rows appear during vertical reverse run or overlap. The order of the displayed rows is shown in FIG. 34, wherein the solid lines represent the lines of the upper pollinator and the dotted lines of the line of the lower pollinator.

As the master and slave channel signals are preceded, the U / L MAIN SIGNAL indicator will be shifted to the left or right relative to the U / L indicators (A, B, C) of the type of auxiliary channel. In the position shown in the diagram, the data should be written to the image RAM 350 using mode A because the decision edge is in area A. Mode A is useful because when the PIP receives a vertical synchronization component, it writes to the image the same RAM type of memory as will be required by the display unit to read from the 350 RAM image triggered by the V SYNC MN signal (vertical main channel synchronization component). Since the signals are preceded, the mode will vary according to their relative positions. The current modes are shown graphically at the top of FIG. 32 and shown in the table of FIG. 33. There is an overlap between modes B and C, since for most of the period for which mode B is in effect, mode C is also applicable and vice versa. This applies to all 262 rows except two rows. If both modes B and C are valid, either of them can be used.

A block diagram of the interleaving integrity circuit 700 of the present invention is shown in FIG. 36. The output signals of circuit 700 are reset write control reads and reads for video RAM 350, for the on-order access memory 354 arranged in the auxiliary signal path, and for the on-order access memory 356 arranged in the main signal path, as shown. FIG. 28. The main image signal pole type is determined by the pair of VSYNC MN and HSYNCMN signals. Type of pimples. the auxiliary video signal is determined by the corresponding pair of VSYNC AX and HSYNCAX signals. Each pair of signals has a predetermined phase relationship that is set in the gate array 300. This relationship is shown in FIGS. 35 (a) to 35 (c) relating to both signal pairs. In all cases, the HSYNC signal has a square waveform whose leading edges correspond to the beginning of the horizontal line of the signal in question. In all cases, the VSYNC signal has only one leading edge per line that corresponds to the beginning of the vertical line of the signal. The relationship between the leading edges of the respective signal pairs is controlled by the circuitry 700 to determine the steps that are necessary (if at all) to accommodate the types of auxiliary signal and main signal. To avoid ambiguity, the leading edges of the main signal pair are never narrower than 1/8 of the horizontal line period. The leading edges of the auxiliary pair of signals are never narrower than 1/10 of the horizontal line period. Thus, there is a mutual temporal instability of the leading edges. This relationship is provided by the gate field timing circuits.

The main pair of VSYNC_MN and HSYNC MN signals are inputs of the first field type 702 circuitry, which includes two D-type flip-flops. In one case, the HSYNC-MN signal is sampled by the VSYNC_MN signal, which means that VSYNC MN is the clock input. The output of this flip-flop is an UL MN indicator of the upper main signal, which may be for the upper and lower types for the logical one and the logic zero state for the lower, but this assignment is arbitrary. In the second. in this case, the VSYNC MN signal is sampled by the HSYNCMN signal, in the same manner.

As in flip-flop 852 explained in connection with FIG. 30. The relevant output V _ie circuit 702 is a vertical output, synchronized with horizontal outlet.

rim VSYNC AX, giving clock impulses. is the UL AX indicator

The auxiliary pair of VSYNC_AX and HSYC AX signals are inputs of the second field type circuitry 710, which also includes two D-type flip-flops. In one case, the HSYNC AX signal is sampled to indicate that VSYNC AX is the output of this flip-flop. an auxiliary signal that can have a logical one state for the upper pole type and a logic zero state for the lower pole type, but this assignment is arbitrary. In the second case, the VSYNC AX signal is sampled by the HSYNC signal ΑΧ, in the same manner as in the flip-flop 852 explained in connection with FIG. 30. The respective output Vu of circuit 710 is a vertical output synchronized with a horizontal output.

The determination of the field type is shown in FIG. 35 (a) to 35 (c). If the edge edge strike occurs in the first half of the horizontal row period, as in FIG. 35 (b), is a downy mildew. If the edge edge incidence occurs in the second half of the horizontal row period, as in Fig. 36 (c), the field edge is of the upper type.

Output V _; also for the main signal and the HSYNC MN signal, the inputs of the delay circuits 704, 706 and 708 create a delay of horizontal line periods to ensure the correct phase relationship of the output signals WR RST FIFO MN, and RD RST FIFO AX. Delayed by the D-type flip-flops shown in FIG. 30th

RD RST FIFO MN, which can be performed similar to the two between the write and read pointers, creates a delay of two to three periods of horizontal lines.

The UL MN of the upper and lower poles corresponds to the U / L MAIN SIGNAL signal shown at the top of FIG. 32 and is one input of comparator 714 designated UL SEL. Other inputs of the comparator 714 are the outputs of the UL AX signal generator 712. The test generator 712 has a UL signal input UL AX, which is the output of the circuit 710. Another input of the test generator 712 is the HSYNC ΑΧ signal as a clock signal. The outputs of the test generator 712 are the U / L (A), U / L (B) and U / L (C) signals shown at the bottom of FIG. 36 and corresponding to the three possible modes A, B and C. Each of the U / L (A), U / Lib (B) and U / L (C) signals is compared to UL MN, which is Also shown in FIG. 32. If the UL MN agrees with U / L (A), the pollen types are also matched and there is no need to maintain interleaving integrity. If UL MN agrees with U / L (B), the types of polls are not matched. To maintain the integrity of the interleaving, it is necessary to delay the writing of the upper pole by one line. If UL MN agrees with U / L (C), the types of polls are also not matched. In order to maintain the interleaving integrity, it is necessary to introduce the entry of the bottom line by one line in advance.

The result of this comparison is the SEL input of the selector circuit 718 designated RST AX SEL. The other inputs of this circuit are three vertical synchronization signals RST A, RST B and RST C generated by a generator 716 designated RST AX GEN. The three synchronization signals have different beats from each other to take corrective action to maintain interleaving integrity according to the output of the comparator 714. The delay circuit 722 restores synchronization of the selected raster mapping mapping used to process the digital signals with the auxiliary video output signal, thereby producing a WR RST VRAM signal. AX. The delay circuit 720 performs a similar function and generates RD RST VRAM AX and WT RST FIFO AX signals. As is apparent from FIG. 32, modes B and C overlap most of the time. In fact, only two of every 525 comparisons will require only one of the B or C modes and not any of them. The comparator 714 may be arranged such that, in both modes, mode C is preferred to mode B. This choice may be arbitrary or may be due to other reasons arising from the circuit arrangement.

The circuit 111 shown in FIG. 4 (b) is a modification of circuit 11 of FIG. 4 (a), in which a liquid crystal display system is arranged. Procedures for the signals detailed above may also be suitable for liquid crystal display systems. The pixel map generated by the matrix address generator 113 is based on the digital multiplexed output Y MX, U MX and V MX of the gate array 300. The matrix address generator 113 performs excitation of the liquid crystal display means 115.

Data reduction or compression and data recovery or stretching may be performed by alternative methods according to various widescreen television arrangements according to the invention. In one alternative, the coded signal is read to the auxiliary signal by the resolution control circuit 370, which is subtracted again from the resolution control circuit 357. The resolution control circuit 370 may also be regarded as a data reduction circuit, and the resolution control circuit 357 may be considered a data recovery circuit. Thus, in this method of resolution control, the on-bit signal is encoded by om bit bits, neglecting the least valid bit. . One bit bit sequence. 01010101, etc. to the n-bit lowest validity signal.

n-1 bit signal. A n-1 802 signal and one input for adding coded signals and a corresponding one-bit circuit for reading the coded signals are shown in FIG. 39 and FIG. The two-bit circuit for adding the coded signals and the corresponding two-bit circuit for reading the coded signals are shown in FIG. 4.1 and FIG. 42nd

As shown in FIG. 39 and 40, the summation circuit 372 combines the n-bit signal with a one-bit code. The preferred one-bit sequence is discarded after adding the code sequence to circuit 374. The coded signal of n-1 bits is then processed by the PIP 320, inverters 352A and 352B; memory 354 with attendance in the order of arrival. The subsequent output of the circuit 306B after decoding the picture in the picture is processed by the coded data recovery circuit 357 in bits to the summation circuit of the burst 804. The signal at the second burst 804 masks the lowest valid bit of the encoded signal. The output of the gate 804 is provided directly to the input of the non-equivalence circuit 808 and delayed by the circuit 806 by one clock pulse or one pixel, and then fed to the second input of the non-equivalence circuit 808. The output of the non-sequentiality circuit 808 is one input of the product gate 810 and the simultaneous input of the Y component interpolator 359, which input constitutes the new lowest valid bit of the decoded signal. The second input of the product gate 810 is a signal of the same code sequence and the same phase as the coded signal to the summing point 372. The output of the product gate 810 is subtracted the summing circuit input 802. The summing circuit output 802 is combined with an auxiliary bit. This creates an n-bit decoded signal as input to Y interpolator 359.

The two-bit coding circuit 370 shown in FIG. 41, includes a summation circuit 376 that combines an n-bit signal with a two-bit coding sequence. According to this arrangement according to the invention, the coding signal can be defined by any repeating sequence of numbers 0, 1, 2, 3, which are in this sequence in any order. This definition includes the following sequences in Table 1.

Table 1 0123 1023 2013 3012 0132 1032 2031 3021 0213 1230 2103 3120 0231 1203 2130 3102 0312 1302 2301 3201 0321 1320 2310 3210 coding sequence,

image forming in memory 354 with operator advantageous is 02130213, etc. as shown in FIG. 41. The N-bit signal that is outputted by the summation circuit J376 has two bits with the lowest validity trimmed by circuit 378. The encoded n-2 bit signal is then processed by the razor processor 320, inverters 352Ά and 352B, respectively, and the circuit 306B picture-in-picture decoding.

The quarter frequency component is usually less preferred than the half frequency component, although the quarter frequency component has half the amplitude compared to the half frequency component. Therefore, the decoding scheme can only be selected to suppress a quarter frequency component. The fixed signal path of the decoding circuit is designed to delay and adapt the amplitudes. The path of the second signal comprises an inverse bandpass filter combined with a limiter. The inverse bandpass filter suppresses the frequency in the middle of the passband when added to the delayed and amplitude signals caused by the original signal. The limiter ensures that only amplitudes of coded size are suppressed. This decoding arrangement does not affect the signal component having a half frequency compared to the sampling frequency. The half-frequency signal component has a sufficiently low amplitude and a sufficiently high frequency to have a sufficiently low visibility and thus avoid problems.

In FIG. 42, such a decoding circuit 306D 'is shown. The on-2 bit signal, which is output from the picture-in-picture decoding circuit 306B, is the input of the delay circuit 822, which generates a delay of two clock pulses or two pixels, to the second delay circuit 814 and to the summing circuit 812. is a subtraction input of the summation circuit 812 whose output is an on-1 bit signal. The encoded n-1 bit signal is an input to the limiting circuit 81-6. In this case, the output values of the limiting circuit 816 are limited by the interval (-1.0, 1), i.e. the absolute value of one. The two-bit output signal of the limiting circuit 816 is applied to the input of the delay circuit 818 to generate a delay of two clock pulses or two pixels and is simultaneously a subtraction input of the summation circuit 820. The delay circuit 818 and summation circuit 820 form a band-pass filter. wherein the frequency is a quarter of the sampling frequency. A two-bit signal is a binary complementary signal. The output of the summation circuit 82 is a three-bit signal that is a subtraction input of the summation circuit

826. The output signal of the n-2 bits of the delay circuit 822 is the input of the multiplier 824. The output of the multiplier 824 is the n-bit signal whose two bits with the lowest validity are equal to zero. By summing in circuit 826, these bits are assigned values, possibly some corrections. The output of the summation circuit 826 is a partially decoded n-bit signal that is an input to the inter-shifted shift sequence of the blank Y-pad 359.

The resolution or, better to say, the quality of the decoded video signal may, under certain circumstances, be improved by the temporal offset of the coding sequence. This sequence, whether single-bit or double-bit, repeats continuously in a given row, but is phase shifted on different rows. A variety of timeshift schemes can be generated. In order to hide the display errors resulting from the actual coding process, the two shown in FIG. 43. Mutual of one and two pixels are those in which all rows of a single pole have the same phase and all rows of the following pole are offset by one or two pixels relative to the first pole. The relative displacements of the frames transmitted by the two-bit coded signals are most effective in still images. In live images, a certain row structure may be visible where flat areas move. One pixel offset is particularly advantageous for two-bit codes if the signal is decoded, but for a signal that is not decoded, a two pixel offset is currently preferred. Whether or not a signal is to be decoded depends on the display format.

An alternative to the data reduction coding is to compress the pairs of pixels, which is explained with reference to FIG. 44. In the upper part of FIG. 44 shows a strip containing lines 1, 2, the elements of each line being indicated by a letter. Each pixel indicated by the letter P will be retained and each pixel marked by the letter R will be replaced. Permanent and replaced elements are moved one line away from the row. In other words, the second, fourth, sixth, etc. are exchanged in odd-numbered counters. figurative element. In even-numbered counselors, the image elements that are on odd places are exchanged. Two basic alternatives consist in replacing each replacement element with a one-bit or two-bit code. The bits for the codes are taken from a series of bits that are available to define persistent pixels. This number of bits is limited by the memory capacity of the image processor. In this case, the CPIP type chip and the RAM image pair 350 represent a limitation of an average of 4 bits per pixel. If each swapped pixel is replaced with a single bit code, then 7 bits are available for each persistent pixel. Similarly, if each exchanged pixel is replaced by a two-bit code, then 6 bits are available to describe each persistent element. In both cases, each pair of consecutive pixels (one permanent and one replaced) requires a total of 8 bits. Thus, a total of eight bits per pair represents an average of only four bits per pixel. Data reduction is in the range of 6: 4 to 7: 4. The sequence with the elements to be exchanged is illustrated by the portion of the field that contains three consecutive lines: n-1, n, n + 1. The pixels to be replaced are designated R1, R2, R3, R4 and R5. The elements that will be preserved are labeled A, B, C and D.

According to the one-bit code scheme, the pixel to be exchanged is replaced by zero if it is its etc. The value approximates the pixel above it and the diameter of the pixels which are on either side of it. In the example shown in FIG. 44, the one-bit replacement code for pixel R3 will be zero if the value of pixel R3 is closer to the diameter value of elements B and C than to the pixel value A. Otherwise, the one-bit replacement code will be 1. pixels B and C if the single bit code is zero. If the one-bit code is equal to one, then the pixel value R3 'will be the same as the pixel value A.

Also shown is the replacement and restore sequence for a 2-bit code. The 2-bit replacement code for pixel R3 is equal to zero. if the pixel value R3 is closest to the pixel value A. A two-bit replacement code is equal to one if the R3 value is closest to the average of A and B. The two-bit replacement code is equal to two if the R3 value is the closest to A and C. if the value R3 is closest to the average of B and C. The refresh sequence corresponds to the replacement sequence. If the two-bit code is zero, the pixel value R3 'is equal to A. If the two-bit code is equal to one, the pixel value R3' is equal to the average of A and B. If the two-bit code is equal, then the value of the pixel R3 'is equal to the average of the values of the pixels B and C.

The one-bit code is preferred insofar as the persistent pixels are written with one-bit resolution. The two-bit code is advantageous in that the replaced pixels are described in greater resolution. It is advantageous to perform the calculations with only two-row values, thereby minimizing the necessary capacity of the row memory. On the other hand, however, the inclusion of the D value in the calculations could produce a more accurate substitute sequence, but at the expense of the need for another row of image memory capacity. Compressing pairs of pixels may be particularly effective to provide good resolution in both horizontal and vertical directions, and in some cases better than coding and decoding. However, the resolution of diagonal transitions is generally not as good as coding and decoding.

According to the invention, a variety of data reduction and recovery schemes are available, including, for example, compressing pairs of pixels and encoding and decoding. In addition, different coding sequences of different bit counts and different methods of compressing pairs of different bit count pixels are available. A particular data reduction and recovery scheme may be selected by a widescreen microprocessor to achieve maximum resolution for each particular type of display format.

The widescreen processor also has the ability to control vertical deflection to perform vertical zoom. The widescreen processor topology is such that raster mapping (interpolation) functions are independent of each other and vertical zoom for both the auxiliary and the main channel.

Due to this stretched both horizontal and vertical, thus maintaining the main channel zoom at the correct ratio of grape. However, unless the auxiliary channel interpolator settings are changed, the picture in picture (small picture) will be zoomed vertically, but not (which controls the vertical topology may be deflected) the main channel horizontal. The auxiliary channel interpolator may therefore be adapted to perform greater horizontal stretching in order to maintain the correct aspect ratio of the small picture in the picture during vertical stretching.

A suitable example of this procedure is to display a 16 x 9 envelope format, as explained in more detail below. Briefly, main water 1: 1 mapping (without stretching is zoomed by 33 to avoid black

If set to 5/8 straight grid is set to i). Vertical direction% (i.e., stretched at a 4/3 ratio), by bands associated with the image from the envelope format source. The aspect ratio of the main channel image is correct. Rated auxiliary channel setting for 4x3 source without vertical zoom

5/6. The differential value for the expansion coefficient X shall be determined as follows:

X = (5/6) x (3/4) = 5/8 Auxiliary channel interpolator 359 maintains the correct aspect ratio for the small image and the objects within the image in the image are not distorted.

A particular advantage of widescreen aspect ratio televisions is that envelope format signals may be stretched to fill the entire widescreen, although it may be necessary to interpolate this signal to provide additional vertical resolution. According to the invention there is provided an automatic envelope size detection circuit that automatically performs stretching of a 4 x 3 aspect ratio video signal that includes a 16 x 9 aspect ratio video format aspect ratio. The automatic envelope format detector is explained in detail in FIG. 45 to 49.

In order to increase the vertical height of the envelope signal, the vertical scanning frequency is increased so that the black areas at the top and bottom of the image are removed or are at least substantially reduced. The automatic envelope format detector is based on the assumption that the video signal will generally correspond to the signal shown in FIG. 45. Areas A and C have no active image, or may have low luminance levels that are less than a predetermined luminance threshold. Area B has an active image or at least a luminance level that is higher than a predetermined luminance threshold. The respective region time intervals are a function of the envelope format, which may range from 16x9 to 21x9. The time lengths of sections A and C are approximately 20 lines for the 16x9 format. The envelope format detector checks the brightness levels of areas A and / or C. If an active image or at least a minimum brightness level is detected in areas A and / or C, the envelope format detector outputs an output signal, e.g. logic zero, indicating a 4x3 NTSC signal source. page format view. However, if the image is detected in area B, but not in areas A and C, then it is assumed to be an envelope signal source. In this case, the output signal would be a logical one.

The performance of the detector can be improved by the hysteresis shown schematically in FIG. 46. Once an envelope format signal has been detected, the minimum number of field signals in the normal format must be determined before the display changes to the 4x3 normal signals. Similarly, once a normal 4x3 signal has been detected, the envelope format for the minimum number of fields must be detected before switching the imaging unit in wide mode. The circuit 1000 of the reader 1004, the reader 100 includes a line and a detection circuit

1002, in which the above-described image signal analysis algorithm is performed.

In another embodiment of the embodiment of the invention, the envelope format detection is performed by calculating two gradients for each image line row. To calculate these two gradients, four values are required: the maximum and minimum values of the line being processed and the maximum and minimum values of the previous line. The first gradient, referred to as a positive gradient, is formed by subtracting the minimum value of the previous row from the maximum value of the current row. Second gradient; marked as a negative gradient, is formed by subtracting the minimum value of the current row from the maximum value of the previous row. Both gradients may have a positive or negative • value depending on the scene content, but negative values of both gradients may be ignored. This is because only one gradient can currently be negative and the size of the gradients with a positive value will always be greater than or equal to the size of the gradients with a negative value. This simplifies the circuitry, since the need to calculate the absolute value of the gradients is eliminated. If any of the gradients has a positive value that exceeds the programmable threshold, either

or on the previous line the presence of an image. These values can be used by the microprocessor to determine whether the image source is in envelope format or not. The circuit 1010 for performing this envelope format detection method is shown in the block diagram of FIG. 48. The circuit 1010 includes an input luminance filter, a line maximum detector 1020, a line minimum detector 1022, and an output section 1024. The input luminance filter includes pulse final response stages 1012 and 1014 and merge circuitry 1016 and 1018. The circuit 1010 de, 96, The envelope format tection processes digital luminance data Y IN from a wide range of 1 processor.

An input filter is used to improve the noise characteristics, making the detection more reliable. The filter is essentially formed by two stages of the final pulse response having the following transmission characteristic;

H (z) = (1/4) x (1 + Z ^') x (i + Z'')

The output of each stage is cut off to eight bits. (divided by two) to maintain the unit DC gain.

The row maximum detector 1020 includes two registers. The first register contains the maximum pixel value at the current point of the row period. At the beginning of each row period, the initial is initiated by an IR pulse of one hour pulse to 80h. A value of 80h is the minimum possible value of an 8-bit number in two complementary formats. The circuit is accessed by a signal labeled LTRBX EN having a logical 1 state of approximately 70% of the active image line. The second register contains the maximum pixel value for the entire previous line and is updated once per row period. Incoming luminance data Y IN compare! with an existing maximum pixel value stored in the first register. If they exceed the register value, the first register is updated in the next clock cycle. At the end of the image line, this register will contain the maximum value of the entire portion of the lines that have been accessed. At the beginning of the next image row, the value of the first register is introduced into the second register.

The row minimum detector 1022 operates in the same manner, except that its second register contains the minimum pixel value for the previous row. The minimum pixel value is initialized to 7Fh, which is the maximum possible pixel value for an 8-bit number in binary complementary format.

The output section 1024 takes the values of the two second registers and stores them in eight-bit strips that are updated once per line. Then two gradients are calculated, a positive and a negative gradient. On the first line of the field, where any of these gradients is positive and greater than the programmable threshold, an enable signal is generated that allows the computation of the existing line value to be entered into the first line register. At each row where either of the two gradients is positive and exceeds the programmable threshold, an additional enable signal is generated that allows the computation of the current row value to be entered in the last row register. The last line register will thus contain the last line of the field in which the threshold has been exceeded. Both of these enable signals can only act between lines 24 and 250 of each field. This prevents incorrect detection resulting from closed caption information and transient switching states of the VCR head. At the beginning of each field, the circuit is reinitialized and the first and second row register values are fed to the respective envelope register end registers. The LTRBX BEG and LTRBX END signals indicate the beginning and end of the signal in the envelope signal.

Fig. 49 illustrates an automatic envelope format detector as part of the vertical dimension control circuit 1030. The vertical dimension control circuitry includes an envelope format detector 1032, a vertical display control circuit 1034, and a three-port output circuit 1036. Alternatively, vertical blanking and reset pulses may be transmitted as separate signals. According to the invention, an automatic envelope format detector can automatically zoom in or stretch a 4 x 3 aspect ratio video signal that includes a 16 x 9 aspect ratio envelope format. If the VERTICAL SIZE ADJ output signal becomes active, increase the circuit 500 shows the vertical dimension control shown in FIG. 22, the vertical deflection height at a 4/3 ratio, thereby allowing the active picture portion of the envelope format signal to fill a wide screen without distorting the aspect ratio. In another alternative, not shown in the drawings, an automatic envelope format detector may include a circuit for decoding a code word or signal transmitted by an envelope format signal source, which code identifies the signal it is transmitted as a envelope format signal.

The vertical imaging control circuit 1.044 also determines which portion of the grid beyond the image dimension will be displayed on the screen. This is known as vertical panning. If the image signal with a larger vertical dimension is not in the envelope format, the conventional display format image will be zoomed, i.e.. j. stretched to simulate the wide format. In this case, however, the cut off portions of the 4/3 format image will contain the active image information. Vertical cropping of 1/3 image is necessary. therefore, regardless of further interventions, the top sixth and bottom sixth of the image will always be cropped. However, the image content may indicate that it is better to crop more of its upper part than the lower part, or vice versa. For example, if all of the downtime is at the lower level, i.e. j. on the ground, the viewer may prefer to crop more of the sky. Thus, the vertical panning capability allows you to select which portion of the transoculated image will be displayed and which portion will be streaked.

The vertical panning is explained with reference to FIG. 23 and 24 (a) to (c). In FIG. 23 shows a three-level vertical blanking and resetting signal in the upper part. These signals can also be generated separately. The vertical blanking pulse starts when the L COUNT signal is equal to VRT BLNK and ends when the LCOUNT signal is equal to VRT BLNK1. The vertical reset pulse starts when the L COUNT signal is equal to VRT PHASE and lasts for 10 horizontal lines. The LCOUNT signal is the output of a 10-bit counter used to keep track of horizontal lines relative to the rising edge signal VSYNCMN. The VSYNC_MN signal is a synchronized version of the VDRV MN signal, which is the vertical synchronization component of the main signal routed to the gate array. The VRT BLNKO and VRTBLNK1 signals are generated by the microprocessor depending on the vertical panning command. The VRTPHASE signal programs the relative phase of the VERT RST output relative to the rising vertical sync component in the COMPSYNC output. The COMP SYNC output is the output of a J-K flip-flop. The state of this flip-flop is determined by decoding the counter outputs. L COUNT and H COUNT. HCOUNT is a horizontal position counter. The L COUNT counter is used to divide the COMP SYNC signal into three segments corresponding to the horizontal synchronization pulse, the equalization pulse, and the vertical synchronization pulse.

100

The vertical deflection current without image overhang, which in fact relates to a normal six percent image overhang, is shown in dashed lines, as it is the corresponding vertical blanking signal. The vertical blanking pulse width without image overhang is C. The vertical sync pulse is in phase with the vertical reset pulse. The vertical deflection current is shown in solid line for the image overlap mode. It is the corresponding vertical blanking pulse of width D.

If the lower projection of image A is equal to the upper projection of image B, the representation will be in the form shown in FIG. 24 (a). If the vertical reset pulse is formed to lag behind the vertical sync pulse, the lower overlap of image A is less than the upper overlap of image B, resulting in the image shown in FIG. 24 (b). This is a vertical pan downward, depicting the lower part and obscuring the upper third of the defense. Conversely, if the vertical reset pulse is formed to precede the vertical sync pulse, the lower image overlap is greater than the upper image overlay B, resulting in the image shown in FIG. 24 (c). This is pan upwards, showing the upper part and dimming the lower part of the image. The phase sync of the vertical sync signal and the vertical reset signal can be controlled by the widescreen microprocessor 340, allowing vertical panning during the overlap of the operating mode image. Obviously, the overlapped image grid remains vertically centered or symmetrical during vertical panning. The blackout interval can be moved or positioned vertically asymmetrically to the center of the screen, obscuring the greater part of the image up than down or vice versa.

A wide-screen television according to various embodiments of the arrangement according to the invention can stretch or compress the image using adaptive interpolation filters. Interpolators for the main and auxiliary signal time components may be time shift correction filters. For example, a four-point interpolator includes a two-point linear interpolator and a merged filter and multiplier that are cascaded to provide amplitude and phase compensation. Overall, four adjacent data samples are used to calculate each interpolated point. The input signal is fed to a two-point linear interpolator. The delay of this input is proportional to the value of the delay control signal (K). Amplitude and phase errors are delayed signals are minimized using a correction signal obtained by the additional filter and multipliers that are cascaded. This correction signal performs a spike that balances the frequency response of the point-to-point linear interpolation filter for all values (K). The original four-point interpolator is optimized for use with passband signals_i/ 4, where f ;; is the data sampling frequency.

According to another alternative embodiment of the invention, both channels can be used, which is called a two-step interpolation process. The frequency response of the original interpolation filter variable can be improved by using such a two-step process. This process is hereinafter referred to as two-step interpolation. The two-stage interpolator of the invention comprises a final pulse response filter of 2n + 4 taps with fixed coefficients and a four-point variable interpolator as shown in FIG. 56 and 57. The final pulse response filter output is spatially positioned midway between the input image samples

A (' _k .'

102 of the element as shown in FIG. 56. The output of this filter is then combined by interleaving with the original data samples which are delayed to produce an effective sampling rate of 2fs. This is a valid assumption for frequencies in the bandwidth of the final pulse response filter. As a result, the effective transmission bandwidth of the original four-point interpolator is greatly expanded.

Compensated variable interpolation filter, known i

of the prior art, produces accurate interpolated samples until the frequency components of the signal are greater than about one quarter of the sampling frequency, ie 1/4 fs. For signals having a frequency component substantially greater than; 1/4 f _s , a two-step approach may be used, as shown in the block diagram for the two-step interpolator 390 in FIG. 58. The DSA digital signal sampled by the sampling frequency f _of the filter, it enters the final impulse response, e.g., the solid filter 391. The filter 391 forms a final impulse response of the DSA signal, second digital signal DS B samples to the sample rate of f., But the time points between the values of the first DSA signal, for example at midpoints between these values. The DS_A signal is also an input to the delay circuit 392, which produces digital samples that are identical

DS_A, but time delayed by (N + 1) / fs. The data streams DS_B and DSC are combined by interleaving in the multiplexing circuit 393, resulting in a data stream value of a DSD at twice the sampling rate, or 2f s. The DS_D data stream is the input of the compensated variable interpolator 394.

Generally, a fixed pulse response filter is designed to accurately produce multiple samples corresponding to time locations accurate halfway between the DS C half signal and the signal

- 103 hami incoming samples. These are then interleaved with delayed but otherwise unmodified samples, creating a data rate of 2fs. Final impulse response filter. tends to be the most common. generated using an even number of symmetrical balanced taps. An eight-branch filter that has, for example, a branch weight:

-1/32, 5/64, -11/64, 5/8, 5/8, -11/64, 5/64, -1/32, will accurately interpolate signals having frequency components up to about 0.4 f ?. Since the data interleaving frequency is doubled to 2f _: .-. , the signal processed by the proportional interpolator never contains a frequency component higher than 1/4 of the sampling frequency.

The advantage of the two-stage interpolator is to enable accurate interpolation of signals with bandwidths approaching one half of the sampling frequency. Thus, the system is best suited for display modes that require time stretching, such as zoom, where the aim is to retain as much of the original bandwidth as possible. This may be possible with widescreen television, especially with an auxiliary channel, where the auxiliary signal is initially sampled at a relatively low frequency, for example 10 MHz. Maintaining as much of the bandwidth as possible may be important.

A two-stage interpolator 390 'that is suitable for zooming is shown in the block diagram of FIG. 59. The components that are common to the interpolator 390 shown in FIG. 17, may have the same reference numerals with respect to data flows. The purpose of the two-stage interpolator 390 'is to horizontally zoom the incoming image by the factor m, with m being greater than 2.0. Thus, if the input and output data signals have the same sampling frequency f j, the output samples must be generated for each input sample. The signal is stored in line memory 395 with ob104 '.

• Z <>

the servant in the order of arrival at frequency i and its part is then read as the data stream DS A at the reduced frequency? . Hourly pulses f .; they are formed under a system of clock impulses f; »and do not have a uniform period.

The data stream DS B corresponding to the sample values in the middle between the existing data stream DS A samples is determined using a fixed filter 391 of the final pulse response and then interleaves with the delayed data stream DS C samples to form a double frequency DSD data stream. The DS_D data stream, which has twice the original sample density, is then processed by the variable interpolator 394 to produce sample values for each period of f k. The shifting circuit comprising the inverter 398 and the summator 399 produces an output which, with each hour period f; k increases by increment r = 2 / m. The fractional portion id-drives the variable interpolator by feeding the K value from inverter 398. The integral carrier output (CO) produced by means of latch 397 clock pulses 2f _of the read operation of memory 395 in order of arrival and the displacement data 391 the final filter response irnpulsú ~ Delay-making circuit 392, the multiplex circuit 393 and interpolator 394. The slit 396 forms a signal from a 2f ·; signal f?. .

According to other embodiments of the invention, interpolators may be used, the advantage being that they store the image of the auxiliary and the main channel in a buffering manner without additional line memory. Thus, the main channel line memory also becomes an image memory. Existing variable interpolation filters require double multiplication. The first multiplication is performed by a factor C, which is a two-bit number. The second multiplication is performed by a factor of K. The factor of K is a five-bit number, allowing the case where K = 16/16. they are

105 two ways to avoid the need for five-bit multiplication. The first option is to multiply by a factor of 1-K instead of K, whereby K = 0 is never selected as the display point. The second option is to multiply by the factor K, whereby K = 1 is never selected as the display point.

A simplified multiplier for an 1/16 or 1/32 interpolator is shown in FIG. 61. The multiplier allows multiplication of a variable and a five-bit variable ^. b, where b = (b _4, bj, b ?, b, bo). The expression b, ·, is the least significant bit and b. _t is the most effective bit. The values of b are limited to integers between 0 and 16, inclusive, although a similar procedure can be used to create more complex multipliers. For example, a multiplier for integers between 0 and 32 can be derived from the same rule. If b = 10000, the multiplier multiplies the output of the preceding addition circuit by at least two. For the arrangement shown, the number and number is on bits. The conditional multiplication function of two may be performed, for example, by a shift register or a multiplexing circuit.

The K and C values can be stored in a memory block and the counter can, depending on the required acceleration. index the read pointer to retrieve the desired memory location and load K and C values into interpolation multipliers. For this reason, it is very advantageous if the C value is encoded into a K value so that a single four-bit or five-bit word can transmit both the K value and the C value. The C value is then a function of the K value. . 62, where K is a five-bit number. In the arrangement shown in FIG. 63, a greater number of summation gates may be used to accurately determine C values. The values are shown in the table in FIG. 64th

To achieve different waveforms, the functions C ~ f (K) are

106, another possible embodiment as shown in the example of the alternative decoder of FIG. 65. By using this decoding scheme, for example, the need for a single-chip lookup table or additional registers for storing values can be eliminated by using only a few gates. Cinitel K can be more easily decoded using the circuit shown in FIG. 66th

The two-step interpolation explained by FIG. 56 to 58 may be optimized to overcome the value of 0.25 fs, where fs is the original sampling rate, in an alternative manner to that of FIG. 59 shows the response at 0.25 fs in size for all K = (0, 1/8, 2/0 ... 1) values of 0.5 dB. If the amplitude responses of the various interpolation filters are more than 0.5 dB apart, visible errors can be expected. In certain simulations, it was found that ζθ visible errors can occur at an amplitude response of more than 1.0 dB. The individual response of the horizontal interpotedy should be

Frequency curves that the deviation frequency described in conjunction with FIG. 67.

1 of the K envelope response.

for selected values where response curves of more than 1.0 are not spaced dB for any frequency as shown in FIG. 67. The critical frequency at which visible errors can be expected is indicated by f c. In practice, the cut-off frequency or the divergence of the frequency curves should be reduced as low as possible. With the arrangement according to the invention, the frequency bandwidth of the interpolator can be expanded by a 2n + 4 compensating circuit which extends the value f c for the whole horizontal interpolation. Moreover, such a compensating circuit can be made without adding another control variable and thus without

107 additional degree of freedom.

The following linear interpolation compensation circuit may extend the critical frequency f, ·, of the total interpolation to 0.7 x fs / 2 or 0.35 f _d , using the 0.5dB maximum envelope criterion. If the 1.0 dB criterion is used, diverging curves at f _i; = 0.75 xf _; -./2 = 0.375 f _K. In addition, if the design of K = 0 and K = 1 is limited in the design so that there is no need to select, the bandwidth may be increased even slightly beyond f. By selecting the C value, the range of spikes can also be adjusted.

By means of a linear interpolator, an eight-point interpolator can be formed with an eight-tap final pulse response filter for amplitude and phase compensation. The total interpolator for K = (0, 1/16, 2/16, ... 1) can be described as follows:

C / 2 - Z '(C ~ ^R) + CU + Z C) Z-3 + (1 - C + C) - Z * (3/2.) (C) + (C./2) (FROM-'·· ) .

The relationship between K and C is shown in the table and graph in FIG. 68 and 69. A set of curves shows that the ripple in the transmission band is less than 1.5 dB. The critical frequency for this compensation circuit is at 0.7 xf _s / 2.

This embodiment of the invention can also be extended to a multi-tapped compensation circuit that provides additional usable bandwidth.

The eight-point interpolator may consist of an eight-point final pulse response compensation filter and a two-point linear interpolator, as shown in FIG. 70th

The following relationships can define three such compensation circuits:

(1) —C / 4b Z- '· (3 / 4HC) + Z-' (-3/2) (C) + Z ~ ^J (K + C)

108 + (1- K +

Z ⁷ (-C / 4) (2) -C / 8 + Z + Z-1 (1-K

C) Z '' i + Z- s (-3/2) (C) + Z i (5/8) (C) + Z2 (-12 / 8) (C) + + C) + Z ' ^r, (-12 / 8) (C) + Z (3/4) (C) + z - ³ (K + C) (5/8) (C) +

Z- ⁷ (-C / 8), and (3) -C / 8 + Z - (C / 2) + and Z-4 (1 - K + C) and

Z -? (-11 / 8) (C) Z “ ⁶ (-11 / 8) (C) + z · η k + c) + Z ⁶ (C / 2) +

Z- ⁷ (-C / 8), where K = (0, 1/16, 2/16, ... 1)

Each of these circuits. has its own distinct bandwidth and advantages. For the arrangement of FIG. 70, the K and C tables are not shown. The C value may be selected to allow the most convenient set of curves to be obtained for any particular compression or expansion as a whole.

The control signal sends a K value to the linear interpolator. The K value is then decoded to obtain a C value for the compensation circuit multiplier. In all interpolation equations, the multipliers of the C value are the coefficients of the final impulse response. For example, the above equation (1) has tap weights (-1/4, 3/4, -3/2, 1, 1, -3/2, 3/4, -1/4).

This embodiment of the invention can generally be extended to 2n tap impulse response filters used as compensation circuits, although using only two linear multipliers to calculate linear interpolation and the associated compensation circuit can be quite difficult. An alternative to a 10-tap final pulse response filter may be, for example, the use of an 8-tap fixed filter for Z ¹ to Z ^-6 taps, with Z ⁸ and Z ⁷ taps dependent on some of K and C. This is feasible because frequency response needs additional compensation for widening the passband if K approaches

109 from any direction of 1/2, i. j. if K = 0 or K = 1.

In FIG. 60 is a block diagram of a specific circuit 1150 for forming an eight-branch two-stage filter using a four-point interpolator. The luminance image signal to be expanded or compressed is the input of the lag delay circuit 1152. The delay circuit outputs, designated ZT Z-. FROM-··'. Z-3, Z · », 7th · · Z ^- '· and Z -' inputs osmiodbočkového 1154 final filter impulse response. This filter generates at least one set of labeled I-labeled samples, for example between actual Z-labeled samples. The results can sometimes be improved by using a plurality of pulse response filters that generate a plurality of intermediate point sets, since this significantly increases the complexity of the system. Such additional filters, each requiring a delay circuit Z ^{- 1,} are illustrated by multiplying the final impulse response filter 1154 and the delay circuit 1158 for Z * ^? . The outputs Z ^-3 , Z ⁴ and Z are also the inputs of the delay adaptation circuit 1156. Output I 'is the primary input of the data selector circuit 1160, like its version I-delayed by the circuit 1158. Outputs Z ~ ''>r;, Z ^- ' ⁴ *' · and 2 ~ · ^{5, Ί:} are also the inputs of the data selector 1160. The inputs of the data selector circuit 1160 are selected to be as uneven as possible with respect to the delay. The number of such inputs is one greater than the number of points of the second stage interpolator, in this case the four-point interpolator 1102. The relative time position of the data selector 1160 is as follows:

Z ~ ' ³ ' · ', I, Z - ⁴ ·· n! , I-1, Z- ^: * ^{: i}

MUX SEL multiplexer selector circuit 1160. You select Other data sets can be a pole, for example, the control signal is diagrammatically indicated

- 110 are arranged and arranged so that any interpolation of the interpolator 1162 t> y 1 based on two real points and two intermediate points. The outputs Y0, Y1, Y2 and Y3 of the data selector circuit 1160 correspond to one of two selectable sets and are the inputs of a four-point interpolator 1162. The operation of the multiplexer control signal MUX_SEL is a function of K, t. j. MUXSEL = f (K). The choice of the MUX SEL signal depends on which of the original points is the intermediate point. The output Yout of the interpolator 1162, which responds to the K and C control responses, is a molten or compressed image luminance signal.

Claims (18)

A display system comprising display means having a first aspect ratio of the display format, means for mapping an adjustable display region in display means, means for processing the first and second video signals from input video signals of one of different display aspect ratios, switching means for optional association. video source sources such as said input video signals, means for selecting the first or second video signal or a combination thereof as output video signal, and means for controlling mapping means, processing means, and selector means to adjust the aspect ratio of the display format and aspect ratio of each image transmitted by the output video signal The display system of claim 1, wherein one of the different display format ratios is the same as the first display format ratio. 3. The imaging system of claim 1, wherein the processing means is adapted to selectively trim the input video signals. The display system of claim 1, wherein the mapping means comprises means for forming a screen for the screen. 112 The display system of claim 1, wherein the mapping means comprises means for forming an address matrix for the liquid-crystal display unit. 6. The display system of claim 1, wherein said display region is adjustable in only one dimension. Display system according to claim 6, characterized in that the display area is adjustable only in the vertical direction. 8. The imaging system of claim 1, wherein the processing means is adapted for horizontal interpolation of video signals. 9. The imaging system of claim 1, further comprising means for converting interlaced video signals to a non-interlaced image format. 10. The imaging system of claim 1, wherein the video signal sources comprise channel selectors and a preamplifier ^. - 113 video connectors. The imaging system of claim 1, wherein the processing means comprises respective interpolation means for the first and second input video signals. Display system according to claim 11, characterized in that the display area is adjustable only vertically, wherein the processing means interpolate the input video signals only horizontally. The imaging system of claim 1, wherein the mapping means comprises horizontal and vertical biasing circuits for generating a raster, wherein the raster is vertically adjustable and the processing means integrates the input video signals only horizontally. The imaging system of claim 11, wherein the interpolation of the input video signals is performed by selectively stretching or compressing the input video signals. 15. The imaging system of claim 1, further comprising second means for selecting between an output video signal and an external video signal for display by the mapping means and the display means. 16. Imaging system indicating; with means for synchronizing detergents. j í 11. The method of claim 1, wherein the composition comprises processing and expanded materials 17. Imaging system containing imaging means of first aspect ratio and other mapping means Other imaging areas in imaging means of the first means for processing indicate input video signals having one of a different aspect ratio format, with optional interpolation and trimming of the signal. second means for processing data from the input video signals having one of the formats having a different ratio with optional interpolation and signal trimming, switching means for selectively connecting the video signal sources as the input video signals, the means for selecting. 115 an output signal between selectively interpolated and trimmed output signals from the first or second processing means and a combination of selectively interpolated and trimmed output signals. both processing means, and means for controlling the mapping means, the first and second processing means, and the selective means for adjusting each picture contained in the output video signal in an image ratio and a porn side format. The display system of claim 17, wherein one of the different display ratio formats of the input video signals is the same as the first display ratio format of the display means.