SK280556B6 - Wide-angle tv image-forming set - Google Patents

Abstract

A display system comprises: a display (244; 115) having a first format display ratio that is coupled with a mapping circuit (50; 113) to provide conversion of an output video signal (Y_MX, U_MX, V_MX) onto a different format display; a plurality of video signals (Y_M, U_M, V_M; Y_A, U_A, V_A), each of said video signals (Y_M, U_M, V_M; Y_A, U_A, V_A) having one of different format display ratios; video processor (304, 306) for processing at least two of said plurality of video signals (Y_M, U_M, V_M; Y_A, U_A, V_A), as necessary, to be compatible with one another and with said display (244; 115); switching means (SW1, SW2, SW3, SW4) for coupling first and second ones of said video signals (Y_M, U_M, V_M; Y_A, U_A, V_A) as inputs to said video processor (304, 306); a selector (312) for selecting, as said output video signal (Y_MX, U_MX , V_MX), between: one of said first and second ones of said video signals (Y_MN, U_MN, V_MN; Y_AUX, U_AUX, V_AUX) as processed.

Description

Technical field

The present invention relates to a television imaging system, in particular a widescreen imaging system that interpolates image data to produce different display formats, both direct viewing and projection display systems.

BACKGROUND OF THE INVENTION

Most of today's television systems have an aspect ratio, ie. j. horizontal to vertical height ratio of 4: 3. Widescreen viewing is more in line with the movie display format, such as 16: 9. Televisions with a 4: 3 aspect ratio, often referred to as 4x3, have limited viewing options from single and multiple video sources . Television broadcasts broadcast by commercial broadcasters are, except for experimental broadcasts, broadcast in 4x3 format. However, many viewers find the 4x3 display format less satisfactory than the wider display format that is common with movies. Television with a wider display format not only provides more enjoyable viewing, but is also capable of displaying widescreen sources in the corresponding widescreen viewing format. Movies are displayed in their original format and not in truncated or distorted form. The video source does not have to be truncated, even if the film is converted to a video signal, for example using a film sensor or processors in a television.

The widescreen aspect ratio of the image can be applied to both basic or standard line decomposition rates as well as multiples thereof, as well as interlaced and non-interlaced lines. For example, standard NTSC video signals are displayed by interleaving consecutive fields, each field being generated by raster scanning at a basic or standard line scanning rate of approximately 15,734 Hz. The basic degradation rate of the video signals is denoted differently, either f _H , lf _H or 1 H. The actual frequency of the signal lf _H will vary depending on different video standards. In order to improve the image quality of television devices, systems for displaying video signals in a progressive manner without interleaving have been developed. Progressive scanning requires that each displayed frame be deinterleaved within the same period of time as is allocated to decompose one or two frames of the interlaced format. Flicker-free AA-BB images require each field to be staggered twice in succession. In any case, the line decomposition frequency shall be twice the standard line frequency. The degradation rate for such sequential or flicker-free displays is referred to as 2f _H or 2H. For example, according to US standards, the scanning frequency is approximately 31,468 Hz.

Widescreen TVs are also adapted to display both conventional and widescreen signals as well as a combination of them in a multiple display system. However, the use of widescreen TV displays presents numerous problems. The main areas of these problems are alternating display formats at multiple signal sources, generating equal time signals from asynchronous but simultaneously displayed sources, creating high resolution images from densified data signals, and switching individual multiple sources to generate multiple display systems.

SUMMARY OF THE INVENTION

These problems are solved by a wide-screen television display system according to the invention. SUMMARY OF THE INVENTION The display system comprises a display screen in a first aspect ratio of the display format coupled to a mapping circuit to enable the output video signal to be converted to another display format, a set of video signal inputs, each of the video signals being a picture information signal in one from a variety of display formats, a screen-coupled image processor for processing at least two of the set of video signals to achieve mutual compatibility between the signals and to make the signals compatible with the screen, switches connected to the image processor inputs to provide the first and second video signals; the video processor outputs coupled to an output video signal to select either one of the first and second processed video signals, wherein the output video signal is a single image display, or to select a combination of first and second processed video signals, wherein the output video signal is a multiple image display, and a control circuit of the mapping circuit, the image processor, and the output video signal selector to adjust each picture transmitted by the output video signal in the aspect ratio of the display format and aspect ratio of the picture displaying both a single and a multiple image.

In one preferred embodiment, the first aspect ratio display screen has a wide aspect ratio aspect ratio. In another preferred embodiment, one of the set of video signal inputs is a video signal input with a first aspect ratio of the screen display format.

It is preferred that in this embodiment, the screen having the first aspect ratio of the display format has a aspect ratio of a wide white display format.

In another preferred embodiment, one of the plurality of video signal stacks is an input of an image signal having a aspect ratio of a display format different from the first screen of the display format.

Preferably, in this embodiment, the screen having the first aspect ratio of the display format has a aspect ratio of the widescreen display format.

In another preferred embodiment, two of the set of video signal inputs are video signal inputs having a display format aspect ratio different from the first screen display aspect ratio.

Preferably, in this embodiment, the screen having the first aspect ratio of the display format has a aspect ratio of the widescreen display format.

In yet another preferred embodiment, one of the video signal input sets is a video signal input with a first aspect ratio of the display format of the display means, and another of the video signal input set is a video input with an aspect ratio of display format different from the first aspect ratio of the display format.

Preferably, in this embodiment, the display having the aspect ratio of the display format has a aspect ratio of the widescreen display format.

SK 280556 Β6

The image processor preferably comprises a trimming circuit for selective trimming and an interpolator for selective interpolation of each of the first and second of the video signal array.

The mapping circuit preferably comprises a screening circuit for creating a screen grid, or an address matrix array for a liquid crystal screen.

Further, the mapping circuit is preferably configured to provide independent adjustment of the image size in the first direction, and the image processor is configured to provide independent adjustment of the image size in the second direction, perpendicular to the first direction, wherein the image is represented by an output image signal.

It is also preferred that the mapping circuit is configured to provide independent image size adjustment in the horizontal or vertical direction, and the image processor is configured to provide independent image size adjustment in the vertical or horizontal direction.

In another preferred embodiment, the mapping circuit and the screen are formed to work with non-interlaced video signals having a horizontal spread rate nf _H , where f _H is a normal horizontal spread rate n and is a positive integer, and further comprises means for converting video signals having interlaced format and horizontal the spread rate f _H on image signals having an unfolded image format and the horizontal spread rate nf _H.

In a further preferred embodiment, a second selector connected to the mapping circuit comprises a choice between an output video signal and another input video signal, which is applied to the mapping circuit along a signal path that bypasses the image processor.

In another preferred embodiment, the screen has a widescreen aspect ratio, the various aspect ratios are either a conventional aspect ratio aspect ratio or a screen aspect ratio aspect ratio, a first and a second image processor each including means for trimming and interpolating the video signals. for processing at least two of the video signal set as desired, the control circuit is configured to selectively implement a multiple picture display format set wherein some of the display format sets are different video signal formats having a different aspect ratio of the display formats, at least one they differ from the first aspect of the screen display format.

In this embodiment, preferably, the video signal input is an input of the video signal carrying the main picture with the aspect ratio of the widescreen format and the overlapping auxiliary picture with the aspect ratio of the conventional format, and the main picture with the aspect ratio of the conventional format and overlapping the auxiliary picture with the aspect ratio of the wide format.

BRIEF DESCRIPTION OF THE DRAWINGS

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be explained in more detail with reference to the drawings, in which: FIG. 1 (a) to 1 (i) different widescreen display formats; FIG. Fig. 2 is a block diagram of a widescreen television display system according to the invention adapted for operation in line scanning 2f _H ; 3 is a block diagram of the widescreen processor shown in FIG. 2, FIG. 4 (a) a block diagram of a widescreen television display system according to the invention adapted for operation in line scanning

I f _H, FIG. 4 (b) a block diagram of a widescreen television display system according to the invention adapted to operate with a liquid-crystal display unit; FIG. 5 is a block diagram of the widescreen processor shown in FIG. 4, FIG. 6 is a block diagram with further details of the widescreen processor of the common diagrams of FIG. 3 and 5, FIG. 7 is a block diagram of an image forming processor in the image shown in FIG. 6, FIG. 8 is a block diagram of the gate array shown in FIG. 6 with the main, auxiliary and output signal sides, FIG. 9 and 10 show the time-lapse diagram of the display format of FIG. 1 (d) with completely truncated signals, FIG. 11 (a) is a block diagram with a more detailed illustration of the path of the main signal of FIG. 8, FIG. 11 (b) a waveform of the main signal of FIG. 11 (a) when the video signal is pressed, FIG.

II (c) the shape of the main signal of FIG. 11 (a) when the video signal is expanded, FIG. 12 is a block diagram showing in greater detail the path of the auxiliary signal of FIG. 8, FIG. 13 is a block diagram of a timing and control portion of the image-in-picture processor of FIG. 7, FIG. 15, 16 and 17 are block diagrams of the decimation portion of the timing and control portion shown in FIGS. 14, FIG. 18 is a table of values used to control the decimation portion shown in FIG. 15 to 17, FIG. Figures 19 (a) and 19) b) block diagrams of fully programmable universal decimation circuits for controlling horizontal and vertical compression ratios; 20 is a block diagram of the interleaved line conversion circuitry shown in FIG. 2, FIG. 21 is a block diagram of the noise attenuation circuit shown in FIG. 20, FIG. 22 is a combination of the block diagram and the circuit diagram of the deflection circuit shown in FIG. 2, FIG. 23 shows the time courses of the vertical movement of the image, FIG. 24 (a) to 24 (c) display formats according to the waveforms shown in FIG. 23, FIG. 25 is a block diagram of the RGB interface shown in FIG. 2, FIG. 26 is a block diagram of the RGB to Y, U, V converter shown in FIG. 25, FIG. 27 is a block diagram of the circuit for generating the internal 2f _H signal in the transfer FF _H to 2f _H, FIG. 28 shows a different block diagram of a portion of the auxiliary signal path shown in FIG. 8, FIG. 29 is a diagram of a five-row memory with an operator in order of arriving to avoid collisions of the read / write pointer; FIG. 30 is a block diagram of a simplified circuit serving as an auxiliary path synchronization circuit in a gate array; FIG. Figure 31 is a diagram of the time dependence between the status of the field indicator and the image line; 32 to 34 of a diagram of a method of maintaining interleaving integrity of co-displayed interleaved video signals simultaneously; FIG. 35 (a) to 35 (c) waveforms of the signals processed by the circuit shown in FIG. 36, FIG. 36 is a block diagram of the interleaving integrity circuit of FIG. 31 to 35, FIG. 37 is a schematic diagram of an arbitrary access image memory operation associated with an image-in-picture processor; FIG. Fig. 38 is a block diagram of an output switching control circuit between the main and auxiliary video signals; 39 and 40 are block diagrams of individual data reduction and recovery circuits performing the function of the resolution processing circuit of FIG. 6 and 8, FIG. 41 and 42 are block diagrams of a two-bit data reduction and recovery circuit to supplement the resolution processing circuit of FIG. 6 and 8, FIG. Fig. 43 is a table of values forming a rotation scheme to improve operation of data reduction and recovery circuits; 44 is a schematic table explaining another alternative of showing the resolution processing circuits of FIG. 6 and 8, FIG. Figures 45 and 46 illustrating the operation of the automatic envelope detector; 47 is a block diagram of an automatic envelope detector; FIG. Fig. 48 is a block diagram of an alternate demonstration of an automatic envelope detector circuit; Figure 49 is a block diagram of a vertical image adjustment circuit including an envelope detector; Figs. 50 (a) to 50 (f) shape waveforms of color components of the main video signal when converting from analog to digital; FIG. 51 (a) and 51 (b) shape diagrams explaining the inclination of the brightness and color components as the main signal passes through the gate field; FIG. 52 (a) and 52 (b) of a portion of the path of the timing components and the color components of the main signal when the image is compressed; FIG. Figs. 53 (a) to 53 (1) shape diagrams explaining the compression of the color components relative to the components of time; FIG. 54 (a) and 54 (b) of a portion of the path of the timing and color components of the main signal when the image is stretched; 55 (a) to 55 (1) shape diagrams explaining the expansion of the color components relative to the luminance components; FIG. 55 and 57 illustrate the operation of the two-step interpolation filter variables usable in the interpolators of FIG. 8, 11 (a) and 12; FIG. 58 is a block diagram of a two-stage compensated interpolation filter variable; FIG. 59 is a block diagram of a two-stage compensated filter variable arranged for zooming; FIG. 60 is a block diagram of an eight-branch two-stage interpolation filter circuit; FIG. 61 is a block diagram of a resolution interpolator 1/16 or 1/32; FIG. 62 shows a table of K and C values for the interpolator shown in FIG. 61, FIG. 63 is a block diagram of a circuit for determining C values from K values; FIG. 64 is a table of values calculated by the circuit of FIG. 63, FIG. 65 is a block diagram of an alternate embodiment of a circuit for determining values of C from values of K; FIG. 66 is a block diagram of another alternative embodiment of a circuit for determining values of C from values of K; FIG. 67 shows the frequency response curves of a conventional two-stage four-point interpolator; FIG. 68 and FIG. 69 is a graph illustrating the frequency response of an eight-point interpolator and FIG. 70 is a block diagram of an eight-point interpolator with a frequency response corresponding to FIG. 68 and 69.

DETAILED DESCRIPTION OF THE INVENTION

The individual parts of FIG. 1 illustrate some, but not all, of the various combinations of single and multiple image formats that may be made by various embodiments of the display system of the invention. The selected illustrations are intended to facilitate the description of the individual circuits contained in the widescreen television display system of the invention. For the sake of simplicity of illustration and description, a 4x3 ratio is assumed to be a conventional width-to-height ratio for an image source or signal, while a 16x9 is generally considered a wide-width to height-ratio. are limited to these ratios.

Fig. 1 (a) shows a television for direct observation or projection with a conventional 4x3 display format. If the transmitted image is a 16x9 aspect ratio as a 4x3 signal, black bars appear at the top and bottom of the screen. This is commonly referred to as an envelope format. In this case, the observable image is quite small relative to the total display area available. Another possibility is that the 16x9 display source is changed before transmission, so that the image fills the entire vertical viewing range of the 4 x 3 display unit. However, in this case a lot of left and / or right information is cut off side. Another alternative is that the envelope image may be enlarged vertically, but not horizontally, but the resulting image will be significantly distorted by vertical dragging. None of these three options are appropriate.

Fig. l (b) shows a 16x9 screen. The 16xx9 image source is displayed in full, without cropping or distortion.

An image in a 26x9 envelope format, which itself is changed by a 4x3 signal, can be progressively degraded by doubling or adding lines to create a larger display with satisfactory vertical resolution. The widescreen television display system of the invention may display such a signal in a 16x9 aspect ratio format, whether from a main source, an auxiliary source, or an external color signal source.

Fig. l (c) shows a 16x9 main signal display in which the embedded picture is in a 4 x 3 display format. If both the main and the auxiliary video signal are 16x9 display sources, the embedded picture may also have 16x9 image views. The embedded image can be displayed in various positions.

Fig. 1 (d) shows a display format in which the main and auxiliary video signals are displayed with the same dimensions. Each image area has an 8x9 display format that is different from both 16x9 and 4x3 formats. In order to display a 4'3 display source in such an image area. without causing horizontal or vertical distortion, the signal on the left and / or right side shall be truncated. Most of such an image may be displayed with less cropping if some horizontal aspect ratio distortion is permissible. Horizontal compression results in vertical dragging of objects in the image. The widescreen television of the invention is capable of providing any combination of cropping and aspect ratio distortion, from maximum cropping without distorting aspect ratio to maximum distortion of aspect ratio without cropping.

The constraints imposed by the sampling of the data in the processing of the auxiliary video signal make it difficult to produce a high resolution image having the same size as the display of the main video signal. These difficulties can be overcome in various ways.

Fig. l (e) shows a display format in which a 4 x 3 picture is displayed in the center of a 16 x 9 screen. Vertical dark bands are visible on the right and left sides.

Fig. 1 (f) shows a screen on which one large 4x3 image and three smaller 4x3 images are simultaneously displayed. A smaller picture outside the perimeter of a large picture is sometimes referred to as an out picture rather than an in-picture picture. The term picture-in-picture is used herein for both display formats. If a widescreen television is equipped with two tuners, either internal or one internal and one external, for example in a connected video recorder (magnetoscope, video recorder), two of the displayed images may display real-time movement in accordance with the source. The remaining images can be displayed in still image format. Obviously, by adding additional tuners and auxiliary signal processing circuits, more than two moving images can be taken. It will further be appreciated that the large image and the three small images may also be switched to the position shown in FIG. 1 (g).

Fig. 1 (h) shows an alternative in which a 4x3 image is placed in the center of the screen and six smaller images are arranged in vertical columns on each side, also in 4x3 format. As with the previous arrangement, a widescreen television equipped with two tuners can provide two moving images. The remaining eleven images will be in the form of still images.

Fig. 1 (i) shows a screen with a field of twelve images in a 4x3 display format. Such an arrangement is particularly advantageous as a guide for channel selection, where each of the images is at least a still image pertaining to a particular channel. As with the arrangements described above, the number of moving pictures will depend on the number of tuners and signal processing circuits available.

The various formats shown in FIG. 1 are illustrative, but not limiting, and may be illustrated by a widescreen television shown in the other drawings and described in greater detail below.

In FIG. 2 shows a block diagram of a wide screen television display system 10 according to the invention, adapted to operate with 2f _H line scanning. The television display system 10 generally comprises an input circuit 20, video signals, a chassis or television microprocessor 216, a widescreen processor 30, a 40f _H / 2f _H converter, a mapping circuit 50 formed as a deflection circuit, a second color interface selector 60, a converter 240 YUV / RGB, screen driver 242, direct observation screen 244, or projection type, and power supply 70. Grouping of different circuits into different functional blocks is made for ease of description and does not limit the relative physical location of these circuits.

The video signal input circuit 20 is adapted to receive several complete video signals from different sources. The video signals may optionally be switched to be displayed as main or auxiliary signals. The radio frequency switch 204 has two antenna inputs ΝΤΙΝΤΙ and ANT2. These represent inputs for both outdoor antenna and cable reception. The radio switch 204 determines which antenna input is connected to the first tuner 206 and which to the second tuner 208. The output of the first tuner 206 is an input to the single-chip circuit 202 which performs a number of functions related to tuning, horizontal and vertical deflection and video signal control. The particular chip shown has the industrial designation TA7730. In the single-chip circuit 202, a baseband VIDEO OUT video signal is formed from the signal of the first tuner 206, which is routed both to the video signal switch 200 and to the TV1 input 30 of the wide screen processor. Other baseband inputs to video switch 200 are labeled AUX1 and AUX2. These can be used for camcorders, compact disc laser players, video players, video games and similar devices. The video switch output 200, which is controlled by the television microprocessor 216, is labeled SWITCHED VIDEO and is another input to the widescreen processor 30.

As further evident from FIG. 3, the wide screen processor switch SW1 30 selects between the signals TV1 and SWITCHED VIDEO, the output being a SEL COMP OUT video signal applied to the Y / C decoder input 210. The Y / C decoder 210 may be an adaptive line comb filter. The other two sources S1 and S2 of the image signals are also inputs of the Y / C decoder 210. Each of the inputs S1 and S2 represents a different S-VHS source and consists of separate luminance and color signals. The switch, which may be embodied as part of the Y / C decoder 210 in any of the adaptive line comb filters or as a standalone switch, responds to the microprocessor 216 TV signals and selects one of the brightness and color signal pairs designated as Y_M and C_TN outputs. The selected pair of luminance and color signals is then considered the main signal and is processed in the main signal path circuits. The designation of signals containing _M or _MN refers to the path of the main signal. The chrominance signal C_IN is redirected back to the single-chip circuit 202 to produce the difference color signals U_M and V_M. In this regard, U is the equivalent designation for (R-Y) and V is the equivalent designation for (B-Y). The signals Y_M, U_M and V_M are then converted into a digital form by the widescreen processor 30 for further processing.

The second tuner 208, which is functionally defined as part of the widescreen processor 30, generates a baseband video signal TV2. The switch SW2 selects between the signals TV2 and SWITCHED VIDEO as the inputs of the second Y / C decoder 220. The second Y / C decoder 220 may also be designed as an adaptive line comb filter. The switches SW3 and SW4 make the choice between the brightness and color outputs of the decoder 220 and the bright and color signals of the external video source indicated by Y_EXT and C_EXT. The signals Y_EXT and C EXT correspond to the S-VHS input S1. The decoder 220 and the switches SW3 and SW4 may be combined, for example, in adaptive line comb filters. The output of switches SW3 and SW4 is then considered as an auxiliary signal and is further processed in the auxiliary signal path circuits. The selected brightness output is indicated by Y_A. The designations of the signals comprising _A, _AX, _AUX refer to the path of the auxiliary signal. The selected color signal is converted to color difference signals U_A and V_A. The signals Y_A, U_A and VA are then converted to a digital form for further processing. The arrangement of the devices for switching the video signal sources into the main and auxiliary signal paths provides maximum flexibility in making the choice of sources for different parts of different display formats. The complete sync signal COMP SYNC, corresponding to the signal Y_M and generated by the widescreen processor 30, is fed to the sync signal separator 212. The horizontal synchronization component H and the vertical synchronization component V are the inputs of the vertical subtraction circuit 214 which generates a VERTICAL RESET signal fed to the widescreen processor 30. The widescreen processor 30 produces an internal vertical reset output signal INT VERT RST OUT directed to the second selector 60 in the color interface. The second color interface selector 60 makes a choice between an internal vertical reset output signal and a vertical synchronization component of the external source of the beacon signal. The output of this switch is a selected vertical synchronization component SEL VERT SYNC fed to a mapping circuit 50 formed as a deflection circuit. The horizontal and vertical synchronization components of the auxiliary video signal are produced by the synchronization mixture separator 250 in the wide-screen processor 30. Lf the signal transmitter 40 _H to 2f _H signal converts interlaced video signals to progressively scanned non-interlaced signals, e.g., those in which each line is displayed twice, or also when the interpolation of adjacent lines of the same field-based, an additional set of lines. In some cases, the use of the previous line or interpolated line will depend on the level of motion that is detected between adjacent fields or frames. The generation of 2f _H timing signals is shown in more detail in FIG. The converter circuit 40 operates in conjunction with a RAM image type 420.

This memory can be used to store one or more image frames to allow sequential display. The converted image data, such as signals Y_2f _H and V_2f _H , is fed to a second selector 60 in the color interface.

The second color selector 60, shown in more detail in FIG. 25, allows a choice between the converted image data or the external RGB image data to be displayed by the input circuit 20 of the video signals. The external color signal is considered to be a 2f _H widescreen display signal. From the widescreen processor 30, a vertical synchronization component INT VERT RST OUT of the main signal is fed to the second color selector 60, allowing the selected vertical synchronization component (f in _m or f _vext ) to be _mapped to the mapping circuit 50 formed as a deflection circuit. The widescreen function allows the user to select an external color signal by creating an INT EXT control signal. However, the selection of an external color signal input may lead to a vertical collapse of the screen and damage the screen or projection screen in the absence of such a signal. The second color selector 60, therefore, detects an external synchronization signal to prevent a non-existent internal color signal from being selected. The colors and time interval of the external color signal are also controlled by the microprocessor in function of the control circuit 340 of the widescreen image mapping circuit.

The widescreen processor 30 includes a picture-in-picture processor 320 that processes the video auxiliary signal. The term picture-in-picture is sometimes abbreviated as PIP or pix-in-pix. The gate array 300 combines master and auxiliary video signal data into a variety of display formats, some of which are shown in FIG. l (b) to 1 (i). The image-in-picture processor 320 and the gate array 300 are controlled by a microprocessor in function of the widescreen mapping circuit control circuit 340. A microprocessor in function of the widescreen mapping circuit control circuit 340 is in communication with the TV microprocessor 216 via a serial bus. The serial bus contains four signal lines for data, clock pulses, opening signals and reset signals.

The widescreen processor 30 further generates a complete vertical blanking and resetting signal in the form of a three-level sandcastle signal. Alternatively, the blackout and zero signals can also be generated as separate signals. The complete blanking signal is fed via the video signal input circuit 20 to the second color selector 60.

In the mapping circuit 50, which is designed as a deflection circuit and is shown in more detail in FIG. 22, a vertical reset signal from the widescreen processor 30, a selected horizontal synchronization signal at 2f _H from the second color selector 60, and additional widescreen processor control signals 30 are provided. These additional control signals relate to horizontal phasing, vertical adjustment and east / west adjustment. The mapping circuit 50, in the form of a deflection circuit, generates 2f _H feedback pulses fed to the widescreen image processor 30, the converter 40 to convert 1f ₁ to 2f _H to the YUV / RGB converter 240.

The operating voltages for the entire widescreen television display system are generated by a power supply 70, which may be connected to an AC network.

The widescreen processor 30 is shown in more detail in FIG. 3. The main components of the processor 30 are the gate array 300, the picture-in-picture circuit 301, the analog-to-digital and digital-to-analog converters, the second tuner 208, the microprocessor in the widescreen mapping circuit control circuit 340 and the widescreen output coding circuit 227. Further details of the widescreen processor 30 that are common to both 1f _H and 2f _H , e.g. The picture-in-picture circuit is shown in FIG. 6. The PIP 320 that forms a substantial portion of the PIP 301 is shown in more detail in FIG. 7. The gate array 300 is shown in more detail in FIG. 8. Some of the components shown in FIG. 3 and forming part of the main and auxiliary signal paths have been described in detail.

The second tuner 208 is coupled to the intermediate stage 224 and the audio stage 226 and operates in conjunction with the microprocessor as a control circuit 340 of the widescreen mapping circuit.

The microprocessor in function of the control circuit 340 of the mapping circuit includes an input / output circuit 340A and an analog output circuit 340B. The input / output circuit 340A generates color and time control signals, a 1NT / EXT signal to select an external color tone signal source, and control signals to switches SW1 to SW6. The input / output circuit 340A also monitors the EŽ T SYNC DET signal from the RGB interface to protect the deflection circuit and the screen (s). Analog output circuit 340B generates control signals for vertical adjustment, east-west adjustment, and horizontal phasing via respective interconnect circuits 254, 256, and 258.

The gate array 300 combines video information from the main and minor video signal paths to form a composite wide-screen image, for example, one of the images shown in different parts of FIG. The clock pulses for the gate array 300 are generated by a phase locked loop feedback loop 374 that cooperates with the low pass filter 376. The main video signal is fed to the widescreen processor 30 in analogue form and in YUV format as signals labeled Y_M, U_M and V_M. These main signals are converted from analog to digital by analog-to-digital converters 342 and 346, which are shown in more detail in FIG. 4th

The colorant signals have common U and V denominations, which can be assigned to either the RY or BY signals or the I and Q signals. The bandwidth of the sampled brightness signal is limited to 8 MHz because the system clock frequency is 1024 f _H , which is approximately 16 MHz. A single analog-to-digital converter and an analog-switch can be used to sample color component data because the U and V signals are limited to 500 kHz or 1.5 MHz for band I. The UV_MUX line selected for the analog switch or multiplex circuit 344 is 8 MHz signal derived by dividing the system clock frequency by two. A one-hour pulse width SOL pulse sets this signal at the beginning of each video line synchronously to zero. The UV MUX signal then changes its status in every row of the clock. Since the line length corresponds to an even number of clock cycles, the triggered state will continuously flip between 0 and 1 without interruption. The Y and UV data flows from the A / D converters 342 and 346 are shifted because each of the A / D converters has a delay equal to with one hour cycle. Similarly, in order to compensate for this data shift, the clock gate information from the main signal path interpolator control circuit 349 in the image processor 304 must be delayed. If the clock gate information was not delayed, the UV data would not be correctly matched upon rejection. This is important because each UV pair represents one vector. The element U of one vector cannot be paired with the element V of another vector without causing a color shift. Instead, sample V of the previous pair is discarded together with sample U of the new pair. This method of multiplexing the components U and V is referred to as 2 = 1: 1, since two samples of brightness are assigned to each pair of color components U, V. The Nyquist frequency for both U and V is effectively mixed to half the Nyquist frequency of brightness. Thus, the Nyquist output frequency of the analog-to-digital converter is 8 MHz for the luminance component, while it is 4 MHz for the color component.

The picture-in-picture circuitry 301 and / or gate array 300 may also include means for improving the resolution of the auxiliary data despite being compressed. A number of data reduction and recovery circuits have been developed including e.g. pressing pairs of pixels and correction codes. In addition, various data reduction correction sequences including different bit counts and different methods of compressing pixel pairs at different bit counts are contemplated. One of these data reduction and recovery schemes can then be selected by a microprocessor in the function of the widescreen mapping circuit control circuit 340 to achieve maximum display resolution for each individual type of display format.

The gate array 300 includes interpolators that interact with the line memories 356 and 358 with the operator in the order of arrival. Interpolators and memories are used to resample the main signal. Another interpolator can perform resampling of the auxiliary signal. The clock and sync circuits arranged in the gate array 300 control the handling of both the main and auxiliary signal data, including combining them into a single video output signal having the components Y-MX (should not be Y MX?), U_MX, and V_MX. These output components are converted into analogue form by the analog-to-analog converters 360, 362 and 364. The signals Y, U and V are in analogue form fed to the converter 40 to convert 1f _H to 2f _H , where they are converted to non-interlaced scanning. The Y, U, and V signals are also encoded by the Y / C encoder 227 to produce a Y-OUT-EXT / COUTEXT output signal with a widescreen display format available on the panel slots. The selection of the synchronization signal for the encoder 227 is made by the switch SW5, either the C-SYNC-MN gate array signal 300 or the C SYNC AUX circuit 301 for picture-in-picture generation. SW6 then selects between Y_M and C_SYNC_AUX as the sync signals for the widescreen panel output.

The individual parts of the horizontal synchronization circuit are shown in more detail in FIG. The phase comparator 228 is part of a phase lock loop comprising a low passage 230, a voltage-controlled oscillator 232, a divider 234, and a capacitor 236. The voltage-controlled oscillator 232 operates at a 32f _H frequency generated by a ceramic resistor 238 or similar device. The output 32f _{H of the} REF of the resonator 238 is the input of the converter 40 to convert 1f _H to 2f _H. The output of the voltage-controlled oscillator 232 is divided by 32 to form the second input signal at an appropriate frequency for the phase comparator 228. The output of divider 234 is the timing signal REF _H ha passed to the processor 30 and to a wide screen converter 40 for converting the FF _H to 2f _H. The timing signals 32f _H REF and 1f _H REF are fed to a splitter 400 where they are divided by 16. The output 2f _H is then fed to a pulse width modulation circuit 402. The control of the splitter 400 by the 1F _H REF signal provides synchronization of the splitter operation with the input phase locked loop for the input of the video signals. The circuit 402 for modulating the pulse width ensuring an appropriate width of the 2f _H pulse signal REF at the correct operation of the phase comparator 404, for example, the type CA1391, which forms part of the second phase locked feedback loop, further comprising a low pass filter 406 and VCO 408 to the frequency 2 f _H. The voltage-controlled oscillator 408 generates an internal timing signal at a frequency of 2f _H , used to drive the sequentially spaced display. Another input signal to the phase comparator 404 is the feedback pulses of the mapping circuit 50 or the corresponding timing signal. The use of a second phase locked-loop feedback loop comprising a phase comparator 404 ensures that each decay period given by 2f _H is symmetrical within each period 1f _{H of the} input signal. Otherwise, the display could have a grid break, for example one in which one half of the image lines is shifted to the right and the other half of the image lines is shifted to the left.

A block diagram of the interleaved image conversion circuit 900 for the progressive scan image is shown in FIG. The circuit 900 may be embodied as an integrated circuit and perform all the signal processing functions necessary to convert the video signals with the interleaved components into a progressive non-interlaced format. In addition, for signals where necessary, circuit 900 performs noise attenuation within an adjustable range. The circuit shown may be used for the Y, U, and V signal components in conjunction with an integrated circuit RAM image memory 902, such as the HM53051 P type.

The color components U_C and V_C of the signal are internally forced to one logic zero by one pulse delay. The analog multiplexing circuit 908, coupled to the outputs of the keying circuits 904 and 906, alternately samples each of the color components at a frequency of 2 MHz. These samples are then converted to an 8-bit digital signal by a fast analog-to-digital converter 910 operating at a frequency of 4 MHz. The samples further pass the noise damping circuit 912 to the acceleration memory 914. This memory stores only the active portion of each incoming image line of 53 microseconds, so that only 106 samples of each color component are stored therein. Memory content is read at a rate that is twice the write speed, creating two identical lines of color information. The signal is set to zero by the blanking circuit 916 during an interval when no samples are available at the memory output. The two color components are then separated in the demultiplexer circuit 918 and converted into an analogue shape by means of two digital-to-analog converters 920 and 922. The reference base for the digital-to-analog converters 920 and 922 is adjustable via a serial bus connected to the control circuit 924

This can be used to adjust the color saturation if necessary.

The luminance signal Y_C is forced internally to the level that can be adjusted via the serial control bus during the pulse back delay 926. This signal changes from an 8-bit digital format using a fast analog-to-digital converter 928 operating at a frequency of 16 MHz. Then this signal passes through circuit 930, which can be used to automatically adjust the black level if necessary. The brightness is filtered by the low pass filter 932, the characteristic of which is given by the following relation:

H (z) = (1 + z ') ² (L + Z ^{2) 2/16}

This filtered signal is then additionally sampled in circuit 934 at 4 MHz. The additional sampled signal is interpolated by the interpolator 936 back to a 16 MHz frequency using the same low pass filter characteristic and subtracted from the delayed version of the original luminance signal at summation point 938 to produce a signal containing only high frequency luminance components. The high-frequency luminance signal then passes through the non-linear deadband 940 circuit in which low-amplitude noises are removed. The breakpoints of the non-linear characteristic can be set by the serial control bus.

The additional sampled low frequency signal passes through the recursive circuit 942 for noise attenuation and is then interpolated by the interpolator 944 back to a 16 MHz frequency, and then added to the noise-free high frequency signal at summation point 946. The luminance signal is then converted to a sequential or interleaved format by the accelerator memory 948. The memory stores only 53 milliseconds of the signal, which corresponds to 848 samples. The content of this luminance memory is read twice for each incoming image line. Further, the smaller acceleration memory 950 includes information representing the difference between the interpolated luminance signals for the intermediate row and the incoming luminance signal. The smaller accelerator memory 950 contains only low frequency information about 212 samples. When the luminance signal acceleration memory 948 is read for the first time, the difference signal from the second acceleration memory 950 is interpolated to full intensity by the interpolator 952 and added to the luminance signal at summation point 970. This produces a signal having low-frequency components corresponding to the interpolated luminance signal and high-frequency components corresponding to the incoming luminance signal. When the content of the memory 948 is read a second time, the difference signal is not added. The output is then a double speed signal relative to the input.

Circuit blanking 954 is inserted during an interval when no data from the acceleration memories is available. The level of this interleaved blackout is adjustable by the chassis microprocessor using a serial control bus. Three signals are required: DATA, CLOCK and ENABLE. The accelerated digital signals are converted into an analogue form by the digital-to-analog converter 956. The reference base for the converter is adjustable via the control bus.

Line interpolation of low frequency luminance information is performed completely at a reduced sampling rate (4 MHz) using motion adaptive processing. The 1 Mbit RAM external video memory 902, used as a frame memory, stores two fields of an eight-bit low-frequency luminance signal and one field of a tribit motion signal. The connection to the RAM image 302 is made by the frame memory interface 964. Each field stored in the memory represents a maximum of 256 active image lines, each containing 212 active samples. As the low-noise low-noise luminance signal passes through the 958 lf _H delay circuit, spatial interpolation (used in motion areas) is generated, and for this the delayed and non-delayed signals are averaged in circuit 960. The 958 lf _H delay output is also stored in frame memory 902 One field without one half line later, this output is treated as a field delayed signal. This generates a time-interpolated signal for the stationary areas.

The field delayed signal is again stored in frame memory 982 and recalled after another field, reduced by one-half of the line. The result is a net delay of one frame. The frame delay signal is then compared to a sample-by-sample non-delayed signal in the motion detector 962. Here a tribite motion signal is generated representing eight different motion levels. The motion signal is also stored in the frame memory 902, from which it is retrieved by one field, enlarged by one half line, later.

The delayed field motion is compared to the non-delayed motion, and a signal representing a higher level of motion is made in circuit 978. This motion signal is used to control the soft switch or fader 966, which selects between spatially interpolated and temporally interpolated signals in eight different gray gradations.

The un-delayed low-frequency luminance signal at subtraction point 968 is subtracted from the output of the weir 966, producing a signal representing the difference between the interpolated and the incoming low-frequency luminance signal. The difference signal is then stored in a separate acceleration memory 950 as described.

The noise attenuation circuit 942 may be constructed as shown in the block diagram of FIG. 21. The input signal at subtraction point 980 is subtracted from the output signal delayed by the delay circuit 986. If the delay value is selected correctly, the input of most signals is nearly the same as the delayed output and the difference is small. This difference then passes through constraint 382, without limitation (if it does not exercise constraint, the limiter has a gain equal to 7/8). When adding the output of the restrictor 982 to the circuit input at the summing point 984, most of the input signal is suppressed, being replaced by a delayed output signal. This suppresses small changes, especially noise. If the input is significantly different from the delayed output, a restriction is applied. The resulting output is then almost equal to the input. The threshold at which the limitation occurs is adjustable by means of a serial control bus, whereby the noise attenuation rate can be varied from zero (zero threshold) to any desired value.

For noise attenuation of the low-frequency luminance signal, the delay in the circuit described is equal to one frame time. Thus, the noise of the still images is attenuated by the temporary lowpass filter.

The noise attenuation circuit is a cascade consisting of two of these circuits, one of which has a delay equal to one sampling signal (0.5 microseconds) and the other has a delay equal to the time corresponding to one raster line (64 microseconds). The first circuit filters the noise in the horizontal direction, while the second circuit performs the vertical filtration.

The circuit 900 may include a converter 40 for converting 1f _H to 2f _H , which is shown in more detail in FIG. 27. The reference numerals used in FIG. 27 are therefore also shown in FIG. 20, in the lower left corner. The timing signals used in the circuit are derived from an oscillator 238 which operates at a 32 MHz frequency and is synchronized by a phase lock with 1024 times the horizontal deflection frequency of the display unit. These signals are complemented by a deflection circuit return signal to input 2f _H. The middle frequency of the oscillator 238 is controlled by the external LC-circuit 974, while the external loop RC-filter 406 controls the phase locked loop characteristic. Phase of internal timing signals (terminal gates, blackout, etc.) can be adjusted relative to input 2f _H via serial bus.

Input 1f _H must also detect which of the pulses at 2f _H appear at the beginning of the incoming row and which in the middle of the incoming row.

The vertical pulse input, e.g., f in _m , is used to detect the beginning of the field so that the correct lines are stored in the frame memory. The number of rows that elapses between the vertical pulse face and the start of memory operation is adjustable via the bus command. A 2f _H internal circuitry for generating a horizontal deflection assembly has been described. Phasing of output 2f _H relative to input 1f _H can be adjusted using the serial bus.

The mapping circuit 50, formed as a deflection circuit, is shown in more detail in FIG. The circuit 500 is designed to adjust the vertical dimension of the raster, in accordance with the necessary size of the vertical overshoot needed to create different display formats. As shown schematically, the current source 502 generates a constant amount of current IfRAMP that is provided by the vertical flip capacitor 504. Transistor 506 is connected in parallel to the capacitor 504 and periodically discharges it when the vertical reset signal sounds. If no adjustment is made, the maximum available vertical grid size is generated by the I _RAMP stream. This may correspond to the amount of vertical overshoot needed to fill the wide-screen display unit with an extended signal source having a 4x3 aspect ratio aspect ratio, as shown in FIG. 1 (a). If a smaller vertical grid size is desired, the adjustable current source 508 will take a variable amount of current 1 _ADJ from the current Iramp. so the vertical flip capacitor 504 charges slower and at a lower peak value. The adjustable variable current source 508 operates in response to a vertical dimension control signal, e.g., in an analog form, formed by the vertical dimension control circuit 1030 shown in FIG. 49. The vertical adjustment circuit 500 is independent of the manual vertical adjustment 510, which may be a potentiometer or an adjustment knob on the rear panel. In both cases, an excitation current of the appropriate size is guided into the deflection coil or coils 512. The horizontal deflection is equipped with a phase adjustment circuit 518, an east-west correction circuit 514, a 2f _H phase-feedback loop loop 520 and a horizontal output circuit 516.

The second color selector 60 is shown in more detail in FIG. 25. Selection of the signal to be finally displayed is made between the output of the converter 40 to convert 1f _H to 2f _H and the input of the external color signal. For the purpose of the described wide-screen color television according to the invention, the external input of the color signal is assumed to be a source of a progressively deinterleaved video signal with a widescreen display format. The external color signals and the complete blanking signal from the video signal input circuit 20 are inputs of the converter 610 for converting the RGB signal to the YUV signal, which is shown in more detail in FIG. 26. Detailed external synchronization signal frequency of the LF _H outside the input color signal separator 600 of the external synchronization signal. The vertical synchronization signal is selected by switch 608. The horizontal synchronization signal is selected by switch 604. The video signal is selected by switch 606. Each of the switches 604, 606 and 608 is controlled by an internal / external control signal generated by the microprocessor in the control circuit circuit 340 function. Widescreen image. The choice of internal or external video sources is made by the user. However, if the user accidentally selects an external color signal source and is not connected or turned on, or if the external source fails, the vertical screen will collapse and the screen or screens may be seriously damaged. Therefore, the presence of an external synchronization signal is controlled by an external synchronization detector 602. If the required signal is not present, each of the switches 604, 606 and 608 is sent a blocking control signal to prevent the selection of an external color signal source. The RGB to YUV signal converter 610 also receives control signals from the microprocessor as a widescreen mapping circuit control circuit 340.

The converter 610 is shown in more detail in FIG. 26. The color signal synchronization components are separated by respective circuits 612, 614 and 616. The signals are further algebraically combined in summation circuits 618, 620 and 622 to produce RY (U), BY (V) and Y signals. Multipliers 628 and 634 the bit rate changes the phase of the RY and BY signals so that the effective color of the signals changes even if the phase is not quite suitable for the RY and BY phasers. Multipliers 640 and 638 then similarly change the phase to alternate the effective color tone regardless of the bias of the R-Y and B-Y signals from the correct phase angle. The color and tone control signals may be generated by a microprocessor in the function of the widescreen mapping circuit control circuit 340 controlled by the TV microprocessor 216. This allows easy control of the color and tone color characteristics of the external color signal without the need for additional circuitry or external adjustment itself. color signal source.

For a Y signal, the difference is 7.5 IRE relative to a well-defined black level. Compensation is performed by a correction blanking circuit 648, which inserts a 7.5 IRE offset. The KEY signal is a control signal generated in the front delay of the video signal behind the rear of the vertical sync signal and before the beginning of the active image. The KEY signal determines when to perform keying in circuit 646. The delay circuits 624 and 626 determine the exact phase relationship of the R-Y, B-Y, and Y signals, despite the subsequent change due to the color control and color tone instructions.

An overall block diagram of a widescreen television 11 according to the invention, adapted for operation with line decomposition at the frequency 1f _H , is shown in FIG. 4. Those parts of the television 11 which substantially correspond to their counterparts in the television 10 shown in FIG. 2, the same reference numerals are assigned. Television 11 generally comprises an input circuit 21 for receiving video signals, a TV microprocessor 216, a widescreen image processor 31, a horizontal deflection circuit 52, a vertical deflection circuit 56, a matrix circuit 241, a screen driver 242, a direct observation or projection type screen 244 and a power supply. source converter 70. lf _H to 2f _H and RGB interfaces are not used. Accordingly, measures are provided herein to display an external color signal with a wide screen format at a scanning frequency 1f _H. The grouping of different circuits into functional blocks is made for ease of description and is therefore not intended to limit the relative physical position of these circuits.

The video signal input circuit 21 is adapted to receive a plurality of complete video signals from different sources. The video signals can be selectively switched to display as main and auxiliary video signals. The radio frequency switch 204 has two antenna inputs ΝΤΙΝΤΙ and ANT2. These represent inputs for both external antenna and cable reception. The radio frequency switch 204 determines which of the antenna inputs leads to the first tuner 206 and which to the second tuner 208.

The output of the first tuner 206 is an input of a single-chip circuit 203 which performs a number of functions related to tuning, horizontal and vertical biasing, and video signal control. The particular single-chip circuit shown has the industrial type designation TA8680. The baseband VIDEO OUT video signal produced in the single-chip circuit 203 from the signal supplied from the first tuner 206 is both the input of the video switch 200 and the input of the TV1 of the wide-screen processor 31. The other baseband video inputs to the video signal switch 200 are designated AUX1 and AUX2. These inputs can be used for camcorders, VCRs and similar devices. The output of the video signal switch 200, which is controlled by the TV microprocessor 216, is labeled SWITCHED VIDEO, which is at the same time another input of the widescreen processor 31.

As shown in FIG. 5, the wide picture processor switch SW1 selects the TV1 and SWITCHED VIDEO signals, outputting a SEL COMP OUT video signal to the Y / C input of the decoder 210. The decoder may be an adaptive line comb filter. Another SI video source is also an input of the Y / C decoder 210. The SI source is an SVHS source and consists of separate luminance and color signals. The switch, which may be embodied as part of a decoder 210, in any of the adaptive line comb filters or as a separate switch, responds to the microprocessor 216 TV signals and selects one of the brightness and color signal pairs, designated as Y_M and C_IN outputs. The selected pair of luminance and color signals is then considered the main signal and is processed in the main signal path circuits. The decoder / demodulator arranged in the widescreen processor 301 produces color difference signals U_M and V_M. The signals Y_M, U_M and V_M are then changed to a digital form in the widescreen processor 31 for further processing in the gate array 300.

The second tuner 208, which is functionally defined as part of the widescreen processor 31, generates a baseband video signal TV2. The switch SW2 selects between the signals TV2 and SWITCHED VIDEO as the Y / C inputs of the second decoder 220. The second decoder 220 may be made as an adaptive row comb fdter. Switches SW3 and SW4 make the choice between the luminance and color outputs of the decoder 220, the luminance and color signals of the external video source, designated YEXT / CEXT, and the signals Y_M, C_IN. The Y_EXT / C_EXT signals correspond to the S-VHS input S1. The decoder 220 and the switches SW3 and SW4 can be combined, for example, in adaptive line comb filters. The output of switches SW3 and SW4 is then considered as an auxiliary signal and is further processed in the auxiliary signal path circuits. The selected brightness output is indicated by Y_A. The selected color signal is converted to color difference signals U_A and V_A. The signals Y_A, U A and V A are then changed to a digital form for further processing. The arrangement of the devices for switching the video signal sources into the main and auxiliary signal paths provides maximum flexibility in making the choice of the costs for different parts of different display formats.

The widescreen processor 31 includes a picture-in-picture processor 320 that processes the video auxiliary signal. The term picture-in-picture is sometimes abbreviated as Pl1 or pix-in-pix. The gate array 300 combines master and auxiliary video signal data into a variety of display formats, some of which are shown in FIG. l (b) to l (c). The image-in-picture processor 320 and the gate array 300 are controlled by a widescreen microprocessor in function of the control circuit 340 of the mapping circuit. The microprocessor in the function of the mapping circuit control circuit 340 is in communication with the TV microprocessor 216 via a serial bus. The serial bus contains four signal lines for data, clock pulses, opening signals and setting signals. The widescreen processor 31 further generates a complete vertical shading and adjustment signal in the form of a three-level sandcastle signal. Alternatively, the vertical blanking and adjustment signals can also be generated as separate signals. The complete blanking signal is then routed through the input section for receiving video signals to the RGB interface.

The horizontal and vertical sync component of the main signal is formed in the sync signal separator 286 that forms part of the demodulator 288 arranged in the widescreen processor 31. The horizontal sync component is the input of the phase locked feedback loop 290 at the frequency 1f _H. The horizontal and vertical sync signals of the auxiliary video signal are generated in the sync signal separator 250 arranged in the wide picture processor 31. The horizontal deflection circuit 52 operates in conjunction with the single-chip circuit and responds to the east / west adjustments and the microprocessor horizontal phase control signals as a widescreen mapping circuit control circuit 340. The vertical deflection circuit 56 is controlled by the vertical dimension control circuit 54. The vertical dimension control circuit 54 responds to the vertical dimension control signals transmitted by the microprocessor in function of the widescreen mapping circuit control circuit 340 and operates in a manner similar to the vertical dimension control circuit for the 2f _H frequency of the television described.

The widescreen processor 31 is shown in more detail in FIG. 5. The main components of the widescreen processor 31 are the gate array 300, the picture-in-picture circuit 301, the analog-to-digital and digital-to-analog converters, the second tuner 208, the microprocessor as widescreen mapping circuit control circuit 340 and widescreen output encoder 227. . Further details of the widescreen processor 31 that are common to both 1f _H and 2f _H , such as an image-in-picture circuit, are shown in FIG. 6. The PIP 320 that forms a substantial portion of the PIP 301 is shown in more detail in FIG. 7. The gate array 300 is shown in more detail in FIG. 8. A series of components shown in FIG. 3 and forming parts of the main and auxiliary signal processing paths have already been described in detail. A number of other components, such as the second tuner 208, the microprocessor in function of the widescreen mapping circuit control circuit 340, the interface outputs, the analog-to-digital and analog-to-analog converters, the gate array 300, the image-in-picture circuit 301 and the phase-lock feedback loop 374 as explained in connection with FIG. 3, so that their detailed description is not repeated.

The main video signal is routed to the widescreen processor 31 in an analogue form, both as Y_M and C_1N signals. The signal C_IN is decoded by the demodulator 288 into color difference signals U_M and V_M. The main signals are then changed from analog to digital by analog-to-digital converters 342 and 346, which are shown in more detail in FIG. 6. The auxiliary image data is also in analog form and in YUV format as signals marked Y_A, U_A and V_A. In the image-in-picture circuit 301, these auxiliary signals are converted to digital form, then compressed and stored in a field the memories to be synchronized with the main signal and then passed to the gate array 300 where they are combined with the main signal to create the selected display format, for example, by row pooling. The operation of the PIP 301 is explained in more detail with reference to FIG. 6. The PIP 301 and / or the gate array 300 may also include means to improve the resolution of the auxiliary data, despite being compressed. The analogue signals, indicated by Y, U, and V, are routed to encoder 227 to produce output signals Y_OUT EXT / C_OUT_EXT in widescreen format, which in this case are inputs of single-circuit 203. The encoder receives only C_SYNC_MN signal from gate array 300. Switch SW5 selects between Y_M and C_SYNC_AUX signals as inputs to analog-to-digital converters. The single-chip circuit 203 generates YUV signals for the RGB matrix circuit 241, which generates RGB signals for the display drivers 242 from the Y_OUT_EXT and COUTEXT signals.

Fig. 6 is a block diagram illustrating further details of the widescreen image processors 30 and 31 common to 1f _H and 2f _H as shown in FIG. 3 and 5. The signals Y_A, U_A and V_A are inputs of the picture-in-picture processor 320, which may include a resolution control circuit 370. The widescreen television of the invention may compress and stretch the image. These particular effects represented by the various associated display formats shown in FIG. 1, are generated by an image-in-picture processor 320 which can receive, for resolution, the processed data signals Y_RP, U_RP, and V_RP from the resolution control circuit 370. Distinguishing processing may not always be used, but only during the selected display formats. The picture-in-picture processor 320 is shown in more detail in FIG. 7. The main components of the processor 320 are the analog-to-digital converter section 322, the input section 324, the quick-action and pick-up section 326, the timing and control section 328, and the digital-analogue section 330. The timing and control section 328 is shown in more detail in FIG. 14th

The picture-in-picture processor 320 may be constructed as an improved variation of the CPIP base chip. It allows a number of special functions or effects, the following of which are illustrative. The basic special effect is a large image, part of which is covered by a smaller image than shown in FIG. l (c). Large and small images can be created from the same video signal or different video signals, and can be interchanged or moved. Generally, the audio signal is always switched to match the large picture. The small image can be moved to any position on the screen or it can advance through a number of predetermined positions. The zoom function allows to enlarge and reduce the dimensions of a small image, for example to any series of predetermined sizes. At some point, for example, the format shown in FIG. l (d), have a small and large image of substantially the same size.

In single-image mode, for example, in the formats shown in FIG. l (b), 1 (e) or l (f), the user may zoom in on a single image content, for example in steps from 1.0: 1 to 5.0: 1, while in zoom mode, the user may search or pan the image content, while the shaded image can move through different areas of the image. In either case, a small image or a large image or a zoomed image may be displayed as a still image (still image format). This function also allows a stroboscopic format in which the last nine frames of the image can be repeated on the screen. The frame rate can be varied from thirty frames per second to zero frames per second.

The picture-in-picture processor 320 used in the widescreen television of the invention is somewhat different from the basic embodiment of the CPIP type chip. If a CPIP base chip was used on a 16x9 TV without using an image acceleration circuit, the embedded images would have a distorted aspect ratio due to 4/3 times the horizontal expansion resulting from the wider screen degradation.

The objects in this image would be horizontally stretched. If an external accelerator circuit were used, the aspect ratio distortion would not occur, but the image would not fill the screen.

Current image-in-picture processors, which are based on a basic CPIP-type chip and used in conventional television sets, have certain undesirable characteristics. The incoming video signal is sampled by clock pulses with frequency 640F _H, which are coupled to the horizontal synchronization signal of the main video source. In other words, the data stored in the RAM image memory, merged with the CPIP chip, is not sampled orthogonally to the source of the incoming auxiliary signal. This is a fundamental limitation of field synchronization using the basic CPIP chip design. The unorthogonal nature of the input sampling rate results in parallelogram distortion of the sampled data. The limitation is a consequence of the RAM image used with the CPIP chip, which must use the same clock pulse to write and retrieve data. When data from an image RAM, such as a RAM image 350, is displayed, the parallelogram distortions occur as random jitter along the vertical edges of the image and are generally considered to be completely unacceptable.

The picture-in-picture processor 320 of the present invention, different from the basic embodiment of the CPIP chip, is adapted to asymmetrically compress the image data in one of a number of selectable display modes. In this operating mode, images are compressed 4: 1 horizontally and 3: 1 vertically. This asymmetric compression mode creates images with

2806 distorted aspect ratios that are stored in the RAM image. Objects in the images are compressed horizontally. However, these images are normally removed from memory for subsequent display on a 16x9 display format screen, for example by channel scanning. The image fills the screen and its aspect ratio is not distorted. Asymmetric compression according to this aspect of the invention allows the creation of special display formats on a 16x9 screen without the need for an external set of acceleration circuits.

Fig. 14 is a block diagram of a timing and control circuit 328 of an image-in-picture processor 320, for example, a modified version of the described type of CPIP chip. The timing and control section 328 includes a decimation circuit 328C that performs asymmetric compression as one of a number of selectable display modes. Auxiliary images of different sizes can be performed by other display modes. Each of the horizontal and vertical decimation circuits includes a counter that is programmed for a compression coefficient selected from a value table controlled by a widescreen microprocessor in function of the control circuit 340 of the mapping circuit. The value range can be 1: 1, 2: 1.3: 1, etc. Compression coefficients can be symmetrical or asymmetrical, depending on the table layout. The control of the compression ratios can also be done by fully programmable microprocessor-controlled universal decimation circuits as a widescreen mapping circuit control circuit 340. The decimation circuit 328C is shown in more detail in FIG. 15 to 18.

Fig. 15 is a block diagram of a circuit for performing horizontal compression. The circuit includes a decimation circuit formed by a counter 850 denoted by MOD_N_CNTR1. The numeric value at input N is the horizontal coefficient N, denoted by HOR N FACTOR. The horizontal coefficient N refers to the extent to which the size of the picture represented by the picture data of the auxiliary signal will be reduced to be displayed as picture in picture or as picture off picture. At the same time, this coefficient is a measure of the speed at which the pixels in the line are sampled. The numeric input for the input value is set to "0". The asynchronous output (RCO) is a horizontal line sampling opening signal. Fig. 16 is a block diagram of a circuit for performing vertical compression. The circuit comprises a decimation circuit formed by a counter 858 denoted MOD_N_CNTR2. The numeric value at input N is the vertical coefficient N, denoted by VERTNFACTOR. The vertical coefficient N also relates to the extent to which the size of the picture represented by the picture data of the auxiliary signal to be displayed as picture in picture or picture out of picture will be reduced, but in this case it is a measure of how many lines are selected for sub-sampling. The numeric input for the input value is determined by a numerical calculation based on the vertical coefficient N. "2" is added to the vertical coefficient N, the sum is then divided by two and the division result is keyed with U / L_FIELD_TYPE to distinguish between the upper and lower fields. The counter 858 outputs a vertical line sample opening signal.

The horizontal and vertical coefficients N are formed by the circuit 859 shown in FIG. 17. The input is an N_FACTOR value ranging from 0 to 7. Each N value corresponds to a pair of horizontal and vertical compression ratios as shown in the table in FIG. 18. N_FACTOR values are generated by the microprocessor in function of the widescreen mapping circuit control circuit 340. Circuit 859 includes multiplexing circuitry 862 and 864 and circuit 860 for comparison to a value of "6". For each N_FACTOR value other than "6", the horizontal and vertical compression ratios are symmetrical, due to the zero inputs of the multiplexing circuits. If N_FACTOR is "6", the multiplexer unit inputs are keyed as outputs. The result of these inputs is asymmetric compression, 4: 1 in the horizontal direction and 3: 1 in the vertical direction.

Counters in decimation circuits are represented as integer decimators. However, processing may not be limited to compressing images in integer increments, provided that the horizontal compression factor is 4/3 times the vertical compression factor. Also, asymmetric compression is not limited to a widescreen device with a 16x9 display format. If the aspect ratio of the display format is, for example, 2: 1, the horizontal compression coefficient would be 3/2 times the vertical compression coefficient.

The control of the compression ratios can also be performed by fully programmable microprocessor-controlled universal decimation circuits as a widescreen mapping circuit control circuit 340, as shown in FIG. 19 (a) and 19 (b). The horizontal compression coefficients are formed by the circuit shown in FIG. 19i (a), which consists of a summation point 866, a field 868 of eight OR type gates and a screensaver 870. Each 8-bit bit of the gate field output 868 has a logical unit status if the H_RESET signal is input: equal to the input of the field that is the output of the summation point 866. The vertical compression coefficients are generated by the circuit of FIG. 19 (b), which consists of a summing point 872, multiplexer 874 and screen 876. In each circuit, the transmission input summing point C connected to a constant voltage to a logic level 1. In each of the circuit is the output of summing point CC ¹ the respective sample opening signal. In the circuit of FIG. 19 (b), the multiplex circuit unit input is coupled to ground to obtain a constant level 0 logic signal. The horizontal and vertical compression coefficients may be supplied from the microprocessor as a widescreen mapping circuit control circuit 340.

In full-screen picture-in-picture modes, the picture-in-picture processor receives, in conjunction with the freely oscillating oscillator 348, a decoder signal, such as an adaptive line comb filter, as the Y / C input, decodes this signal into Y, U, V color components. and vertical sync pulses. These signals are processed in the picture-in-picture processor for various full-screen modes, such as zoom, still picture, or channel deinterleave. For example, during channel degradation mode, the horizontal and vertical sync components supplied from the video signal input section have a lot of discontinuity because the sampled signals (different channels) have different sync pulses and are switched on at seemingly random moments. Therefore, the sampling clock signal (and the clock for reading and writing in the image RAM) is determined by a freely oscillating oscillator. For still image or zoom modes, the sample clock is coupled to the horizontal synchronization component of the incoming video signal, which in these special cases is the same as the clock frequency of the display.

As again shown in FIG. 6, the outputs Y, U, V and C_SYNC (synchronization mixture) of the PIP 320 in analog form can be re-encoded into Y / C components by a coding circuit 366 that is in conjunction with an oscillator 380 with a frequency

SK 280556 Β6

3.58 MHz. This signal, designated Y / CPIPENC, may be connected to a Y / C switch (not shown) which allows the Y / C components of the main signal to be replaced by recoded Y / C components from the coding circuit. From this point on, the picture-in-picture Y, U, V signals and the synchronization signals are the basis for both horizontal and vertical timing in the rest of the apparatus. This operating mode is suitable for performing an in-picture zoom mode based on the operation of the interpolator and the operator's memory in the order of arrival arranged in the main signal path circuits.

In multi-channel mode, as shown in FIG. 1 (i), twelve small images of the twelve channels may be simultaneously displayed according to a predetermined decomposition order. The PIP 320 has an internal clock source, controlled by an 3.58 MHz oscillator 348. The incoming auxiliary signal is changed from analog to digital, and, depending on the special effect selected, it is loaded into the RAM image type 350. In the prior art, the compiled special effect changes in the image-in-picture processor back into an analog form and then combined with the main signal data. However, in the widescreen television described, partly due to the limitation of the number of executable different clock rates, the auxiliary data is the direct output of the RAM image 350 without being further processed by the PIP 320. However, minimizing the number of clock signals advantageously reduces the interference of the audio signal that occurs in television circuits.

As further shown in FIG. 7, the PIP 320 includes an analog-to-digital converter section 322, an input section 324, a quick-change and bus section 326, a timing and control section 328, and a digital-analogue section 330. The picture-in-picture processor 320 generally digitizes the video signal to the luminance signal Y and the color difference signals U, V, while additionally sampling the results and storing them in a 1 megabit RAM image memory 350 as explained. The RAM image memory 350 associated with the processor 320 has a capacity of one megabit, which is not sufficient to store the entire field of image data in eight-bit samples. Increasing memory capacity is costly and may require a more complex set of control circuits. A smaller number of bits per sample in the auxiliary channel, on the other hand, represents a reduction in quantization resolution or bandwidth relative to the main signal, which is processed exclusively in eight-bit samples. This effective bandwidth reduction is usually not a problem when the additional display image is relatively small, but can cause problems if the additional image is larger, for example of the same size as the main image. The resolution control circuit may optionally execute one or more schemes to improve the quantization resolution or effective bandwidth of the auxiliary image data. A number of data reduction and recovery schemes have been developed including, for example, compressing pairs of pixels, adding and subtracting coded signals. The encoded signal adding circuit would be functionally arranged behind the RAM image memory 350, for example, in an auxiliary signal path in the gate array 300, as explained in more detail below. In addition, different sequences of encoded signals including different bit counts and different methods of compressing pairs of pixels at different bit counts are contemplated. One of these data reduction and recovery schemes may then be selected by a microprocessor in the function of the widescreen mapping circuit control circuit 340 to achieve maximum display resolution for each individual kind of display format.

The resolution control circuits are explained in more detail in connection with FIG. 56 to 70.

The luminance and color difference signals are stored in 6-bit components Y, U, V at a ratio of 8: 1: 1. In other words, each component is quantized into six-bit samples, and for each pair of color difference samples there are eight luminance samples. The processor 320 to form an image in the image is operating in a mode in which incoming video data is sampled at a clock frequency 640F _H, which in this case coupled "with the synchronizing component of the incoming video signal. In this mode, the data stored in the RAM image is sampled orthogonally. If the data from the picture memory 350 of the image-in-picture processor 320 is read, this is done using the same clock frequency 640f _H coupled to the incoming video auxiliary signal. Although this data is sampled and stored orthogonally and can be read orthogonally, it cannot be orthogonally displayed directly from the RAM 350 due to the asynchronous nature of the main and auxiliary video signal sources. Sources of main and auxiliary video signals could be considered synchronous only if they displayed signals from the same video source.

Further processing is required to synchronize the auxiliary channel, which is the data output of the RAM 350, with the main channel. Again, as shown in FIG. 6, two 4-bit screensavers 352A and 352B are used to recreate the eight-bit data blocks by combining the four-bit video RAM output 350. Four-bit screensavers also reduce the frequency of data clock pulses from 1280f _H to 640f _H.

The display unit and the deflection assembly are generally synchronized with the main video signal. The main video signal must be accelerated to fill the wide screen as explained.

The auxiliary signal shall be vertically synchronized with the first video signal and the display unit. The auxiliary video signal may be delayed in the field memory by a fraction of the field period, and then expanded in the row memory. Briefly, the synchronization of the auxiliary image data with the main image data is performed using the RAM type image memory 350 as a field memory and the line memory 354 with an inbound order in which the signal is expanded. The auxiliary signal path interpolator 359 may correct acceleration in memory 354. The size of the handler memory 354 in the order of arrival is 2048 x 8. Problems that may occur when synchronizing the master and slave signals are the collisions of the read and write pointers in the operator memory 354 in order of arrival in the auxiliary signal path and maintaining interleaving integrity. A field synchronization system that prevents such read and write pointer conflicts and that maintains the integrity of the field is explained by FIG. 28 to 36.

The gate array 300 is common to both the widescreen processor, i.e. both the processor 30 and the processor 31. The main signal path in the image processor 304, the auxiliary signal path in the image processor 306, and the path of the output video signal selector 312 are shown. The gate array 300 also includes a timing and synchronization circuit 320 and a widescreen microprocessor decoder 310. The data and address outputs of the widescreen microprocessor decoder 310, referred to as WSP DATA, are routed to each of the main circuits and paths mentioned above as well as to an image-in-picture processor 320 and a resolution control circuit 370. Obviously, whether or not certain circuits are defined as being part of the gate array, given largely by the need to facilitate explanation of the various embodiments of the invention.

The gate array 300 is configured to stretch, compress, and trim the image data of the main image channel and, if necessary, to produce various display formats. The luminance component Y_MN is stored in the handler memory 356 in the order of arrival, at a time depending on the type of interpolation of the luminance component. The combined U / V_MN color constituents are stored in the memory 358 with the operator in the arrival order. The luminance and chrominance components of the Y PIP, UPIP, and V PIP auxiliary signals are generated by the demultiplexer circuit 355. The luminance component is subjected to the discriminating processing in circuit 357 (if necessary) and then expanded as needed by interpolator 359, outputting the Y_AUX signal.

In some cases, the auxiliary picture is as large as that of the main signal, such as shown in FIG. l (d). The capacity limitation of the RAM type of image memory 350 associated with the PIP 320 may not provide a sufficient number of data points or pixels to fill such a large display area. In these circumstances, the resolution control circuit 357 may be used to recover the pixels of the auxiliary video signal that replace the pixels lost when the data is compressed or reduced. The resolution processing may correspond to the processing performed by the circuit 370 shown in FIG. For example, circuit 370 may be a coded signal acquisition circuit and circuit 357 may be a coded signal reading circuit. The auxiliary signal interpolation may be performed in the auxiliary signal path in the image processor 306 and is shown in more detail in FIG. 12. The picture-in-picture circuit 301 shown in FIG. 6, controls a field memory for the six-bit components Y, U, V, stored in an 8: 1: 1 ratio, which is an image memory of 350 RAM. The image RAM 350 always holds two image data fields in a plurality of memory locations. Each memory location stores eight bits of data. One six-bit Y pattern (luminance), sampled at 640f _H , and 2 additional bits are stored at each eight-bit location. These two additional bits contain either fast switching data (FSWDAT) or a portion of sample U or V (sampled at 80f _H ). The FSW_DAT values indicate the type of field that was written to the RAM image as follows: FSW_DAT = 0: no image, FSW_DAT = 1: upper (odd) field, and FSW DAT = 2: lower (even) field).

The fields in the RAM image occupy spatial positions whose boundaries are defined by horizontal and vertical addresses, as shown in the memory location scheme of FIG. 37. The boundary at these addresses is defined by changing the quick switch data from the no picture position to the active field position and vice versa. These fast switching data transitions define the perimeter of the picture embedded in the picture, also referred to as the clipboard or the picture-in-picture overlay. It will be understood that the aspect ratio of the display of objects in the image embedded in the image may be controlled independently of the aspect ratio of the clipboard format or image overlay, e.g. 4x3 or 16x9. The position of the embedded image on the screen shall be determined for each main signal field by the starting address of the image RAM read pointer at the start of the scan. Since two RAM data fields are stored in the RAM image and the entire RAM image 350 is read during the display period, both fields are read during the display decomposition. The picture-in-picture circuitry 301 determines which field will be read from the display memory, using fast switching data and a read pointer start position. It may seem logical that if the display unit that is coupled to the main video source just displayed the upper field of the main image, then that portion of the RAM image corresponding to the upper field of the auxiliary image would be read, followed by conversion to analog data and display.

This would be feasible for about half of all possible phase relationships between the main and auxiliary video signal sources. However, problems arise because reading RAM is always faster than writing pictures compressed into RAM in picture-in-picture mode. The memory reader may override the writer if the same type of field is read and written at the same time. The consequence would be a five per cent probability of tearing motion at some point in the small picture. The image-in-picture circuit therefore always reads a field of the opposite type to that currently being written in order to overcome the problem of movement tearing. If the type of frame currently being read is the opposite of the type of field currently being displayed, then the inverted field stored in RAM is inverted by deleting its upper row when it is read from memory. As a result, a small image maintains proper interleaving without tearing the movement. The end result of the field sync is that the CPIP produces a signal called PIP_FSW. This is an overlay signal that the PIP produces an analog switch that switches the Y / C signals of the main and sub channel (brightness and modulated color image information).

The auxiliary image input data is sampled at 640f _H and stored in a RAM image 350. Auxiliary data read from this memory is labeled VB AM_OUT. The picture-in-picture circuitry 301 is also able to reduce the auxiliary picture by integer coefficients equal in both horizontal and vertical directions as well as asymmetrically. As further shown in FIG. 12, the auxiliary channel data is cached and synchronized with the main channel digital video signal by four-bit savers 352A and 352B, the on-access auxiliary memory 354, the timing circuit 369, and the synchronization circuit 371. The VRAM_OUT data is sorted by the demultiplex 355 ijas), U, V (color components) and FSW-DAT (fast switching data). The FSW-DAT indicates which type of field has been written to the RAM image. The PIP-FSW signal is received directly from the PIP circuit and fed to the output control circuit. Here, encoding is made about which of the fields read from the RAM to be displayed. Finally, the data of the auxiliary video channel components for output for display is selected by the three multiplexing circuits 315, 317 and 319 shown in FIG. Instead of overlaying the small picture in the picture using an analog switch in the composite or Y / C coupler circuit, as in the CPIP chip, the widescreen microprocessor performs the function of the PIP control circuit 340 digitally. However, as described below, the PIP-FXW control signal is used to control the digital overlap together with the FSW-DAT signal.

The sub-channel is sampled at 640 f _H while the main channel is sampled at 1024 f _H. The in-service memory 354 is 204 8 x 8 and changes data from the sub-channel sampling frequency to the main channel clock frequency. In this process, the video signal is subjected to an 8/5 (1024/640) compression, which is more than the 4/3 compression required to properly display the sub-channel signal. Therefore, the auxiliary channel must be expanded by an interpolator to correctly display a small 4x3 image. The required range of expansion by the interpolator is 5/6. The expansion coefficient X is determined as follows:

X- (640/1024) x (4/3) -5 / 6

Thus, a small picture can be correctly displayed in 4x3 format by setting the interpolator 359 to perform a 5/6 stretch (5 input samples, 6 output samples) regardless of how it is scaled down by the image-in-picture processor.

The PIP / FSW data does not provide sufficient interpretation of which field of the image RAM associated with the CPIP type chip should be displayed because the PIP data is horizontally rasterized to maintain the correct PIP ratio. Although the correct interleaving would be maintained with a small picture in the picture, the overlapping region of the picture in the picture would generally have an incorrect horizontal dimension. The only case that the size of the PIP area would be correct would occur when stretched at a ratio of 518 using interpolator 359, resulting in a small 16x9 format picture. For all other interpolator 359 settings, the overlap circuit would remain in 16x9 format while the embedded image would change horizontally. The PIPFSW signal contains insufficient information about the correct horizontal dimension of the PIP. The data stored in the picture memory is read before the picture-in-picture circuit completes the synchronization algorithm. Thus, the fast switching data FSW_DAT that is included in the VRAM-OUT data stream from the image RAM is corresponding to the type of field written to the RAM. Although the image component data (Y, U, V) stored in the image RAM is corrected to prevent motion jitter and achieve proper interleaving, the FSWDAT signal is not modified.

In accordance with the solution of the invention, the PIP is the correct size because the FSW DAT information is stretched and interpolated along with the data components Y, U, V. The FSW_DAT signal contains information to correctly determine the dimensions of the overlay area, but does not indicate which the field is the correct field to display. The PIP_FSW and FSW_DAT signals can be used together to solve the problem of maintaining interleaving integrity and the correct overlap size. In normal operation, when a CPIP-type chip is used in 4x3 TVs, the placement of the field in the RAM image is arbitrary. Fields can be aligned vertically or horizontally or not aligned at all. In order to achieve functional compatibility of the widescreen processor, it is necessary that the picture-in-picture positions of the picture are not stored in the memory on the same vertical lines. In other words, the picture-in-picture fields cannot be programmed using the same addresses for the top and bottom fields. From a programming point of view, it is desirable to store the image frames in an image in the image memory 350 RAM vertically aligned as shown in FIG. 37th

The PIP OVL signal controls the output control circuit 321 so that the auxiliary data is displayed when the signal is active, that is, when it has a logical unit level. A block diagram of the PIP_OVL signal generating circuit is shown in FIG. The circuit 680 includes a JK type flip-flop 682 whose output Q is one of the inputs of the multiplexing circuit 688. The output of the multiplexing circuit 688 is the input of the D-flip-flop 684 whose output Q is the second input of the multiplexing 688 and simultaneously The PIP signals FSW and SOL (line start) are respective inputs J and K of flip-flop 682. The non-equivalence circuit 686 has two inputs for the FSW DATO and FSW DAT1 bits of the fast switching data. Values (1, 0) and (0, 1), which are logically exclusive inputs, indicate a valid field as either odd or even. Values of (0, 0) and (1, 1) that are not logically exclusive indicate the absence of valid data. The transition from one of the pairs (0, 1) or (1, 0) to one of the pairs (0, 0) or (1, 1), or vice versa, indicates a boundary delimiting the perimeter or overlay of the picture in the picture. The output of the non-equivalence circuit 686 is the second input of the product gate 690. The third input of the product gate 690 is the RD_EN_AX signal, which is a read enable signal for the slave auxiliary memory 354 in the arrival order. The product gate 690 outputs the PIP_OVL signal. Circuit 680 introduces a one-line delay (one line field delay) from the moment when the PIP FSW becomes active to actually access the overlap area. This is also counted in the image data path since the in-service memory 354 also introduces a one-line field delay for the image data in the image. The picture-in-picture overlay is therefore perfectly aligned with the picture data, although it is delayed by one line of the field against programming in the picture-in-picture circuitry. The RD_EN_AX signal allows the picture-in-picture to be overlaid only if valid auxiliary data has been read from the operator's memory 354 in the arrival order. This is necessary because the data from the memory 354 can be retained even after the reading is finished, which may cause the PIP overlay logic to determine that the overlay is active outside the valid PIP. Enabling picture-in-picture overlay with RD_EN_AX ensures that picture-in-picture data is valid. In accordance with the solution of the invention, the overlay of the small auxiliary image is correctly positioned and sized, regardless of how the auxiliary video signal has been expanded, compressed or interpolated. This is true for small image sources with both 4x3 and 16x9 formats and many other formats.

The color components U_PIP and V PIP are delayed by circuit 367 for a period of time depending on the kind of interpolation of the luminance component at which the U_AUX and V_AUX signals are output. The respective main and auxiliary signal components Y, U and V are combined in respective multiplexing circuits 315, 317 and 319 arranged in the path of the video output selector 312 so that the read enable enable signals 354, 356 and 358 are handled in the arrival order. The multiplexing circuits 315, 317 and 319 are controlled by the multiplexer output control circuit 321. The multiplexer output control circuit 321 is controlled by the clock signal CLK, the line-start SOL signal, the H_COUNT signal, the vertical blanking adjustment signal, and the output of the PIP processor 320 and the widescreen microprocessor in the mapping circuit control circuit 340.

The multiplexed luminance and color components Y_MX, U_MX and V_MX are routed to the respective digital-to-analog converters 360, 362 and 364. Downstream of the digital-to-analog converters, the low-pass filters 361, 363 and 365 shown in FIG. 6. The various functions of the PIP 320, the gate array 300, and the data reduction circuit are controlled by a widescreen microprocessor in the function of the control circuit 340 of the mapping circuit. The widescreen microprocessor in the function of the control circuit 340 of the mapping circuit performs echoes to the signals of the TV microcontroller 216 to which it is connected by a serial bus. The serial bus may be four-wire, as shown, having a data line, clock signals, enable signals, and set signals. A widescreen microprocessor in function of the control circuit 340 of the mapping circuit is coupled to the various circuits of the data field 300 by a decoder 310.

In one case, it is necessary to compress an NTSC video signal in 4x3 format using a 4/3 coefficient to clog the displayed aspect ratio distortion. In the latter case, the image may be stretched to perform horizontal zoom functions, which are usually accompanied by vertical zoom. Horizontal zoom up to 33% can be performed by reducing the compression to less than 4/3. A sample interpolator is used to recalculate the incoming video signal to new pixel positions because the bandwidth of the luminance component of the video signal (for S_VHS format is up to 5.5 MHz) occupies a significant percentage of the frequency which is 1024 f _H for this beacon signal. 8 MHz.

As shown in FIG. 8, the luminance data Y_MN is conveyed by an interpolator 337 arranged in the main signal path in the image processor 304, which recalculates the sample values based on image compression or expansion. The function of the switches or directional selectors 323 and 331 is to reverse the topology path of the main signal in the image processor 304 relative to the relative position of the on-access memory 356 in the order of interpolator 337. These switches therefore select whether interpolator 337 is upstream of memory 356. necessary to compress or whether the memory 356 precedes the interpolator 337, which is required for expansion. The switches 323 and 331 are controlled by a direction control circuit 335 which is controlled by a widescreen microprocessor in function of the control circuit 340 of the mapping circuit. It should be borne in mind that in small-picture modes, the auxiliary video signal is compressed when stored in the 350 RAM image memory, and for practical purposes only stretching is required. Therefore, no similar switches are required in the auxiliary signal path in the image processor 306.

The path of the main signal in the image processor 304 is shown in more detail in FIG. 11 (a). The switch 323 is formed by two multiplexing circuits 325 and 327. The switch 331 is formed by a multiplexing circuit 333. The three multiplexing circuits are controlled by a direction control circuit 335 which is controlled by a widescreen microprocessor in function of the control circuit 340 of the mapping circuit. The horizontal timing and synchronization circuit 339 generates clock signals that control the writing and reading of the in-service memories in the order of arrival, as well as the screens 347 and 351 and the multiplexing circuit 353. The clock CLK and the line start SOL are generated by the timing and synchronization circuit 320. The analog-to-digital converter control circuit 369 is controlled by a Y_MN signal, a widescreen microprocessor in function of the mapping circuit control circuit 340, and the highest valid bit of the UV_MN signal.

The interpolation control circuit 349 generates values (K) of intermediate pixel positions, an interpolation compensation filter weighing (C) and hourly keying information CGY for the luminance component and CGUV for the color component. Hourly key information omits (decimates) or repeats the data stored in the operator's memories in the order of arrival, allowing samples to not be written at some clock pulses (to create a squeeze) or read several times (to create a stretch).

Such compression is shown in FIG. 1 l (b). The line LLMA_RAMP_IN represents the linearly rising luminance data written into the memory with the operator in the order of arrival. The WR_EN_MN_Y signal is active at the LU level, meaning that if the signal is LU level, the data is written to memory. At the same time, every fourth sample is prevented from being recorded. The serration line LUMA_RAMP_OUT represents ascending luminance data as if it were read from the operator's memory in the order of arrival if it were not interpolated first. The average slope of the luminance data characteristic is as shown in FIG. 1 l (b), 33% steeper than the rise in the data being recorded. At the same time, the active reading time required is 33% shorter than the data writing time. This results in a 4/3 compression. The interpolator 337 recalculates the luminance samples written to the memory with the operator in the order of arrival so that the read data characteristic is smooth and not jagged.

The stretching can be performed in exactly the opposite way to the compression. When pressed, the clock enable information is attached to the write enable signal in the form of blocking pulses. As the data is expanded, the clock key information is attached to the read enable signal. Herein, delays are introduced between the data when it is read from the operator's memory 356 in the arrival order, as shown in FIG. 11 (c). The LUMA_RAMP_IN line represents the data before it is written to the memory 356, and the wavy LUMA RAMP OUT line represents the data when it is read from the memory 356. In this case, the interpolator that is downstream of memory 356 recalculates the sampled data from their expansion. The data must be delayed when read from memory 356 and clocked in interpolator 337 in the case of expansion. This is different from compression when data is clocked continuously when passing through interpolator 337. In both cases, ie when compressed and expanded, the clock germination operations can be easily performed synchronously, i.e. using the lead edges of the 1024 f _H system clock pulses.

This luminance interpolation topology has a number of advantages. Hourly keying operations, i. j. omitting and repeating data can be performed synchronously. If the switchable image data topology was not used to interchange the interpolator and memory positions, the read or write clock pulses would have to be doubled for skipping or repeating, meaning that two data points would have to be written or read from the memory in a single clock cycle. The resulting circuitry could not operate synchronously with the system clock pulses, since the write or read frequency would have to be twice as high as the system clock signal. In addition, switchable topology requires only one interpolator and one attendant memory in the order of arrival, which performs both compression and expansion. If the video signal switching described above was not used, double clocking could only be avoided by using two operator-handled memories in order to perform compression and expansion. The expansion memory would have to be placed in front of the interpolator and the memory to be pressed down behind the interpolator.

One of the conditions for proper circuit function is that the number of data samples written to the operator's memory in the arrival order must be equal to the number of samples read from the memory for that row for each horizontal line. If the number of samples to be written and read were not the same, the main channel image would be greatly skewed as the pointers to read and write lines by line were overtaken. This requirement is due to the fact that the in-service memories in the main channel are reset once per field. First, the vertical sync pulse of the main signal is reset to the write pointer, and then the read pointer is reset one line later.

For read and write indicators, a variable number of clock cycles may be required to move despite the same number of locations, due to the fact that both image data is compressed and expanded. To ensure that the number of written data samples always equals the number of read data samples, regardless of mode, three register values and two control signals are used to generate read and write permission signals in the operator's memory in the order of arrival for the components Y and UV of the main signal. . The two values of the WR-BEG-MN and RDBEGMN registers created by the widescreen microprocessor in the mapping circuit control function 340 determine the horizontal line position at which read and write should begin, in conjunction with the H_COUNT of the number of pixels in the horizontal direction. HCOUNT is a 10-bit read value used to determine the position of a pixel during a line period. The contents of the counter are cleared by a SOL start-line signal. The SOL signal is a one-hour pulse pulse and sets the horizontal H COUNT counter at the beginning of each line to zero. The SOL pulse is nominally aligned with the face of the horizontal synchronization component.

The third value of the LENGTH register is used to load the upper eight bits of the 10-bit counter to determine the number of data samples that were actually written to or read out by the operator in the order of arrival. The register value bits are inverted and at least two valid bits are brought to the LU level, resulting in a _LENGTH-1 value. The symbol A_ preceding the signal designation indicates a logical inversion. Thus, if the counter is overfilled, the transmission performed is brought to the LU level and the required number of samples is written or read. The actual number of written or read pixel samples is LENGTH x 4 because the register is loaded into the upper eight bits of the counter. The effect of the clock keying is counted by the keying of the access signal to the counter. In this way, the enable signal for the counter can also be used as an enable signal for the operator memory in the order of arrival, ensuring that the number of written or read samples is always LENGTH x 4, regardless of the mode.

Fig. 11 (d) illustrates one of the three identical circuits used to generate write and read permission signals for operator memories in the arrival order for storing the Y and UV components, the permission signals being designated WR_EN_FIFO_Y (case 1), WRENFIFOJJV (case 2) , RDENFIFOY, and RDENFIFOUV. There may be signals when stretching

RD_EN_FIFO_Y and RD_EN_FIFO_UV matched and labeled then RD EN FIFO Y UV (case 3). Circuit 1100 is first explained for case L Circuit 1100 compares the WRBEGMN signal with the upper eight bits of the H_COUNT value in the comparator 1102. The H COUNT value is a ten bit read value used to determine the position of the pixel in the row period. The counter is wiped with a SOL start-line signal. The SOL signal is a one-hour pulse and sets the horizontal HCOUNT counter at the beginning of each line to zero. The SOL pulse is nominally aligned with the face of the horizontal synchronization component.

The output of the comparator 1102 is delayed by the circuit 1118 and compared in the NAND gate 1104 with an inverted but otherwise not delayed version of itself. The output of the NAND type 1104, which is an active LO signal of one clock period width, is the LDn input input to the 10-bit counter 1106. The LDn input is also used to input the system clock leading edge to the 10-bit counter 1106. The LENGTH signal bits are inverted The LENGTH value is used to load the upper eight bits of the 10-bit counter to determine the number of data samples that were actually written to the operator's memory in the arrival order. The output of the inverter array 1110 is routed to the highest bits of the counter 1106 by the LOAD input. At least two valid bits are put into a logical upper level state. The effective value is _LENGTH-1. In order to set aspect -1 of the LENGTH-1 value, counter 1106 is stopped by the traffic transmission signal RCO, which occurs one clock cycle before the length counter 1106 reaches zero. The clock keying information is then summed by the traffic transmission signal RCO at the NOR gate 1112. The same enable signal is inverted by the gate 1116 and used as the enable signal for the operator memory in the arrival order. This memory and counter 1116 are thus made available in exactly the same way, thereby ensuring the correct number of samples to be written. In case 2, the WR_BEG_MU signal is also compared to HCOUNT. However, the CGUV_WR signal is used to generate the output signal WR EN FIFO UV. For 3, the RD_BEG_MN signal is compared to H_COUNT and the CGY_RD signal is used to produce the RD_EN FIFO Y UV output signal.

The processing of the color components for the main channel image can be carried out by several variants of the arrangement according to the invention. One alternative to topology is the arrangement shown in FIG. 8 and 11 (a) and explained in connection with FIGS. 52-55. Another topology for processing the colorant components for a main channel image is the arrangement shown in FIG. 13 and explained with reference to FIG. 51. The UV signal path 530 is shown in FIG. 13 is shown in block diagram form. Path 530 is very similar to the optional luminance data topology in the main signal path in the image processor 304 shown in FIG. 8 and 11 (a). The most significant difference is the use of the delay delay circuit 540 instead of the interpolator 337. The multiplexing circuits 534, 536 and 538 in the arrival order precede the delay delay circuit 540 or the path where the delay delay circuit 540 precedes memory 358. The multiplexing circuits are controlled by direction control circuit 532. . The output of multiplexing circuit 538 is divided into signals U_OUT and V_OUT by demultiplexing circuit 353.

If the interpolation system performs image compression, data samples must be discarded before being written to memory 358. In the case of multiplex U / V data, this represents

SK 280556 Β6 problem. If the data stream Y were discarded by the same clock keying pulses as the data stream Y, the UV components would not alternate in the order of U, V, U, V ... etc. For example, if only a sample U was discarded before writing to memory 358, the sequence would be U, V, U, V, V, U, V, and so on. Therefore, a second clock keying signal is required. This signal is called CGUV (or CGUV if it is logically inverted). This signal is used only during compression, has only half the frequency of CGY pulses and always discards a pair of UV samples. The results of compression in an 8/5 ratio are shown in FIG. 51 (a) and 51 (b).

From this example, it is apparent how the CG signals to write at Y (_CGY) and UV (_CGUV) differ from each other. If the _CGY and _CGUV signals are in the LUN state, the samples are discarded. The CUV signal always starts with sample U and ends with sample V. The UV pair is thus discarded together, avoiding situations in which component V would be discarded from one pair together with component U from the next pair. A comparison of how the UV and Y data read from the respective memories 358 and 356 with the operator in the arrival order is shown in FIG. 51 (a) and 51 (b). Obviously, the UV data is skewed by up to one clock cycle with respect to the Y data. This is due to the fact that U / V indication data is not stored in the data stream of the handled memory in the arrival order. The skewing of the UV data slightly worsens the color component. However, this deterioration is never worse than the 4: 1: 1 multiplex color component system commonly used in high end television systems. The effective Nyquist frequency of the UV components is reduced to 2 MHz due to the rejection of the UV pairs, which is still sufficient for the sources of the "wide" color component I. As a result, the high quality of the color components of the signal is maintained even during the decommissioning of the UV pairs.

Compressing the image data requires that the clock keying signals to be written to the in-service memories 356 and 358 are different for the Y and UV signal paths. In principle, samples U and V must be discarded in pairs, because once the sample is discarded, the status information of that sample (whether sample U or V) is lost. For example, if a ninth bit was added to the memory 358 to transmit UV state information, individual samples U and V could also be discarded. When reading data from the memory 358, the UV components could then be properly sorted by interpreting the ninth bit state. However, since this sorting information is not used, the consequence is that UV data must be discarded in pairs and subsequent sorting after reading the contents of the memory 358 can be very simple.

Sorting of discarded UV pairs requires only a one-bit counter. This counter is synchronously set to a U (zero) state for a clock cycle that begins reading the memory 358 with the operator in the arrival order. This one-bit counter is accessed by the RD_EN_MN signal, which controls the reading of the main memories 356 and 358 with the operator in the order of arrival. In the press mode, the RD EN MN signal is continuously in the logical unit state from start to finish, on each horizontal line. The resulting UV_SEL_OUT signal is an alternating U / V component indicator that drives the selector line of the demultiplexer circuit 353. In this way, the UV samples are successfully sorted after reading from the memory 358, even if the synchronization information of the UV components could not be stored in the memory 358. later recall.

As the image is expanded, writing to the operator memories 356 and 358 is uninterrupted in order of arrival from beginning to end. Reading from these memories is done with delays and samples are held (repeated) while reading from the memories.

This retention or repetition of samples is done using the clock read-out information that is part of the RD_EN_MN signal and its complement RDENMN.

It is important to point out an important difference compared to pressing. The status of the UV sample is known when it is read from the memory 358 with the operator in the arrival order. The UV data is written to the memory 358 by continuously alternating the components U, V, U, V ... etc. When the data is read from memory 358 and then interrupted by delays, a one-bit counter is also paused, which generates a UV_SEL_OUT signal to account for the fact that the data from the memory has been retained. This ensures correct sorting by the demultiplexer circuit 353.

The one-bit counter is paused at the right time because the RD_EN_MN signal is routed to its opening input. This ensures that the UV_SEL_OUT signal is also suspended when the memory 358 is suspended. Executing the stretching does not require that the Y and UV component read permission signals for in-order memories 356 and 358 are separated because the hour read key for UV data, which is a CGUV signal, is now identical to the hour read key for Y data , the CGY signal. Exercising is easier than performing compression. Moreover, the Nyquist frequency of the color component is not impaired when expanded and the 2: 1: 1 signal quality is fully maintained.

The described topology of the multiplexed color component has a number of advantages. The method is efficient and ideally adapted to operation in conjunction with the broadband brightness raster mapping system. The complexity of the circuitry is minimized while maintaining a high degree of color signal quality. These advantages are partly due to the following improvements. UV pairs are discarded at the memory input 358 for UV components. This eliminates the need to keep the clock keying information through this memory, which would require the operator memory in the arrival order to be 1 bit wider than the true accuracy of the UV data. The UV component interpolator, which would operate analogously to the interpolator 337, is replaced by a delay matching circuit. This eliminates a very complex mathematical function. In addition, approximately 2000 gates are saved by creating a parallel array in the integrated circuit. And, ultimately, the ultimate UV signal quality is not lowered, even in the worst case, below the 4: 1: 1 color channel arrangement (Y, U, V) and remains at a 2: 1: 1 ratio after stretching.

In a further embodiment of the invention shown in FIG. 8 and 11 (a), a delay adaptation circuit is not required. Instead, the operator memory in the order of arrival is controlled in a way that achieves the same results. Fig. 52 (a) and 52 (b) illustrate portions of the luminance and color paths in the gate array 300. FIG. 52 (a) is an optional image compression topology in which an interpolator 337 is inserted in front of the memory 356. In the color path, FIG. 52 (b) illustrates only the operator's memory 358 in the arrival order.

Fig. 53 (a) to 53 (1) show an example of image compression. For the purposes of this example, it is assumed that the luminance and color components were correctly matched to the delays prior to the analog-to-digital conversion and that the interpolator has a delay of 5 clock cycles, although the actual interpolator delay is 20 clock cycles and luminance and color signals are not aligned. The UV_MUX selection line for the analog switch or demultiplex circuit 344 is an 8 MHz signal derived by dividing the system clock pulses by two. As shown in FIG. 53 (a), sets the pulse SOL at the beginning of a line having a width of one clock pulse, the UV_MUX signal at the beginning of each horizontal picture line synchronously to zero, as shown in FIG. 53 (b). The UV_MUX signal then flips its status in the horizontal line with each clock cycle. Since the line length is an even number of clock cycles, the state of the UV_MUX signal once triggered will continuously flip between levels 0 and 1. The UV and Y data flows from the A / D converters 346 and 342 are shifted because each of the A / D converters has delay of one hour cycle. Similarly, the delayed clock key information CGY shown in FIG. 53 (e) and the CGUV shown in FIG. 53 (f), from the interpolation control circuit 349 (see FIG. 9). The UV_FIFO_IN data of the UV component shown in FIG. 53 (d) and stored in the operator's memory 358 in the order of arrival, the data Y-F1FO-1N is overtaken by the Y component shown in FIG. 53 (c) because the luminance data passes through interpolator 337 and the color components are not interpolated. Reading the UV_FIFO data from the memory 358 for the UV component is as shown in FIG. 53 (h), delayed by 4 hour cycles against reading Y FIFO data from memory 356 for component Y shown in FIG. 53 (g), thereby adapting to said displacement. This gives a delay of four hours between the leading edge of the read permission signal RD_EN_MN_UV for the UV component memory shown in FIG. 53 (j), and the leading edge of the read enable signal RD_EN_MN_Y for the component Y memory shown in FIG. 53 (i). The resulting data streams Y and UV are shown in FIG. 53 (k) and 53 (1). The most unfavorable non-matching of the Y and UV components is a 1 hour cycle, which is the same result as can be achieved with a more complex system, for example, in which the relative memory positions with the operator can be interchanged in order of arrival and delay adaptation circuit.

It should be noted that reading from the memory 358 of the UV components is delayed by 4 hour cycles in the exemplary embodiment, although the interpolator delay is 5 hour cycles. The most preferred setting for the number of hourly cycles of the UV memory read delay is an even value that is not greater than the interpolator delay. When expressed in computer language C and denoting the delay as DLY_RD_UV, the following is issued: DLY_RD_UV = (int) ((int) INTERP DLY / 2) * 2, where INTERPDLY is the interpolator delay expressed in hourly cycles.

In practice, the interpolator may have a delay of 20 clock cycles (INTERP_DLY = 20) of luminance and color components are not adjusted. The luminance and color signals can be time-adjusted in many ways. The color components are usually delayed by a fire signal due to demodulation. The raster mapping system according to the invention has the advantage that any non-adaptation of the Y and UV components can be overcome by the interpolator delay. In the case of image compression, the DLYRDUV delay in reading the memory of the 358 UV components can be set within a range of 0 to 31 hours. Because the luminance signal interpolator 337 has an intrinsic delay of 20 clock cycles and each clock cycle is approximately 62 nanoseconds in length, the described raster mapping circuit can make corrections for the chrominance delay with respect to the luminance signal up to 1.24 microseconds (62 nanoseconds x 20). In addition, the raster mapping system can perform luminance signal delay corrections relative to the color component up to 682 nanoseconds (62 nanoseconds x [31-20]). This provides an extremely high degree of flexibility for connecting external analog video circuits.

The same different delay as the interpolator in the luminance channel when compressing the image can also be done when stretching the image. Fig. 54 (a) and 54 (b) show portions of the luminance and chrominance signal paths in the gate array 300. FIG. 54 (a) represents an optional topology corresponding to image stretching, wherein the interleaver 337 is downstream of the operator memory 356 in the arrival order. The path of the UV component containing the operator memory 358 in the arrival order remains unchanged. In the example of stretching the image shown in FIG. 55 (a) to 55 (1), it is assumed that the interpolator has a delay of 5 hour cycles. The start-line SOL signal, the UV MUX signal, the luminance data stream input Y_IN to the memory 356, and the color-data UV_IN input to the memory 358 are shown sequentially in FIG. 55 (a) to 55 (d). For correct timing of the Y and UV data, the write (DLY_WR_Y) to the memory 356 of the component Y may be delayed or the read (DLY_RD_UV) from the memory 358 of the UV components may be delayed. Delayed reading from the UV memory 358 is permissible in this case because the memory does not require interpolation coefficients K and C. In the image compression mode, writing would not be delayed, as this would tune the alignment of the coefficients K, C with respect to the clock keying information and the brightness portion of the interpolation would be violated. The correct setting of the DLY WR Y value, which delays writing to the component Y memory by 4 hours cycles, is indicated between the rising edge of the write permission signal WR_EN_MN_UV of the writing to the UV component memory shown in FIG. 55 (f), and the leading edge of the WR EN MN Y enable signal to the component Y memory shown in FIG. 55 (g). The clock keying signal CG and the output signal Y FIFO are shown in FIG. 55 (i) and 55 (j). The resulting time alignment of the components Y and UV is shown by the relative positions of the data streams Y_OUT and UV_OUT of FIG. 55 (k) and 55 (1).

The ability of a raster mapping system to compensate for external misalignment of luminance and color components is equally great for both stretching and compressing the image. This is a very important function of the raster mapping system, since it eliminates the need to use a variable delay line at the luminance channel input to perform luminance and color component adjustment. The choice of a particular topology may be based on a number of factors, and other circuits may also be considered.

The auxiliary signal interpolation is performed in the auxiliary signal path in the image processor 306. The picture-in-picture circuit 301 controls the field memory for storing the six-bit component Y and the U components V of the incoming 8: 1: 1 image data, which is the video memory 350 RAM type. The picture memory 350 stores two picture data fields in a plurality of memory locations. Each memory location stores eight bits of data. In each eight-bit memory location of the stored one šesťbitová luminance sample Y (sampled at a frequency of 640 f _H) and the other two bits. These two other bits comprising either data FSW_DAT fast switching, or part of the sample U or W (sampled at a frequency of 80 f _H). The FSW DAT values indicate which type of field was written to the RAM image. Since two RAM data fields are stored in the RAM 350, and during the display period the RAM 350 is read completely, both fields are read during image decomposition. The picture-in-picture circuitry 301 determines which of the fields will be read from memory for display using fast switching data. The picture-in-picture circuitry 301 always reads a field of the opposite type to that currently being written to overcome the image tearing problem. If the field that is being read is of the opposite type to the field that is currently being displayed, the even field that is stored in the 350 RAM image memory changes when the top row is read. As a result, a small image preserves proper interleaving without tearing the movement.

The timing and synchronization circuit 320 generates read, write, and enable signals necessary for operation of the memories 354, 356, and 358 in the order of arrival. Operator memories in the order of arrival to the main and auxiliary channels are made available to write data of those parts of each line of the image that are required for subsequent display. Data is written from either the master or auxiliary channel, but not both, which is necessary to combine data from each source into the same line or lines of the image. The in-service memory 354 arranged in the auxiliary channel is written synchronously with the auxiliary video signal, but is read synchronously with the main video signal. The main picture signal components are written to the memories 356 and 358 synchronously to the main video signal and read from the memories also synchronously to the main video signal. Frequency of switching between main and auxiliary channel is a function of the selected special effect.

Creating various special effects, such as truncated images, juxtaposed, is done by controlling read and write permission signals for the line memories with the operator in the order of arrival. The procedure for this display format is shown in FIG. 7 and 8. In the case of truncated images displayed side-by-side, the WRENAX write-enable control signal for the memory 354 in the order of arrival is 2048 x 8, arranged in the auxiliary channel active after (1/2) x (5/12) = 5 / 12, or approximately 41% of the active video line period (after acceleration) or 67% of the sub-channel active line period (before acceleration), as shown in FIG. This corresponds to a 33% (approximately 61 active image) truncation of 5/6 interpolation signal extension. In the main video signal shown at the top of FIG. 8, the write control enable signal WR_EN_MN_Y is active for the memory memories 356 and 358 in the arrival order of 910 x 8 after (1/2) x (4/3) = 0.67 or 67% of the active video line period. This corresponds to a truncation of approximately 33% and a 4/3 compression ratio performed in the main channel image by the operator memories in the 910x8 arrival order.

In each of the attendant memories in the arrival order, the data is stored in an equalization manner for reading at a particular point in time. The active time area in which data from each of the memories can be read is determined by the display format selected. In the truncated mode shown side by side, the main channel image is displayed in the left half of the screen and the auxiliary channel image is displayed in the right half of the screen. As shown, the signals of the freely selectable portions of the image have different waveforms for the main and auxiliary channels. The read enable control signal RD_EN_MN of the 910 x 8 in-memory arrival order, arranged in the main channel, is active for 50% of the active image line period, beginning at the beginning of the active image immediately after the rear delay of the video signal. The RDENAX read enable control signal for the sub-channel is active for an additional 50% of the active image line period, beginning with the rear edge of the RD_EN_MN signal and ending with the front delay of the main channel video signal beginning. The write control enable signals are synchronous with the respective input data of the handled memory in the order of arrival (both master and auxiliary), while the read control enable signals are synchronous with the video signal of the main channel.

The display format shown in FIG. l (d) is particularly needed since it allows the creation of two nearly full images arranged side by side. This display is particularly effective and suitable for a wide screen format, such as 16 x 9. Most NTSC signals are in 4 x 3 format, which is, of course, 12 x 9. Two images can be arranged on the same 16x9 screen broadcast in NTSC and in 4x3 formats, either with 33% cropping, or 33% compression of images and introducing aspect ratio distortion. Depending on the user's preference, any image cropping ratio can be set to distort the aspect ratio from 0 to 33%. Two images arranged side-by-side can be created, for example, as a compression of 16.7 and simultaneously a trim of 16.7%.

The operation can be described using generally expressed acceleration and trimming ratios. The display means may be given with a ratio of width and height of the display format expressed as M: N, the source of the first video signal may then have an aspect ratio of display format A: B and the source of the second video signal shall be given with aspect ratio of display format C: D. the signal may optionally be accelerated by a coefficient in the first range, from about 1 to (M / N - A / B), and optionally truncated by a coefficient in the second range, from about 0 to [(M / N - A / B) - 1] . The second video signal may optionally be accelerated by a coefficient in the third range. from about 1 to (M / N-C / D), and optionally trimmed by a coefficient in the fourth range, from about 0 to [(M / N-C / D) -1.

The horizontal display time for a 16x9 screen is the same as for a 4x3 screen because the nominal line length is 62.5 microseconds in both cases. Therefore, the video signal transmitted in the NTSC standard must be accelerated by a factor of 4/3 in order to maintain the correct ratio of the grains without distortion. The 4/3 factor is calculated as the ratio of two display formats:

4/3 = (16/9) / (4/3).

Variable interpolators are used to accelerate the video signals in accordance with embodiments of the invention. In the past, operator-operated memories having different clock frequencies at inputs and outputs have been used to perform similar functions. If, for comparison, two 4 x 3 NTSC signals are displayed on a single 4x3 screen, each of the images (or a combination thereof) must be distorted or trimmed by 50%. There is no need for acceleration comparable to that required for widescreen viewing.

A field synchronization system for preventing pointer collisions for reading and writing and maintaining interleaving integrity is explained in more detail in relation to obi. 28 to 36. The picture-in-picture processor operates by sampling the image auxiliary data with clock pulses at a frequency of 640 f _H coupled to the horizontal synchronization component of the incoming auxiliary image signal. This function allows the orthogonally sampled data to be stored in the pa20

SK 280556 B6 mint 350 type RAM. Reading data from the RAM image must be done at the same 640f _H frequency. Due to the generally asynchronous nature of the main and auxiliary video signal sources, RAM data cannot be displayed orthogonally without being modified. To facilitate synchronization of the slave signal with the main signal, a row memory with independent clock signals for reading and writing is arranged in the slave signal path behind the output of the image RAM 350.

As shown in more detail in FIG. 28, the RAM image output 350 is the input of the first of the two four-bit savers 352A and 352B. The VRAM_OUT output is arranged in four-bit data blocks. Four-bit screensavers are used to combine the auxiliary signal into eight-bit data blocks. The screensavers also reduce the clock frequency of data pulses from 1280 f _H to 640 f _H. The eight-bit data blocks are written to the operator's memory 354 in the order of arrival at the same clock frequency 640 f _H that is used to sample the auxiliary image data when stored in the 350 RAM image memory. The size of the operator's memory 354 in the arrival order is 2048 x 8.

The reading of the eight-bit data blocks from the memory 354 is performed by a display clock signal having a frequency of 1024f _H , which is coupled to a horizontal synchronization component of the main video signal. The basic configuration, which uses multiple line memory with independent input read / write clock signals, allows orthogonal display of data that has been orthogonally sampled. The eight-bit data blocks in the multiplexing circuit 355 are divided into six-bit luminance samples and difference samples. The data samples can then be interpolated as needed to the desired aspect ratio of the display format and written as the output of the image data.

Since the reading and writing of data from the operator's memory in the order of arrival, arranged in the auxiliary channel, are asynchronous, there is a possibility of collisions of pointers to read and write. These collisions can occur when old data is read from the memory before new data can be written to that memory. Pointer collisions can also occur if memory is overwritten with new data before old data could be read from it. It is therefore necessary to preserve the integrity of translation.

First of all, a sufficiently large memory must be selected to avoid collision of pointers to read and write in the memory with the operator in the order of arrival arranged in the auxiliary channel. When displaying an image with a normal aspect ratio format, trimmed by 33%, the 2048x8 operator-access auxiliary memory is capable of storing 5.9 lines of image data, which is calculated as follows:

N = (2/3) x (0.82) x (640) = 350 L = 2048/350 = 5.9 where N is the number of rows taking into account the 82% active row period, and L is length of each row. It has been found that it is not advisable to use higher lead rates than 2 lines per field. Thus, a five-row memory in the order of arrival, sampled according to the invention for an auxiliary channel, may be sufficient to avoid collisions between read and write pointers.

The use of operator memory in the order of arrival in the auxiliary channel may be illustrated as shown in FIG. 29. FIG. 30 is a block diagram of a simplified circuit formed by D-type flip-flops for generating line delays (Z ^-1 ) and reset pulses for reading in an access memory 354 arranged in an auxiliary signal path. At the beginning of a new main signal field, the write pointer is set to the starting point of the operator memories in the arrival order. This reset pulse, designated WR_RST_AX, is a combination of a V_SYNC_MN signal sampled by H_SYNC_AX. In other words, the pulse WR_RST_AX occurs at the first horizontal synchronization pulse of the auxiliary video signal, which is provided after the vertical synchronization pulse of the main signal. Two horizontal lines of the main signal later set the read pointer to the starting point of the memory 354 with the operator in the order of arrival. The corresponding reset pulse is denoted RD_RST_AX and occurs at the third horizontal master pulse, which is provided after the vertical master pulse, or, in other words, at the second horizontal master pulse, which occurs after the WRRSTAX pulse.

Since the main and auxiliary video signals are asynchronous, there is some ambiguity in exactly where the write pointer is located when the read pointer is zeroed. The write pointer is known to override the read pointer by at least two lines. However, if the horizontal synchronization signal of the sub-channel is higher than the horizontal synchronization signal of the main channel, then the read indicator will be ahead of the shown two-line index. This implies that pointer collision is prevented for all signals with a forward speed of less than 2 lines on the field. The arrival memory 354, corresponding to the auxiliary channel, is divided into five line sections by means of suitably timed read / write reset signals. In this scheme, read and write pointers are initiated at the beginning of each of the displayed fields so that they are separated by at least two lines.

If the operator's memory in the arrival order were not five full lines long, the system would sacrifice the memory distance from the write pointer to the read pointer. This is the case for different compression modes, for example, 16%: N = (5/6) x (0.82) x 640 = 437

L = 2048 (5 x 437) = 4.7

In these cases, the length of the handled memory is less than five lines in the order of arrival. When pressed by 16%, the actual memory length is 4.7 lines, a factor of 0.8 in the equation for N when pressed by 33% is a functional limitation of the CPIP chip.

Since the read and write reset signals of the operator memory are separated by at least two lines of the active image in the order of arrival, the sacrifice is always performed at the cost of allowing the read pointer to catch up with the write pointer. In addition, only 80% of the image line is considered active because the image-in-picture processor is not able to store more than 512 image samples in the RAM image 350. In practice, however, this still provides a good active image line. In these cases, the advance rate is sacrificed for more visible image content. In addition, the auxiliary image is more distorted. In the worst case, a single line advance on the field may be tolerated between the main and auxiliary video signal sources. This is still more than necessary for most video sources, and the advance rate tolerance is sacrificed in those in filler modes that are expected to be least used.

Another problem stemming from asynchronous reading and writing of the operator memory in the arrival order is to maintain the interleaving integrity of the auxiliary channel image. Because the screen is coupled to the main video channel, the type of field currently displayed, i.e., the upper or lower field, is determined by the main signal. The type of field that is stored in the image RAM of 350 and is ready to be read at the beginning of the main channel field may or may not be the same as the type of field displayed. Thus, it may be necessary to change the type of auxiliary field stored in the RAM image 350 to adapt it to the main channel image.

The PIP 320 and gate array 300 quantize 262.5 lines of NTSC signal fields to 263 lines of upper (sometimes called even fields). This is due to the fact that the vertical synchronization component is sampled by the pulses representing the horizontal synchronization component, which is illustrated by the diagram in FIG. 31. The upper and lower field indicators have a value of 1 for the upper fields and 0 for the lower fields. The upper fields contain odd rows 1 to 163. The lower fields contain even rows 2 to 262. In FIG. 32 is a first U / L MAIN SIGNAL field indicator of a main image channel type. The HSYNC_AX signal represents the horizontal synchronization components for each sub-channel row.

The U / L (A) field type indicator is the type of field stored in the 350 RAM image memory if each line of the auxiliary channel was written normally. The term "normal" as used herein means that odd lines 1 to 263 are written to the RAM 350 when the upper field is being received and decoded. The U / L (B) field type indicator is the type of field stored in the 350 RAM image memory if the first line of the field is not written to the memory while receiving the top field. Instead, the first line is actually appended to the last line (number 262) of the bottom field. This makes an effective flip of the frame type since row 2 will be the first row displayed and row 3 will be the second row displayed. The received upper field now becomes the lower field and vice versa. The U / L (C) field type indicator is the type of field stored in the RAM image memory 350 when the last line of the top field is added to the memory 350 while receiving the lower field. This again effectively flips the field type, because row 263 will be the first row displayed and row 1 will be the second row displayed.

Adding and subtracting rows in modes B and C does not degrade the auxiliary channel image, as these rows appear during vertical reverse or overlap. The order of the signals shown is shown in FIG. 34, where the solid lines represent the rows of the upper field and the dotted lines represent the rows of the lower field.

As the main and sub channel signals are overtaking, the U / L MAIN SIGNAL indicator will be shifted left or right relative to the U / L indicators (A, B, C) of the sub channel channel types. At the position shown in the diagram, data should be written to the 350 RAM image using Mode A because the decision edge is in area A. Mode A is convenient because when the PIP receives a vertical synchronization component, it writes to the image The memory type 350 RAM is the same type of field as the display unit will require to read from the image RAM 350 triggered by the V-SYNC-MN signal (vertical synchronization component of the main channel). As the signals are overtaking, the mode will change according to their relative positions. The valid modes are shown graphically at the top of FIG. 32 and expressed in the table of FIG. 33. There is an overlap between modes B and C, since most of the time in which mode B is in effect is also in mode C, and vice versa. This is true for all 262 lines except two lines. If both modes B and C are valid, either of them can be used.

A block diagram of the interleaving integrity circuit 700 of the present invention is shown in FIG. 36. The output signals of circuit 700 are reset write and read control signals for the image RAM 350, for the on-order memory 354 in the auxiliary signal path, and for the on-order memory 356 in the main signal path, as shown FIG. 28. The main picture signal field type is determined by a pair of VSYNC_MN and HSYNC_MN signals. The type of auxiliary video signal field is determined by the corresponding pair of VSYNC_AX and HSYNC_AX signals. Each pair of signals has a predetermined phase relationship that is set in the gate array 300. This relationship is shown in FIG. 35 (a) to 35 (c), which refer to both pairs of signals. In all cases, the HSYNC signal has a square shape whose leading edges correspond to the beginning of the horizontal line of the signal. In all cases, the VSYNC signal has only one leading edge on the field that corresponds to the beginning of the vertical field of the signal. The relationship between the leading edges of the respective signal pairs is controlled by circuit 700 to determine the steps that are necessary (if at all) to accommodate the types of auxiliary signal fields and the main signal. To avoid ambiguity, the leading edges of the main signal pair are never narrower than 1/8 of the horizontal line period. The leading edges of the auxiliary signal pair are never less than 1/10 of the horizontal line period. This prevents mutual time instability of the leading edges. This relationship is provided by the gate array timing circuits.

The main pairs of VSYNC_MN and HSYNC MN signals are inputs to the first half-width type determination circuit 702, which includes two type D flip-flops. In one case, the HSYNC_MN signal is sampled by the VSYNCJVIN signal, which means that VSYNC_MN is the clock input. The output of this flip-flop is the UL_MN indicator of the upper and lower field for the main signal, which may have a logical unit state for the upper field type and a logic zero state for the lower field type, but this association is arbitrary. In the second case, the VSYNC_MN signal is sampled by the HSYNC_MN signal in the same manner as in the flip-flop 852 explained in connection with FIG. 30. The corresponding output of the _H circuit 702 is a vertical output synchronized with a horizontal output.

The auxiliary pair of VSYNC AX and HSYNCAX signals are inputs to the second field type determining circuit 710, which also includes two type D flip-flops. In one case, the HSYNC AX signal is sampled by the VSYNC_AX signal, which means that VSYNC_AX is an input of clock pulses. The output of this flip-flop is an UL AX indicator of the upper and lower signals for the auxiliary signal, which may have a logical unit state for the low-field type and a logic zero state for the lower-field type, but this association is arbitrary. In the second case, the VSYNC_AX signal is sampled by the ISYNC_AX signal I, in the same manner as in the flip-flop 852 explained in connection with FIG. 30. The corresponding output of the _H circuit 710 is a vertical output synchronized with a horizontal output.

The determination of the field type is shown in FIG. 35 (a) to 35 (c). If the leading edge of the field occurs in the first half of the horizontal row period, as in FIG. 35 (b), the field is the bottom type. If the leading edge of the field occurs in the second half of the horizontal row period, as in FIG. 36 (c), the field is an upper type.

The _H output of the main signal and the input signal HSYNC_MN delay circuits 704, 706 and 708, which form the delay periods of the horizontal lines to ensure the correct phase relationship of the output signals WR_RST_FIFO_MN, RD_RST_FIFO_MN and RD_RST_FIFO_AX. The delay that can be made by the D-type flip-flops is similar to the circuit shown in FIG. 30. A delay of two to three periods of horizontal lines is created between the write and read indicators.

The ULMN indicator on the top and bottom of the field corresponds to the U / L MAIN SIGNAL signal shown at the top of FIG. 32 and is one input of comparator 714 designated UL_SEL. The other inputs of the comparator 714 are the outputs of the UL_AX signal generator 712. The test generator 712 has a UL signal input UL_AX, which is the output of circuit 710. Another input of the test generator 712 is the HSYNC_AX signal, as a clock signal. The outputs of the test generator 712 are the U / L (A), U / LB) and U / L (C) signals shown at the bottom of FIG. 36 and corresponding three possible modes A, B and C. Each of the U / L (A), U / L (B), and U / L (C) signals is compared to the UL MN at the time of transition of the U / L_MN signal edge. which is also shown in FIG. 32. If UL_MN agrees with U / L (A), the field types are also matched and no action is required to maintain interleaving integrity. If UL / MN agrees with U / L (B), the field types are not matched. To maintain interleaving integrity, it is necessary to delay the writing of the top field by one line. If UL / MN agrees with UIL (C), the field types are also not matched. To maintain the integrity of the interleaving, it is necessary to introduce a one-line advance in writing the bottom field.

The result of this comparison is the SEL input of the selector circuit 718 designated RST AX SEL. The other inputs of this circuit are three vertical synchronization signals RST A, RST_B and RST_C generated by a generator 716 designated RST AX_GEN. The three synchronization signals have different phases from each other to perform corrective action to maintain interleaving integrity according to the output of the comparator 714. The delay circuit 722 restores synchronization of the selected synchronization signal with the auxiliary video output signal, thereby producing a WR_RST_VRAM_AX signal. The delay circuit 720 performs a similar function and produces the RD_RST_VRAM_AX and WT RST FIFO AX signals. As shown in FIG. 32, modes B and C overlap most of the time. In fact, only two of every 525 comparisons will require only one of them. modes B or C and not any of them. The comparator 714 may be arranged such that, with both modes in effect, it prefers mode C over mode B. This choice may be arbitrary or may be due to other reasons resulting from the circuit arrangement.

The circuit 111 shown in FIG. 4 (B) is a modification of circuit 11 of FIG. 4 (a), in which a liquid crystal display system is provided. The raster mapping techniques used in the detailed digital signal processing may also be suitable for a liquid crystal display system. The pixel map created by the mapping circuit 113 formed as a matrix address generator outputs at the digital multiplexed output Y_MX, U_MX, and V_MX of the gate array 300. The mapping circuit 113, constructed as a matrix address generator, drives the liquid crystal display 115.

Data reduction or compression and data recovery or stretching may be performed by alternative methods according to various widescreen television arrangements of the invention. In one alternative, an encoded signal is added to the auxiliary signal by the resolution control circuit 370, which is read again by the resolution control circuit 357. The resolution control circuit 370 may also be considered a data reduction circuit and the resolution control circuit 357 may be considered a data recovery circuit. Thus, in this resolution control method, a code sequence of m bits is added to the n-bit signal, after which the least significant m bits are neglected. The one-bit coded signal acquisition circuit and the corresponding one-bit coded signal acquisition circuit are shown in FIG. 39 and FIG. 40. The two-bit circuit for adding the coded signals and the corresponding two-bit circuit for reading the coded signals are shown in FIG. 41 and FIG. 42nd

As shown in FIG. 39 and 40, the summation circuit 372 combines the n-bit signal with a one-bit code sequence. A preferred single bit sequence is 01010101, etc. After adding the code sequence to the n-bit signal, the least effective bit is discarded by circuit 374. The coded signal with n-1 bits is then processed by the PIP module 320, the savers 352A and 352B, and the operator memory 354 in the arrival order. Subsequent output of circuit 306B after decoding the picture in the picture is an encoded signal with n-1 bits. In the data recovery circuit 357, the encoded signal with n-1 bits is passed to the summation circuit 802 and one input of the product gate 804. The signal at the other input of the product gate 804 masks the lowest valid bit of the encoded signal. The output of the product gate 804 is routed directly to the input of the non-equivalence circuit 808 and delayed by the circuit 806 by one clock pulse or one pixel and then routed to the second input of the non-equivalence circuit 808. The output of the non-equivalence circuit 808 is one input of the product gate 810 and at the same time the input of the Y component interpolator 359, this input constituting the new lowest valid bit of the decoded signal. The second input of the product gate 810 is a signal with the same coded sequence and the same phase as the coded signal passed to the summing point 372. The output of the product gate 810 is a subtraction circuit input 802. The output of the summing circuit 802 is combined with an additional bit fed from the output the non-equivalence circuit 808, thereby producing an n-bit decoded signal as the input of the Y component interpolator 359.

The two-bit coding circuit 370 shown in FIG. 41, includes a summation circuit 376 that combines an n-bit signal with a two-bit coding sequence. According to this embodiment of the invention, the coding signal may be defined by any repeating sequence of numbers 0, 1, 2, 3, which are in this order in any order. This definition includes the following sequences given in Table 1.

Table 1

0123 1023 2013 3012 0132 1032 2031 3021 0213 1230 2102 3120 0231 1203 2130 3102 0312 1302 2301 3201 0321 1320 2310 3210

A two-bit coding sequence that is particularly preferred is 02130213, etc., as shown in FIG. 41. The bit signal output of the summation circuit 376 has the two least significant bits truncated by circuit 378. The coded signal with n-2 bits is then processed by the image-in-picture processor 320, savers 352A and 352B, and a memory 354 the arrival order and the picture-in-picture decoding circuit 306B.

The quarter frequency component is usually less preferred than the half frequency component, although the quarter frequency component has half the amplitude compared to the half frequency component. The decoding scheme can therefore only be selected for suppressing the quarter frequency component. The fixed signal path of the decoding circuit is designed to delay and adjust the amplitudes. The path of the second signal comprises an inverse bandpass filter combined with a limiter. The inverse bandpass filter suppresses the frequency in the middle of the passband when added to the delayed and amplitude-matched original signal. The limiter ensures that only size-encoded aplites are suppressed. This decoding arrangement does not affect the signal component having half the frequency of the sampling frequency. The half-frequency signal component has a sufficiently low amplitude and a sufficiently high frequency to have a sufficiently low visibility and thus avoid problems.

In FIG. 42, such a decoding circuit 106D 'is shown. The n-2 bit signal, which is output from the picture-in-picture decoding circuit 306B, is an input of a delay circuit 822 that generates a delay of two clock pulses or two pixels to a second delay circuit 814 and a summing circuit 812. 814 is a countdown input of the summation circuit 812, which outputs an n-1 bit signal. The encoded signal with n-1 bits is the input of the limiting circuit 816. In this case, the output values of the limiting circuit 816 are limited by an interval (-1.0, 1), that is, an absolute value of one. The two-bit output signal of the limiting circuit 816 is applied to the input of the delay circuit 818 to generate a delay of two clock pulses or two pixels, and at the same time is a countdown input of the summation circuit 820. The delay circuit 818 and summation circuit 820 form a bandpass two, the frequency being a quarter of the sampling frequency. A two-bit signal is a binary complementary signal. The output of the summation circuit 820 is a three-bit signal that is a countdown input of the summation circuit 826. The output signal with n-2 bits of the delay circuit 822 is an input of multiplier 824. The output of multiplier 824 is the n-bits signal. . Sums in circuit 826 are assigned values or some corrections to this bit. The output of the summation circuit 826 is a partially decoded n-bit signal which is an input of the Y component interpolator 359.

The resolution or, to put it more precisely, the quality of the decoded video signal may, under certain circumstances, be improved by the time shift of the coding sequence. This sequence, whether single-bit or double-bit, repeats continuously in a given line, but is phase-shifted on different lines. Many time shift schemes can be created. In order to hide the display errors resulting from the actual coding process, the two shifted sequences shown in FIG. 43. Mutual displacements of fields by one and two pixels are those in which all rows of one field have the same phase and all rows of the next field are displaced by one or two pixels relative to the first field. The relative displacements of the frames transmitted by the two-bit coded signals are most effective in still images. In live images, a certain line structure may be visible where flat areas move. A one-pixel offset is particularly useful for two-bit codes if the signal is decoded, but for a non-decoded signal, a two-pixel offset is currently preferred. Whether or not a signal should be decoded depends on the display format.

An alternative to data reduction coding is to compress the pairs of pixels, which is explained with reference to FIG. 44. In the upper part of FIG. 44 shows a field containing lines 1, 2, 3, and so on. The pixels of each line are marked with letters. Each P element will be retained and each R element will be replaced. Permanent and replaced elements are moved one line per line. In other words: in rows with odd numbers, the second, fourth, sixth, etc. are replaced. figurative element. The even numbered lines then exchange the pixels that are in odd places. Two basic alternatives consist in replacing each replaceable element with a one-bit or two-bit code. The bits for the codes are taken from a series of bits available to define persistent pixels. This number of bits is limited by the memory capacity of the image processor. In this case, the CPIP chip and the RAM image memory 350 represent an average of 4 bits per pixel. If each swapped pixel is replaced by a single bit code, then 7 bits are available for each persistent pixel. Similarly, if each swapped pixel is replaced by a two-bit code, then 6 bits are available to describe each persistent element. In both cases, each pair of consecutive pixels (one permanent and one replaced) requires a total of 8 bits. Thus, a total of eight bits per pair represents an average of only four bits per pixel. Data reduction is in the range of 6: 4 to 7: 4. The sequence of the interchanged elements is illustrated by a portion of the field that contains three consecutive lines: n-1, n, n + 1. The pixels to be replaced are designated R1, R2, R3, R4 and R5. The elements to be retained are labeled A, B, C, and D.

According to the one-bit coded scheme, a swapped pixel is replaced by zero if its value is closer to the pixel above it than the diameter of the pixels on either side of it. In the example shown in FIG. 44, the one-bit replacement code for pixel R3 will be zero if the value of pixel R3 is closer to the diameter of the elements B and C than that of pixel A. Otherwise, the one-bit replacement code will be 1. For data recovery, R3 will be its average value pixels B and C if the one bit code is zero. Al; the one-bit code is equal to one, then the pixel value R3 'will be the same as the pixel value A.

Also shown is the exchange and renewal sequence for the two-bit code. The two-bit replacement code is equal to one if R3 is the closest to the average of A and 13. The two-bit replacement code is equal to two if R3 is the closest to the average of A and C, and three if R3 is the closest to the average of B and C. the sequence corresponds to the substitution sequence. If the two-bit code is zero, the pixel value R3 'is equal to A. If the two-bit code equals one, the pixel value R3' is equal to the average of A and B. If the two-bit code is two, the pixel value R3 'is equal to the average of pixel values A and C. If the two-bit code is equal to three, then the value of pixel R3 'is equal to the average of the values of pixels B and C.

The one-bit code is advantageous if the persistent pixels are described with one-bit resolution. The two-bit code is advantageous in that the replaced pixels are described with higher resolution. It is advantageous to do calculations with only two line values, thus minimizing the necessary line memory capacity. On the other hand, the inclusion of the D value in the calculations could create a more accurate surrogate sequence, but at the cost of an additional line of image memory capacity. Compressing the pairs of pixels may be particularly effective to provide good horizontal and vertical resolution, and in some cases better than encoding and decoding. However, the resolution of diagonal transitions is generally not as good as in coding and decoding.

According to the invention, a variety of data reduction and recovery schemes are available, including, for example, compressing pairs of pixels and encoding and decoding. In addition, different coding sequences with different bit counts and different ways of compressing pairs of pixels with different bit counts are available. A particular data reduction and recovery scheme may be selected by a widescreen microprocessor to achieve maximum resolution for each particular type of display format.

The widescreen processor also has the ability to control vertical deflection to perform vertical zoom. The widescreen processor topology is such that the raster mapping functions (interpolation) are independent of both the auxiliary and the loud channel from each other and from the vertical zoom (which controls the vertical deflection). Due to this topology, the main channel can be stretched both horizontally and vertically, maintaining the main channel zooming with the correct aspect ratio. However, unless the settings for the sub channel interpolators are changed, the picture in picture (small picture) will be zoomed vertically but not horizontally. The auxiliary channel interpolator may therefore be adapted to perform greater horizontal stretching to maintain the correct aspect ratio of the small picture in the picture during vertical stretching.

A good example of this procedure is to display a 16x9 envelope format, as explained in more detail below. In short, the master horizontal mapping is set to:: 1 (no expansion or compression). The vertical direction is zoomed by 33% (i.e. stretched at a 4/3 ratio) to avoid black bands associated with the source image in envelope format. The aspect ratio of the main channel image is now correct. The nominal setting of the auxiliary channel for a 4x3 source without vertical zoom is 5/6. The differential value for the expansion coefficient X shall be determined as follows:

X = (5/6) x (3/4) = 5/8

If the sub channel interpolator 359 is set to 5/8, the correct aspect ratio of the small picture is maintained and the objects inside the picture in the picture are not distorted.

A particular advantage of widescreen aspect ratio televisions is that the envelope format signals may be stretched to fill the entire wide screen, although it may be necessary to interpolate this signal to provide additional vertical resolution. According to the invention, there is an envelope envelope auto detection circuit that automatically performs a 4x3 aspect ratio signal extension that includes a 16x9 aspect ratio envelope image. The automatic envelope format detector is explained in detail with reference to FIG. 45 to 49.

In order to increase the vertical height of the envelope signal, the vertical scanning frequency is increased so that the black areas at the top and bottom of the image are removed or at least substantially reduced. The automatic envelope format detector is based on the assumption that the video signal will generally correspond to the signal shown in FIG. 45. Areas A and C have no active image or have low luminance levels that are less than a predetermined luminance threshold. Area B has an active image or at least a luminance level that is higher than a predetermined luminance threshold. The respective region time intervals are a function of the envelope format, which can range from 16x9 to 21x9. The duration of both A and C sections is approximately 20 lines for 16x9 format. The envelope format detector checks the brightness levels of areas A and / or C. If an active image or at least a minimum brightness level is detected in areas A and / or C, the envelope format detector outputs an output signal such as logic zero indicating an NTSC source with normal 4x3 ratio pages of display format. However, if the image is detected in area B, but not in areas A and C, then it is assumed to be an envelope signal source. In this case, the output signal would be a logical unit.

The operation of the detector can be improved by hysteresis, which is schematically shown in FIG. 46. Once a signal has been detected in an envelope format, the minimum number of field signals in the normal format must be detected before the display changes to the display needed for normal 4x3 signals. Similarly, once a normal 4x3 signal has been detected, the envelope format for the minimum number of fields must be detected before switching the imaging unit to wide mode. Circuit 1000 includes a row counter 1004, a field counter 1006, and a detection circuit 1002 in which the described image signal analysis algorithm is performed.

In another embodiment of the arrangement according to the invention, the envelope format detection is performed by calculating two gradients for each row of the image field. To calculate these two gradients, four values are required: the maximum and minimum values of the row being processed and the maximum and minimum values of the previous row. The first gradient, referred to as a positive gradient, is created by subtracting the minimum value of the previous row from the maximum value of the current row. The second gradient, referred to as a negative gradient, is formed by subtracting the minimum value of the current row from the maximum value of the previous row. Both gradients may have a positive or negative value depending on the scene content, but negative values of both gradients may be ignored. This is because only one gradient can be negative at a time and a positive gradient size will always be

2806 greater than or equal to the gradient size with a negative value. This simplifies the circuitry because the need to calculate the absolute value of the gradients is eliminated. If any of the gradients has a positive value that exceeds the programmable threshold, either the current or the previous line is assumed to have an image. These values can be used by the microprocessor to determine whether the image source is in envelope format or not.

The circuit 1010 for performing this envelope format detection method is shown in the block diagram of FIG. 48. The circuit 1010 includes an input luminance filter, a line maximum detector 1020, a line minimum detector 1022, and an output section 1024. The input luminance filter comprises the pulse final stage stages 1012 and 1014 and the merging circuitry 1016 and 1018. The envelope format detection circuit 1010 processes digital luminance data. Y_IN widescreen processor.

An input filter is used to improve the noise characteristics, making the detection more reliable. The filter is essentially composed of two stages of the final impulse response having the following transmission characteristics:

H (z) = (1/4) x (1 + Z ' ¹ ) x (1 + Z' ³ )

The output of each stage is truncated to eight bits (divided by two) to maintain unit DC gain.

The maximum row detector 1020 includes two registers. The first register contains the maximum pixel value at the current point of the line period. At the beginning of each line period, it is initialized with a SOL pulse with a one-hour pulse width of 80 h. A value of 80 h is the minimum possible value of an 8-bit number in two complementary formats. The circuit is accessed by a signal labeled LTRBX EN having a logical unit status of approximately 70% of the active video line. The second register contains the maximum pixel value for the entire previous line and is updated once per line period. The incoming luminance data Y_IN is compared to the current maximum pixel value stored in the first register. If they exceed the register value, the first register is updated in the next clock cycle. At the end of the image line, this register will contain the maximum value of all part of the line that has been made available. At the beginning of the next picture line, the value of the first register is loaded into the second register.

The row-minimum detector 1022 operates in the same manner, except that its second register contains the minimum pixel value for the previous row. The minimum pixel value is initialized to 7f _H , which is the maximum possible pixel value for an 8-bit number in binary complementary format.

The output section 1024 takes the values of the two second registers and stores them in eight-bit screens that are updated once per line. Two gradients are then calculated, a positive and a negative gradient. On the first line of the field, where any of these gradients is positive and greater than the programmable threshold, an enable signal is generated that allows the computation value of the current row to be entered into the first row register. In each row where either of the two gradients is positive and exceeds the programmable threshold, an additional enable signal is generated that allows the computation value of the current row to be entered in the register of the last row. The last line register will thus contain the last line of the field in which the threshold has been exceeded. Both of these enable signals can only act between lines 24 and 250 of each field. This prevents incorrect detection resulting from closed caption information and VCR head switching states. At the beginning of each field, the circuit is reinitialized and the first and second row register values are fed to the respective envelope format end registers. The LTRBX BEG and LTRBX END signals indicate the start and end of the signal in the envelope signal.

Fig. 49 illustrates an automatic envelope format detector as part of a vertical dimension control circuit 1030. The vertical dimension control circuit includes an envelope format detector 1032, a vertical image control circuit 1034, and a tristate output circuit 1036. Alternatively, vertical blanking and reset pulses may be transmitted as separate signals. According to the invention, an automatic envelope format detector can automatically perform vertical zooming or stretching of a 4x3 aspect ratio image signal that includes a 16x9 aspect ratio envelope image. If the VERTICAL SIZE ADJ output signal becomes active, it increases the control circuit 500 The vertical dimension shown in FIG. 22, a vertical deflection height of 4/3, thereby allowing the active image portion of the envelope format signal to fill a wide screen without distorting the aspect ratio. In another alternative, not shown in the drawings, an automatic envelope format detector may include a circuit for decoding a code word or signal transmitted by a signal source in an envelope format, which code identifies the signal to be transmitted as a signal in an envelope format.

The vertical display control circuit 1034 also determines which portion of the grid that exceeds the image size will be displayed on the shade. This is called vertical panning. If the image signal with the larger vertical dimension is not in the envelope format, the image with the conventional display format will be zoomed, i. j. stretched to simulate a widescreen format. In this case, however, the truncated portions of the 4/3 format image will contain the active image information. Vertical cropping of the image by 1/3 is necessary. Thus, regardless of further interventions, the top sixth and bottom sixth of the image will always be trimmed. However, the image content may determine that it is better to cut more of its upper part than the lower part, or vice versa. For example, if the entire storyline is at the bottom, i.e. j. on the ground, the viewer may prefer to trim most of the sky. Thus, the vertical panning capability allows you to choose which portion of the zoomed image will be displayed and which portion will be cropped.

The vertical panning is explained with reference to FIG. 23 and 24 (a) to (c). In FIG. 23 shows a three-level full vertical blanking and resetting signal at the top. These signals can also be generated separately. The vertical blanking pulse starts when the L_COUNT signal equals VRT_BLNK0, and ends when the LCOUNT signal equals VRT BLNK1. The vertical reset pulse begins when the L_COUNT signal equals VRT_PHASE and lasts 10 horizontal lines. The L COUNT signal is the output of a 10-bit counter used to keep track of horizontal shelves relative to the rising edge of the VSYNC_MN signal. The VSYNC_MN signal is a synchronized version of the VDRV MN signal, which is the vertical synchronization component of the main signal routed to the gate array. VRT_BLNKO and

SK 280556 B6

VRT_BLNK1 are generated by the microprocessor depending on the dependent panning command. The VRT_PHASE signal programs the relative phase of the VERT_RST output relative to the leading edge of the vertical sync component in the COMP_SYNC output. The COMP_SYNC output is the output of a J-K flip-flop. The status of this flip-flop is determined by decoding the outputs of the L_COUNT and H COUNT counters. HCOUNT is a horizontal position counter. The L COUNT is used to divide the COMP_SYNC signal into three segments corresponding to a horizontal synchronization pulse, a equalization pulse, and a vertical synchronization pulse.

The vertical deflection current without image overhang, which in fact relates to a normal six percent image overhang, is shown in dotted lines because it is the corresponding vertical blackout signal. The vertical blanking pulse width without image overhang is C. The vertical synchronization pulse is in phase with the vertical reset pulse. The vertical deflection current is shown in solid line for the image overlap mode. This is the corresponding vertical D-blanking pulse.

If the lower projection of the image A is equal to the upper projection of the image B, the image will have the form shown in FIG. 24 (a). If the vertical reset pulse is formed to delay after the vertical synchronization pulse, the lower image A overlap is less than the upper image B overlay, resulting in the image shown in FIG. 24 (b). This is a vertical pan down, showing the bottom and obscuring the upper third of the image. Conversely, if the vertical reset pulse is formed to precede the vertical synchronization pulse, the lower overlap of the image A is greater than the upper overlap of the image B, resulting in the image shown in FIG. 24 (c). This is an upward pan, showing the top and dimming the bottom of the image. The phase relationship of the vertical synchronization signal and the vertical reset signal can be controlled by a widescreen microprocessor constructed as a mapping circuit control circuit 340, thereby allowing vertical panning during the overlap of the operating modes image. Obviously, the overlapped image grid remains on the screen or shade during vertical panning: even vertically centered or symmetrical. The blanking interval can be moved or positioned vertically asymmetrically to the center of the grid, obscuring the larger part of the image upwards than downwards or vice versa.

A widescreen television according to various embodiments of the arrangement according to the invention may stretch or compress the image. using adaptive interpolation filters. The interpolar luminance components of the main and auxiliary signals may be time shift correction filters. For example, a four-point interpolator includes a two-point linear interpolator and a combined filter and multiplier that are cascaded to provide amplitude and phase compensation. Overall, four adjacent data samples are used to calculate each interpolated point. The input signal is routed to a two-point linear interpolator. The delay of this input is proportional to the value of the delay control signal (K). The amplitude and phase errors of the delayed signal are minimized by using a correction signal obtained by the additional filter and multiplier, which are cascaded. This correction signal performs a spike that compensates for the frequency response of the point-to-point linear interpolation filter for all values (K). The original 4-point interpolator is optimized for use with signals having a bandwidth f _s / 4, where f _s is the data sampling frequency.

According to another alternative embodiment of the invention, both channels can be used, which is called a two-step interpolation process. The frequency response of the original interpolation filter variable can be improved by using such a two-step process. This process is hereinafter referred to as two-step interpolation. The two-stage interpolator of the invention comprises a finite pulse filter with 2n + 4 taps and fixed coefficients and a four point variable interpolator as shown in FIG. 56 and 57. The output of the finite pulse filter is spatially positioned between the pixel input samples as shown in FIG. 56. The output of this filter is then combined by interleaving with the original data samples that are delayed to produce an effective sampling rate of 2f _s . This is a valid assumption for the frequencies in the bandwidth of the final pulse filter. The result is a significant widening of the effective bandwidth of the original four-point interpolator.

The compensated variable interpolation filter known in the art produces precisely interpolated samples until the frequency components of the signal are no more than about one quarter of the sampling frequency, ie 1/4 f _s . For signals having frequency components substantially greater than 1/4 f _s , a two-stage approximation may be used, as shown in the block diagram for the two-stage interpolator 390 in FIG. The digital sampling signal DS_A with a sampling frequency f _s is an input of a finite pulse filter, e.g. a fixed filter 391. The finite pulse filter 391 generates a second digital sample signal DS_B which also has a sampling frequency f _s from the DS_A signal. between the values of the first DS_A signal, for example, at midpoints between these values. The signal is also input DS_A the delay circuit 392, which generates a signal DS_C of digital samples that is identical with the signal DS_A, but the time delay of (N + l) / f _s. The data streams DS_B and DS_C are combined by interleaving in the multiplexing circuit 393, resulting in a data stream of DS_D values at twice the sampling rate, or 2f _s . The DS_D data stream is the input of the compensated interpolator variable 394.

The fixed pulse final filter is generally designed to accurately generate sample values corresponding to timing locations exactly halfway between the positions of the incoming sample. These are then interleaved with delayed but otherwise unmodified samples, creating a data stream with a sampling rate of 2f _s . The finite pulse filter is most commonly produced using an even number of symmetrically balanced taps. Eight-branch filter, which has, for example, branch weights:

-1/32, 5/64, -11/64, 5/8, 5/8, -11/64, 5/64, -1/32, will accurately interpolate signals having frequency components up to about 0.4 f _p . Because the data frequency is doubled to 2 _fs . the signal processed by the variable interpolator never contains frequency components higher than 1/4 of the sampling frequency.

The advantage of the two-stage interpolator is that it enables accurate signal interpolation with bandwidths approaching one half of the sampling frequency. Thus, the system is best suited for display modes that require time stretching, such as zoom, where the aim is to maintain as much of the original bandwidth as possible. This may be useful in widescreen television, especially in an auxiliary channel, where the auxiliary signal is initially sampled at a relatively low frequency, for example 10 MHz. Maintaining as much bandwidth as possible can be important.

A two-stage interpolator 390 'that is suitable for zooming is shown in the block diagram of FIG. 59. The components that are common to the interpolator 390 shown in FIG. 17, have the same reference numerals with respect to data flows. The purpose of the two-stage interpolator 390 'is to zoom the incoming image horizontally by a factor m, where m is greater than 2.0. Thus, if the input and output data signals have the same sampling frequency fiN, m output samples must be generated for each input sample. The signal is stored in the handler memory 395 in the order of arrival at frequency f ' _IN, and a portion of it is then read as a DS_A data stream at a reduced frequency f _s . The clock pulses f ₅ are formed below the clock pulses f ™ and do not have a uniform period.

The data stream DS_B corresponding to the sample values midway between the existing samples of data stream DS_A is determined using the fixed pulse response filter 391 and then interleaved with delayed samples of data stream DS_C to produce a double-rate DS_D data stream. The DS_D data stream, which is twice the original sample density, is then processed by the variable interpolator 394 to produce sample values for each period flN- The savings circuit containing the saver 398 and the summator 399 produces an output that increases each hour period flN by increment r = 2 / m. The fragmentary part controls the variable interpolator by supplying the K value from the saver 398. The integer carrier output (CO) generates by means of the saver 397 clock pulses 2fs to read the arrival memory 395 and shift the data by the final pulse filter 391 through delay circuit 392, multiplexer 393 and the interpolator 394. the splitter 396 produces from the signal 2 f _p f _p signal.

According to other variants of the arrangement according to the invention, interpolators can be used, the advantage being that they store the image of the auxiliary and main channel in an equalizing manner without additional line memory. The main channel row memory thus becomes also an image memory. Current interpolation filter variables require double multiplication. The first multiplication is done by a factor C, which is a two-bit number. The second multiplication is done by a factor of K. A factor of K is a five-bit number, allowing the case where K = 16/16. There are two ways to avoid the need for 5-bit multiplication. The first option is to multiply by 1-K instead of K, never choosing K = 0 as the display point. The second option is to multiply by the factor K, never choosing K = 1 as the display point.

A simplified multiplier for an 1/16 or 1/32 interpolator is shown in FIG. 61. The multiplier allows multiplication of the variable "a" by a five-bit variable "b", where "b" = (b ₄ , b ₃ , b ₂ , bi bo). The expression b ₀ is the least significant bit and b ₄ is the most significant bit. Values of "b" are limited to integers between 0 and 16 inclusive, although a similar procedure can be used to create more complex multipliers. For example, from the same rule, an integer multiplier of between 0 and 32 can be derived. If b = 10000, the multiplier multiplies the output of the previous addition circuit by two conditionally. For the arrangement shown, the number "a" is a number with bits. The conditional multiplication function by two may be performed, for example, by a shift register or a multiplexing circuit.

The K and C values may be stored in a memory block and the counter may, depending on the desired acceleration, index the read pointer to recall the desired memory location and load the K and C values into the interpolation multipliers. For this reason, it is very advantageous if the C value is encoded into a K value, so that a single four or five bit word can transmit both the K value and the C value. The C value is then a function of the K value. FIG. 62, where K is a five-bit number. In the arrangement shown in FIG. 63, multiple summing gates can be used to accurately determine the C values. The values are shown in the table in FIG. 64th

In order to achieve different C = f (K) functions, further embodiments are possible, as shown in the example of the alternative decoder of FIG. 65. By using this decoding scheme, for example, the need for a single-chip lookup table or additional registers to store values can be eliminated by using only a few gates. The factor K may be more easily decoded using the circuit shown in FIG. 66th

The two-step interpolation explained by FIG. 56 to 58 may be optimized to overcome the values of 0.25 fs, where fs is the original sampling rate, in an alternative manner to that described in connection with FIGS. 59. The frequency curves shown in FIG. 67, show that the frequency response deviation at 0.25 fs is 0.5 dB in magnitude for all K = (0, 1/8, 2/8 ... 1) values. If the amplitude echoes of the different interpolation filters are more than 0.5 dB distant, a visible error can be expected. In certain simulations, it has been found that visible errors may occur at an amplitude response of more than 1.0 dB. Therefore, the individual horizontal interpolator echo should form an envelope of responses for the selected values of K, such that the response curves are no more than 1.0 dB apart at any frequency as shown in FIG. 67. The critical frequency at which visible errors can be expected is indicated by f _c . In practice, the cut-off frequency or divergence of the frequency curves should be reduced as low as f _c .

According to a further variant of the arrangement according to the invention, the frequency bandwidth of the interpolator can be extended by a 2n + 4 compensating circuit which extends the value f _c to the whole horizontal interpolation. Such a compensating circuit can additionally be made without the addition of a further control variable, and hence without an additional degree of freedom.

The following linear interpolation compensation circuit may extend the critical frequency f _{c of the} total interpolation to 0.7 xf _s / 2 or 0.35 f _s , using the 0.5 dB maximum envelope criterion. If the 1.0 dB criterion is used, the curves divide at f _s = 0.75 xf _s / 2 = 0.375 f _s . In addition, if the design of K = 0 and K = 1 is limited in the design so that they do not need to be selected, the bandwidth may be increased even slightly beyond f _c . By selecting the value of C it is also possible to control the range of spikes.

By using a linear interpolator, an eight-bit interpolator can be created with an eight-tap final pulse echo filter for aplitude and phase compensation. The total interpolator for K = (0, 1/16, 2/16, ... 1) can be described as follows: c / 2 - Z '' (C ' ³ ' ² ) + Z ' ² (K + C ) + Z ' ³ (1-K + C) - Z' ⁴ (3/2) (C) + + C / 2) (Z ' ⁵ ).

The relationship between K and C is shown in the table and graph in FIG. 68 and 69. The set of curves shows that the ripple in the transmission band is less than 1.5 dB. The critical frequency for this compensation circuit is at 0.7 xf _s / 2.

This embodiment of the invention can also be extended to an eight-way compensation circuit that provides additional usable bandwidth.

An eight-point interpolator can be made up of an eight-way final filter of the impulse response

SK 280556 Β6 and a point-to-point linear interpolator, as shown in FIG. 70th

Three such compensating circuits can be defined by the following relationships:

(1) -C / 4 + Z '' (3/4) (C) + Z ' ² (-3 / ² ) (C) + Z' ³ (K + C) + (1-K + C) Z ' ⁴ + Z' ⁵ (-3/2) (c) + Z ' ⁶ (3/4) (C) + Z' ⁷ (-C / 4) (2) -C / 8 + Z * ¹ (5) / 8) (C) + Z ' ² (-12 / 8) (C) + Z' ³ (K + C) + Z ' ⁴ (1-K + C) + Z' ⁵ (-12 / 8) ( C) + Z ' ⁶ (5/8) (C) + Z' ⁷ (-C / 8), and (3) -C / 8 + Z * '(C / 2 + Z' ² (-1 1 / 8) (C) + Z ' ³ (K + C) + Z' ⁴ (1K + C) and Z ' ⁵ (-l 1/8) (C) + Z' ⁶ (C / 2) + Z ' ⁷ (C / 8).

kdcK = (0, 1/16, 2/16, ... 1).

Each of these circuits has its own distinct bandwidth and advantages. For the arrangement of FIG. 70, the K and C values are not shown. The C value may be selected to allow the most convenient set of curves to be obtained for any particular compression or expansion as a whole.

The control signal sends a K value to the linear interpolator. The K value is then decoded to obtain a C value for the compensation circuit multiplier. The multipliers of the C value in all interpolation equations are the final impulse response coefficients. For example, said equation (1) has tap weights (-1/14, 3/4, -3 / 2.1, 1, -3/2, 3/4, -1/4).

This embodiment of the invention can be broadly extended to 2n tap finite tone filters used as compensation circuits, although using only two linear multipliers to calculate linear interpolation and the associated compensation circuit can be quite difficult. For example, an alternative 10-tap finite impulse filter may be to use an 8-tap fixed filter for Z ' ¹ to Z' ⁶ taps, with Z ° and Z ' ⁷ taps dependent on any of K and C. This is feasible because frequency response needs additional compensation for bandwidth expansion if K approaches 1/2 from any direction, ie if K = 0 or K = 1.

In FIG. 60 is a block diagram of a specific circuit 1150 for creating an eight-pass two-stage filter using a four-point interpolator. The luminance image signal to be expanded or compressed is the input of the line delay circuit 1152. The delay circuit outputs designated Z °, Z ' ¹ , Z' ² , Z ' ³ , Z' ⁴ . Z ' ⁵ , Z' ⁶ and ΐ ^Ί are the inputs of the eight-pass filter 1154 of the final pulse response. This filter produces at least one set of intermediate samples labeled I, for example between actual Z-labeled samples. The results can sometimes be improved by using a plurality of finite pulse filters that generate a plurality of intermediate point sets, although this significantly increases the complexity of the system. Such additional filters, each requiring a delay circuit Z ' ^1, are illustrated by multiplying the final impulse response filter 1154 and the delay circuit 1158 for Z'. The outputs Z ^3, Z ⁴ and Z ⁵ are also inputs of the delay circuit 1156. The output of the matching Γ is the direct input of the data selector 1160, as well as the entry ^L1 delay circuit 1158. The outputs from the ^{(3 +} ". From the ^{(4 + n)} and Z ^{(5 + n)} are also the inputs of the data selector 1160. The inputs of the data selector 1160 are selected to be as symmetrical as possible with respect to the delay, the number of such inputs being one greater than the second tier interpolator points. in this case, a four-point interpolator 1162. The relative time position of the data selector 1160 inputs is as follows:

+ | 0 ^ - (4 + n) pl Z '( ^{s + n} )

The data selector circuit 1160 may be formed by a multiplexer pole controlled, for example, by a MUX SEL control signal. The optional files are diagrammatically indicated and arranged such that each interpolation of interpolator 1162 is based on two real points and two intermediate points. The outputs Y0, Y1, Y2 and Y3 of the data selector 1160 correspond to one of two selectable sets and are inputs of a four-point interpolator 1162. The operation of the MUX SEL multiplexer control signal is a function of the values of K, t. j. MUX_SEL = f (K). The choice of the MUX_SEL signal depends on which of the original points is the intermediate point. The output Yout of the interpolator 1162, which responds to the control values K and C, is an expanded or compressed image luminance signal.

Claims (19)

PATENT CLAIMS A widescreen television display system, comprising a first aspect ratio display screen (244; 115) coupled to a mapping circuit (50; 113) to enable the conversion of the output video signal (Y_MX, U_MX, V_MX) to another display format; a set of video signal inputs (Y_M, U_M, V_M; Y_A, U_A, V_A), wherein each of the video signals (Y_M, U_M, V_M; Y_A, U_A, VA) is a signal carrying picture information in one of different display formats; a video processor (304, 306) coupled to the display (244, 115) for processing at least two of the set of video signals (Y_M, U_M, V_M; YA, UA, V_A) to achieve mutual compatibility between these signals (Y_M, U_M, V_M; Y_A) , U_A, V_A) and to make these signals (Y_M, U_M, V_M; Y_A, U_A, V_A) compatible with the screen (244; 115), switches (SW1, SW2, SW3, SW4) for connecting the first and second video signals (Y_M, U_M, V_M; Y_A, U_A, V_A to the video processor outputs (304, 306) a coupled output video signal selector (312) (Y_MX, U_MX, V_MX) to select either one of first and second processed video signals (Y_MN, U_MN, V_MN; Y_AUX, U_AUX, V_AUX) the dull picture signal (Y_MX, U_MX, V_MX) is a single image display, or to select a combination of the first and second processed video signals (Y_MN, U_MN, V_MN; Y_AUX, U_AUX, V_AUX), wherein the video output signal (Y_MX, U_MX, V_MX) is a multiple image display, and a control circuit (340) of the mapping circuit (50, 113), the image processor (304, 306) and the selector (312) an output video signal (Y_MX, U_MX, V_MX) to adjust each picture transmitted by the output video signal (Y_MX, U_MX, V_MX) in the aspect ratio of the display format and in the aspect ratio of the picture during both single and multiple picture display. The display assembly of claim 1, wherein the first display aspect ratio screen (244; 115) has a wide aspect ratio aspect ratio. Display system according to claim 1, characterized in that one of the set of video signal inputs (Y_M, U_M, V_M; Y_A, U_A, V_A) is a video signal input with a first aspect ratio of the screen display format (244, 115). The display system of claim 3, wherein the first display aspect ratio screen (244; 115) has a wide aspect ratio aspect ratio. Display system according to claim 1, characterized in that one of the set of video signal inputs (Y_M, UM, V_M; Y_A, U_A, V_A) is a video signal input having a display format aspect ratio different from the first screen format aspect ratio (244; 115). The display system of claim 5, wherein the first display aspect ratio screen (244; 115) has a wide aspect ratio aspect ratio. Display system according to claim 1, characterized in that two of the set of video signal inputs (Y_M, U_M, V_M; Y_A, U_A, V_A) are video signal inputs with a display format aspect ratio different from the first aspect ratio of the display format ( 244; 115). Display system according to claim 7, characterized in that the first display aspect ratio screen (244; 115) has a wide aspect ratio aspect ratio. Display system according to claim 1, characterized in that one of the set of video signal inputs (Y_M, U_M, V_M; Y_A, U_A, V_A) is a video signal input having a first aspect ratio of the display format of the display means (244, 115) and another of the set of video signal inputs (Y_M, UM, V_M; Y_A, U_A, V_A) is a video signal input with a display format aspect ratio different from the first screen format aspect ratio (244; 115). Display system according to claim 9, characterized in that the first display aspect ratio screen (244; 115) has a widescreen display aspect ratio. The imaging system of claim 1, wherein the image processor (304, 306) comprises a crop trimming circuit and an interpolator for selectively interpolating each of the first and second image signal sets (YM, UM, VM; Y_A); , U_A, V_A). Display system according to claim 1, characterized in that the mapping circuit (50) comprises a raster circuit for creating a grid for the display (244). The display assembly of claim 1, wherein the mapping circuit (50; 113) comprises a circuit (113) for forming an address matrix for the liquid-crystal display (115). The display system of claim 1, wherein the mapping circuit (50; 113) is configured to provide independent image size adjustment in the first direction, and the image processor (304, 306) is configured to provide independent image size adjustment. in a second direction perpendicular to the first direction, wherein the picture is represented by an output video signal (Y_MX, U_MX, V_MX). The display system of claim 1, wherein the mapping circuit (50, 113) is configured to provide independent image size adjustment in the horizontal or vertical direction, and the image processor (304, 306) is configured to provide independent image size adjustment. in a vertical or horizontal direction. Display system according to claim 1, characterized in that the mapping circuit (50; 113) and the display (244; 115) are designed to handle non-interlaced video signals (Y_M, U_M, V_M; Y_A, U_A, V_). A) having a horizontal thread spread rate where f _H is a normal horizontal spread rate and is a positive integer, and further comprises means for converting video signals (Y_M, U_M, V_M; Y_A, LA, VA) having an interleaved format and a horizontal spread rate f _H to video signals (Y_MN, U_MN, V_MN; Y AUX, U_AUX, V_AUX) having an unfolded image format and a horizontal spread rate f _H. Display system according to claim 1, characterized in that it comprises a second selector (60) connected to the mapping circuit (50, 113) for selecting between the output video signal (Y_MX, U_MX, V_MX) and another input video signal which is coupled to the mapping circuit (50; 113) along the signal expensive that bypasses the image processor (304, 306). The display system of claim 1, wherein the screen (244; 115) has a wide aspect ratio display format, different aspect ratio video signal formats (Y_M, U_M, V_M; YA, U_A, V_A) are either a conventional display format aspect ratio or a wide screen display aspect ratio (244; 115), a first and a second image processor (304, 306) each including means for trimming and interpolating video signals (Y_M) , U_M, V_M; Y_A, U_A, V_A), respectively, for processing at least two of the set of video signals (Y_M, U_M, V_M; Y_A, U_A, V_A), as appropriate, the control circuit (340) is configured to selectively implement systems of display formats of multiple images on screen (244; 115). wherein some of the display format sets represent different video signal formats (Y_M, U_M, V_M; Y A, U_A, V A) having a different aspect ratio of display formats, at least one of which differs from the first aspect ratio of the display format (244; 115). Display system according to claim 18, characterized in that the input of the video signals (Y_M, U_M, V_M; Y_A, U_A, V_A) is an input of the video signal carrying the main picture information with a widescreen aspect ratio and overlapping the auxiliary picture with the aspect ratio the conventional format, and c the main image with the conventional format aspect ratio and the overlapping auxiliary image with the widescreen aspect ratio.