CZ316991A3 - wide-screen television display - Google Patents

Abstract

The system includes a video display having a specific format display ratio. A mapping circuit maps an adjustable picture display area on the video display. Two signal processors generate the first and second selectively interpolated video signals from input video signals. A switching circuit selectively couples video signal sources as the input video signals. A selecting circuit selects as an output video signal between one of the first and second processed video signals and their combination. A control circuit controls the signal processors and other circuits to adjust in format display ratio and image aspect ratio each picture represented in the output video signal.

Description

Technical field

The present invention relates to a television imaging system, in particular a widescreen imaging system, which interpolates image data to produce different display formats, both direct viewing and projection display systems.

BACKGROUND OF THE INVENTION

Most today's television systems have an aspect ratio of 4: 3 horizontal width to vertical height. Widescreen viewing is more likely to be a movie display format, such as 16: 9. Televisions with a 4: 3 aspect ratio, often referred to as 4x3, have limited display capabilities from single and multiple video sources. Television broadcasts broadcast by commercial broadcasters, except for experimental broadcasts, are broadcast in 4x3 format. However, many viewers find the 4x3 display format less satisfactory than the wider display format that is common with movies. A TV with a wider display format not only provides a more pleasing display, but is also capable of displaying widescreen sources in the corresponding widescreen display format. Movies are displayed in their original format and not in cropped or distorted form. The video source does not need to be cut off, even when converting a movie to a video signal, for example using a film sensor or processors in a television.

The widescreen aspect ratio of the image can be applied at both basic or standard line scanning rates and multiples thereof, as well as both interlaced and non-interlaced scanning. For example, standard NTSC video signals are displayed by interleaving consecutive image frame fields, each frame being generated by raster scanning at a basic or standard line scanning rate of approximately 1-5 734 Hz. The basic degradation rate of video signals is denoted differently, either fH, lih or 1H. The actual frequency of the 1fη signal will vary depending on the different video standards. In an effort to improve the image quality of television devices, systems for displaying video signals in a progressive manner without interleaving have been developed. Sequential de-interleaving requires that each displayed frame be de-interleaved in the same time period as is allocated to de-interlace one or two frames of interlaced format. Non-flicker AA-BB displays require each field to be staggered twice in succession. In any case, the line decomposition frequency shall be twice the standard line frequency. The degradation rate for such sequentially or flicker-free displays is referred to as 2f _H or 2H. For example, according to US standards, the scanning frequency is approximately 31,468 Hz.

Widescreen format televisions are also adapted to provide a variety of displays for both conventional and widescreen display signals, as well as a combination thereof in a multiple display system. However, the use of widescreen television displays presents numerous problems. The main areas of these problems are alternating the display formats of multiple signal sources, generating identical timing signals from asynchronous but simultaneously displayed sources, creating high resolution images from densified data signals, and switching individual multiple sources to generate multiple display systems.

SUMMARY OF THE INVENTION. The widescreen television imaging system of the present invention solves these problems. SUMMARY OF THE INVENTION The display system comprises display means having a first aspect ratio of the display format, means for mapping an adjustable display area in said display means, means for processing the first and second video signals from input video signals of one of different aspect ratios of the format display means, switching means for selectively associating video signal sources as said input video signals, means for selecting said first or second video signal or a combination thereof as output video signal, and means for controlling said mapping means, processing means, and selecting means to adjust the aspect ratio the display format and aspect ratio of each picture transmitted by said output video signal.

One of said different aspect ratios may be the same as said first aspect ratio aspect ratio.

In a preferred embodiment, said processing means is adapted to selectively trim said input video signals.

Said mapping means comprises means for creating a screen for the screen.

In another preferred embodiment, said mapping means comprises means for forming an address matrix for the liquid-crystal display unit.

In another preferred embodiment, said display area is adjustable in only one dimension.

Preferably, said display area can only be adjusted in a vertical direction.

In another preferred embodiment, said processing means is adapted for horizontal interpolation of said video signals.

In another preferred embodiment, the imaging system of the invention further comprises means for converting the interlaced picture signals to an non-interlaced picture format.

In another preferred embodiment, said video signal sources comprise channel selectors and video connections.

Said processing means may further comprise respective interpolation means for said first and second input video signals.

With only a vertically adjustable display area, said processing means may be adapted to only analyze interpolation of said input video signals.

In another preferred embodiment, said mapping means comprises horizontal and vertical deflection circuits for generating a raster, the raster being vertically adjustable and said processing means adapted to only horizontally interpolate said input video signals.

Said processing means may be adapted to interpolate said input video signals by selectively stretching or compressing said input video signals.

In a further preferred embodiment, the display system according to the invention comprises second means for selecting between said output video signal and an external video signal for display by said mapping means and said display means.

The display system of the invention may further comprise means for synchronizing said processing and mapping means.

The widescreen television display system of the present invention provides high resolution capability, allows displaying single and multiple images from single and multiple sources having similar or different aspect ratios, the aspect ratio ratios being optional and having all the necessary features and capabilities of the widescreen systems described in the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 (a) to 1 (i) show different widescreen display formats, FIG. 2 is a block diagram of a widescreen television display system of the present invention adapted to operate in 2fH line decomposition; Fig. 3 is a block diagram of the widescreen processor shown in Fig. 2; Fig. 4 (a) is a block diagram of a widescreen television display system according to the present invention adapted to operate in line scanning Ιίκ; FIG. 5 is a block diagram of the widescreen processor shown in FIG. 4; FIG.

a block diagram with further details of the widescreen processor common to the diagrams of FIGS. 3 and 5; FIG.

FIG. 8 is a block diagram of the gate array shown in FIG. 6 with the main, auxiliary and output signal sides; FIGS. 9 and 10 are diagrams of the format of the display format shown in FIG. 1; Fig. 11 (a) a block diagram with a more detailed representation of the path of the main signal of Fig. 8, Fig. 11 (b) the shape of the main signal of Fig. 11 (a) when the video signal is compressed, Fig. 11 (c) a waveform of the main signal of Fig. 11 (a) when the video signal is expanded; Fig. 12 is a block diagram with a more detailed representation of the auxiliary signal path of Fig. 8; 7, 15, 16 and 17 are block diagrams of the decimation portion of the timer and control portion shown in Fig. 14, Fig. 18, a table of values used 15 to 17, 19 (a) and 19 (b) block diagrams of fully programmable universal decimation circuits for controlling the horizontal and vertical compression ratios; FIG. 20 is a block diagram of the interlace-to-interlace conversion circuit 2, FIG. 21 is a block diagram of the noise attenuation circuit shown in FIG. 20, FIG. 22, a block diagram combination. and the circuit diagram of the deflection circuit shown in FIG. 2, FIG. 23, the waveforms of the vertical motion of the image, FIGS. 24 (a) to 24 (c) display formats according to the waveforms shown in FIG. 23, FIG. 2, FIG. 26 is a block diagram of an RGB to

25, FIG. 27 is a block diagram of an internal signal 2ih circuit for converting 1fn to 2fn; FIG. 28 is a different block diagram of a portion of the auxiliary signal path shown in FIG. 8; FIG. Fig. 30 is a schematic diagram of a simplified circuit serving as an auxiliary path synchronization circuit in a gate array; Fig. 31 is a diagram of the time dependency between the half-frame indicator state and the image frame rows; 32 to 34 are diagrams of a method of maintaining interleaving integrity of concurrently displayed interrelated video signals; FIGS. 35 (a) to 35 (c) waveforms of the signals processed by the circuit shown in FIG. 36; 31 to 35, Fig. 37 is a diagram of the operation of the picture memory with lib Fig. 39 and 40 block diagrams of individual data reduction and recovery circuits performing the function of the resolution processing circuits of Figs. 6 and 8, Figs. 41 and 42 block diagrams. 6 and 8, FIG. 43 is a table of values constituting a rotation diagram for improving the operation of the data reduction and recovery circuits, FIG. 44 is a schematic table explaining another alternative embodiment of the resolution processing circuit of FIG. 6 and 8, FIGS. 45 and 46 are diagrams explaining the operation of the automatic envelope detector; FIG. 47 is a block diagram of the automatic envelope detector; FIG. 48 is a block diagram of an alternative embodiment of the automatic envelope detector circuit.

Fig. 38 Output switching Fig. 49 Block diagram of the circuit for adjusting the vertical dimension of the image including the envelope detector, Fig. 50 (a) to 50 (f) Color waveforms of the main video signal when converting from analog to digital Figs. 51 (a) and 51 (b) shape diagrams explaining the slope of the luminance and color components as the main signal passes through the gate array; 53 (a) to 53 (1) shape diagrams explaining the compression of the color components relative to the luminance components; FIGS. 55 (a) to 55 (1) waveforms explaining the expansion of color components relative to the luminance components, Figs. 55 and 57, pixel diagrams explaining the operation of two-stage variables 8, 11 (a) and 12, FIG. 58 is a block diagram of a two-stage compensated variable interpolation filter, FIG. 59 is a block diagram of a two-stage compensated variable filter arranged for translocation, FIG. 60 is a block diagram of an eight-branch circuit Fig. 61 is a block diagram of the resolution interpolator 1/16 * or 1/32, Fig. 62 is a table of K and C values for the interpolator shown in Fig. 61, Fig. 63 is a block diagram of the circuit for determining C values from K values. Fig. 64 is a table of values calculated by the circuit according to Fig. 63, Fig. 65 is a block diagram of an alternative embodiment of a circuit for determining C values from K values, Fig. 66 is a block diagram of another alternative embodiment of a circuit for determining C values from K values. the frequency response of a conventional two-stage four-point interpolator, Figure 68 table and Figure 69 graph, and Fig. 70 is a block diagram of an 8-point interpolator with a frequency response corresponding to Figs. 68 and 69.

DETAILED DESCRIPTION OF THE INVENTION

The individual portions of FIG. 1 illustrate some, but not all, of the various combinations of single and multiple image formats that may be performed by various configurations of the display system of the invention. The selected illustrations are intended to facilitate the description of the individual circuits included in the widescreen television display system of the invention. For the sake of simplicity of representation and description, a 4 x 3 ratio for a picture source or signal is a conventional ratio of the width and height of the display format, while a 16x9 wide ratio of the width and height of the display format is generally considered. However, the various embodiments of the display system according to the invention are not limited to these ratios.

Giant. 1 (a) shows a television for direct viewing, or projection, of a conventional 4x3 display format. If a 16x9 aspect ratio picture is transmitted as a 4x3 signal, black bars appear at the top and bottom of the screen. This is usually referred to as the envelope format. In this case, the observable image is quite small relative to the total display area available. Another possibility is that the 16x9 display source is converted before transmission, so that the image fills the entire vertical viewing range of the 4x3 display unit. In this case, however, much information is clipped to the left and / or right. side. Other. an alternative is that the envelope format image can be expanded vertically but not horizontally, but the resulting image will be appreciably distorted by vertical stretching. None of these three options are appropriate.

Giant. l (b) shows a 16x9 screen. A 16x9 display format image source is displayed completely, without cropping or distortion.

A 16x9 envelope format image, which itself is converted by a 4x3 signal, can be progressively degraded by doubling or adding lines to produce a larger image with satisfactory vertical resolution. The widescreen television display system of the invention can display such a signal in a 16x9 aspect ratio format, whether from a main source, an auxiliary source, or an external color signal source.

Fig. 1 (c) shows a 16x9 main signal display in which a 4x3 aspect ratio picture is embedded. If both the main and auxiliary video signals are sources of 16x9 display formats, the embedded picture may also have a display format with a 16x9 aspect ratio. The embedded image can be displayed in various positions.

Giant. 1 (d) shows a display format in which the main and auxiliary video signals are displayed with the same dimensions. Each image area has an 8x9 display format, which is different from both 16x9 and 4x3 formats. In order to display a 4x3 display format source in such an image area without causing horizontal or vertical distortion, the signal on the left and / or right side must be cut off. Most of such an image can be displayed (with less cropping) if some horizontal aspect ratio distortion is permissible. Horizontal compression results in vertical stretching of objects in the image. The widescreen television of the invention is capable of providing any combination of cropping and aspect ratio distortion, from maximum cropping without distorting aspect ratio to maximum distortion of aspect ratio without cropping.

The constraints imposed by the sampling of data in the processing of the auxiliary video signal make it difficult to produce a high-resolution image having the same dimension as that of the main video signal. These difficulties can be overcome in various ways.

Giant. l (e) shows a display format in which a 4x3 picture is displayed in the center of a 16x9 screen. Vertical dark streaks are visible on the right and left sides.

Giant. l (f) shows a screen that simultaneously displays one large 4x3 image and three and smaller 4x3 images. A smaller picture outside the circumference of a large picture is sometimes referred to as a picture outside picture rather than picture in picture. The term picture-in-picture is used herein for both display formats. If a widescreen television is provided with two tuners, either internal or one internal and one external, for example in a connected VCR (magnetoscope, video recording device), two of the displayed images may display real-time movement in accordance with the source. The remaining images can be displayed in still image format. Obviously, more than two moving images can be created by adding additional tuners and auxiliary signal processing circuits. Further, it will be appreciated that the large image and the three small images may also be switched to the position shown in Fig. 1 (g).

Giant. 1 (h) shows an alternative in which a 4x3 picture is placed in the center of the screen and six smaller pictures are also arranged in vertical columns on each side, also in 4x3 format. As with the previous arrangement, a two-tuner wide-screen television can provide two moving images. The remaining eleven images will be in the form of still images.

Giant. l (i) shows a screen with an array of twelve images in 4x3 display format. Such an arrangement is particularly advantageous as a guide for channel selection, where each of the images is at least a still image associated with a particular channel. As with the arrangements described above, the number of moving pictures will depend on the number of tuners and signal processing circuits available.

The various formats shown in Fig. 1 are illustrative, not limiting, and may be displayed on a widescreen television shown in the other drawings and described in more detail below.

FIG. 2 shows an overall block diagram of a widescreen television display system 10 according to the present invention adapted to operate with line scan 2fh ·. The television imaging system 10 generally comprises an input circuit 20, video signals, a chassis or television microprocessor 216, a widescreen processor 30, a 40 lfH / 2fa converter, a deflection circuit 50, an interface 60, a color YUV / RGB converter 240, a screen driver 242, a direct observation screen 244 or a projection type and a power supply 70. The grouping of different circuits into different functional blocks is provided for convenience of description and does not define the relative physical position of these circuits.

The video signal input circuit 20 is adapted to receive several complete video signals from different sources. The video signals may optionally be switched to be displayed as sig13 designated AUX1 and AUX2. decocamers, laser spotting, main or auxiliary. The radio frequency switch 204 has two antenna inputs ANTI and ANT2. These represent inputs for both external antenna and cable reception. The radio frequency switch 204 determines which antenna input is connected to the first tuner 206 and which to the second tuner 208. The output of the first tuner 206 is an input to the single-chip circuit 202 which performs a number of functions related to tuning, horizontal and vertical deflection and video signal control. The particular chip shown has the industrial designation TA7730. In the single-chip circuit 202, a baseband VIDEO OUT video signal is formed from the signal of the first tuner 206, which is fed both to the video signal switch 200 and to the TV1 input of the widescreen processor 30. Other baseband inputs to video switch 200 are These can be used for compact disc video players, video players, video games and the like. The output of the video switch 200 that is controlled by the television microprocessor 216 is labeled SWITCHED VIDEO and is another input to the widescreen processor 30.

As further evident from FIG. 3, the switch SW1 of the widescreen processor 30 selects the signals TV1 and SWITCHED VIDEO, outputting a SEL COMP OUT video signal applied to the input of the Y / C decoder 210. The Y / C decoder 210 may be implemented as adaptive line comb filter. The other two S1 and S2 video signal sources are also inputs of the Y / C decoder 210. Each of the S1 and S2 inputs is a different S-VHS source and consists of separate luminance and chrominance signals. The switch, which may be implemented as part of the Y / C decoder 210, in any adaptive row comb filter or an iak-o standalone switch, responds to the microprocessor TV signals 216 and selects one of the luminance and chrominance signal pairs, designated as Y_M outputs. and C_IN. The selected pair of luminance and chrominance signals is then considered the main signal and is processed in the main signal path circuits. Signal designations containing _M or _MN refer to the path of the main signal. The chrominance signal C_IN is redirected back to the single-chip circuit 202 to produce the difference color signals U_M and V_M. In this regard, U is the equivalent designation for (R-Y) and V is the equivalent designation for (B-Y). The signals Y_M, U_M and V_M are then converted into a digital form by the widescreen processor 30 for further processing.

The second tuner 208, which is functionally delimited as part of the widescreen image processor 30, generates a baseband video signal TV2. The switch SW2 selects between the signals TV2 and SWITCHED VIDEO as inputs of the second Y / C decoder 220. The second Y / C decoder 220 can also be implemented as an adaptive row comb filter. The switches SW3 and SW4 make the choice between the luminance and color outputs of the decoder 220 and the bright and color signals of the external video source designated Y_EXT and C_EXT. The signals Y_EXT and C_EXT correspond to the S-VHS input S1. The decoder 220 and the switches SW3 and SW4 may be combined, for example, in adaptive row comb filters. The output of switches SW3 and SW4 is then considered as an auxiliary signal and is further processed in the auxiliary signal path circuits. The selected brightness output is indicated by Y_A. Signal designations containing _A, _AX, _AUX refer to the path of the auxiliary signal. The selected chrominance signal is converted to color difference signals U_A and V_A. The signals Y_A, U_A and V_A are then converted into digital form for further processing. Us15 providing a device for switching the video signal sources into the main and auxiliary signal paths provides maximum flexibility in selecting the sources for different portions of different display formats. The complete sync signal COMP SYNC, corresponding to the Y_M signal and generated by the widescreen image processor 30, is fed to the sync signal separator 212. The horizontal synchronization component H and the vertical synchronization component V are inputs of the vertical subtraction circuit 214 which produces a VERTICAL RESET signal fed to the widescreen processor 30. The widescreen processor 30 produces an internal vertical reset output signal INT VERT RST OUT routed to the RGB interface 60. The switch in the RGB interface 60 selects between the internal vertical reset output signal and the vertical sync component of the external color signal source. The output of this switch is a select vertically synchronized SEL_VERT_SYNC component led to the deflection circuit

50. The horizontal and vertical sync components of the video auxiliary signal are generated by the sync mixture separator 250 in the widescreen processor 30.

The signal converter 40f to the 2fs signal converts the interleaved video signals to successively deinterleaved non-interleaved signals, such as those in which each line is displayed twice, or one in which an additional set of lines is created by interpolating adjacent lines of the same field. In some cases, the use of the previous row or interpolated row will depend on the level of motion that is detected between adjacent fields or frames. The generation of 2fn timing signals is shown in more detail in FIG. 27. The circuit of the converter 40 operates in conjunction with a RAM image memory 420. This memory may be used to store one or more image frames to allow sequential display. The converted image data, such as Y_2fn and U_2h and V_2fh 'signals, is fed to the RGB interface 60.

The RGB interface 60, shown in more detail in FIG. 25, allows a choice between the converted image data or the external RGB image data for display by the input signal circuit 20. An external color signal is considered to be a 2f _H wide-screen format signal. From the widescreen processor 30, a vertical synchronization component INT VERT RST OUT of the main signal is routed to the RGB interface 60, allowing the selected vertical synchronization component (fv " or fv " xt) to be transmitted to the deflection circuit 50. control signal INT_EXT. However, the selection of an external color signal input can lead to a vertical screen crash and damage the screen or projection screen in the absence of such a signal. Therefore, the RGB interface 60 detects an external synchronization signal to prevent input of a non-existent external color signal from being selected. The colors and time interval of the external color signal are also controlled by the widescreen image microprocessor 340.

The widescreen processor 30 includes a picture-in-picture processor 320 that processes the auxiliary video signal. The term picture-in-picture is sometimes abbreviated as PIP or pix-in-pix. The gate array 300 combines main and auxiliary video signal data into a variety of display formats, some of which are shown in Figures 1 (b) to 1 (i). The horizontal image and alignment image processor 320 and the gate array 300 are controlled by a widescreen image microprocessor 340. The widescreen microprocessor 340 is in communication with the TV microprocessor 216 via a serial bus. The serial bus contains four signal lines for data, clock pulses, opening signals and reset signals. The widescreen processor 30 further generates a complete vertical blanking and resetting signal in the form of a three-level sandcastle signal. Alternatively, the blanking and reset signals can also be generated as separate signals. The complete blanking signal is fed through the video signal input circuit 20 to the RGB interface 60.

In the deflection circuit 50, which is shown in more detail in FIG. 22, a vertical wobble signal from the widescreen processor 22, a selected horizontal 2f sync signal from the RGB interface 60 and additional widescreen processor control signals 30 are provided. These additional control signals relate to phasing, adjusting the vertical dimension east / west. The deflection circuit 50 generates a 2hr frequency feedback pulse to the widescreen processor 30, a converter 40 to convert 1fr to 2fn to the YUV / RGB converter 240.

The operating voltages for the entire widescreen television display system are generated by a power supply 70 that can be connected to an AC network.

The widescreen processor 30 is shown in more detail in Fig. 3. The main components of the processor 30 are the gate array 300, the picture-in-picture circuit 301, the analog-to-digital converters, the second tuner 208, the widescreen microprocessor 340 and the widescreen output coding circuit 227. Image ··. Further details of the widescreen image processor 30 that are common to both lfs and 2fK, e.g., an image-in-picture circuitry, are shown in Figure 6. An image-in-picture processor 320 that forms a substantial portion of the 301 7. The gate array 300 is illustrated in more detail in FIG. 8. Some of the components shown in FIG. 3 and forming portions of the main and auxiliary signal paths have been described in detail.

The second tuner 208 is coupled to an intermediate stage 224 and an audio stage 226 and operates in conjunction with a widescreen microprocessor 340. The microprocessor 340 includes an input / output circuit 340A and an analog output circuit 340B. The input / output circuit 340A produces color and time control signals, an INT / EXT signal for selecting an external color signal source, and control signals for switches SW1 to SW6. The input / output circuit 340A also monitors the EXT SYNC DET signal from the RGB interface to protect the deflection circuit and the screen (s). Analog output circuit 340B generates control signals for vertical adjustment, east-west adjustment, and horizontal phasing via respective interconnect circuits 254, 256 and 258.

The gate array 300 combines video information from the main and minor video signal paths to form a composite wide-screen image, for example, one of the images shown in different parts of FIG. The clock pulses are generated for the gate array 300 by a phase locked feedback loop 374 that cooperates with the low pass filter 376. The main video signal is fed to the widescreen processor 30 in analogue and YUV format as Y_M,

U_M and V_M. These main signals are converted from analog to digital by analog to digital converters 342 and 346, which are shown in more detail in Fig. 4.

The colorant signals have the common designations U and. V, which can be assigned to either the R-Y or B-Y signals, or the I and Q signals. The bandwidth of the sampled luminance signal is limited to 8 MHz because the system clock frequency is 1024 fa, which is approximately 16 MHz. A single analog-to-digital converter and analog switch can be used to sample color component data because the U and V signals are limited to 500 kHz or 1.5 MHz for band I. The UV_MUX line selected for the analog switch or multiplexer 344 is the frequency of 8 MHz, derived by dividing the clock frequency of the system by two. A single-pulse width SOL trigger line pulse sets this signal synchronously to zero at the beginning of each video line. The UV_MUX signal then changes its status in each row of the clock. Since the line length corresponds to an even number of clock cycles, the triggered state will continuously flip between 0 and 1 without interruption. The Y and UV data flows from the A / D converters 342 and 346 are shifted because each of the A / D converters has a delay of one hour cycle. Similarly, to compensate for this data shift, the clock gate information from control circuit 349 of the main signal path interpolator 304 must be delayed. If the clock gate information was not delayed, the UV data would not be correctly paired when discarded. This is important because each UV pair represents one vector. The element U of one vector cannot be paired with element V of another vector without causing a color shift of 20. Instead, sample V of the previous pair is discarded together with sample U of the new pair. This method of multiplexing the U and V components is referred to as 2 = 1: 1, since there are two brightness samples per pair of color components U, V samples. The Nyquist frequency for both U and V is effectively mixed to half the Nyquist frequency of brightness. Thus, the Nyquist output frequency of the A / D converter is 8 MHz for the luminance component, while it is 4 MHz for the color component.

The image-in-picture circuitry 301 and / or gate array 300 may also include means for improving the resolution of the auxiliary data despite being compressed. A number of data reduction and recovery circuits have been developed, including, for example, compressing pairs of pixels and correction codes. In addition, different data reduction correction sequences including different bit counts and different methods of compressing pixel pairs at different bit counts are considered. One of these data reduction and recovery schemes may then be selected by the widescreen image microprocessor 340 to achieve maximum display resolution for each particular type of display format.

The gate array 300 includes interpolators that interact with the line memories 356 and 358 with the operator in the order of arrival. Interpolators and memories are used to resample the main signal. Another interpolator can resample the auxiliary signal. The clock and sync circuits arranged in the gate array 300 control the handling of both the main and the auxiliary signal data, including combining them into a single video output signal having components Y-MX, U_MX and V_MX. These output components are converted to analog form čís1icově-analogue converters 360, 362 and 364. The signals Y, U and V in analog form are fed to a converter 40 for converting lf _and 2f _and which are converted to non-interlaced. The Y, U, and V signals are also encoded by the encoder 227 into a Y / C format to produce a Y-OUT-EXT / C_OUT_EXT output signal of the wide screen format available on the panel jacks. The selection of the synchronization signal for the encoder 227 is made by the switch SW5, either the C-SYNC-MN gate field signal 300 or the C_SYNC_AUX picture-in-picture forming circuit 301. SW6 then selects between Y_M and C_SYNC_AUX as the sync signals for the widescreen panel output.

The parts of the horizontal synchronization circuit are shown in more detail in FIG. 27. Phase comparator 228 is a phase locked loop component comprising a low pass filter 230, a voltage-controlled oscillator 232, a divider 234 and a capacitor 236. The voltage-controlled oscillator 232 operates at 32f _{and a} ceramic resonator 238 or similar device. The 32fH REF signal output 238 of the resonator 238 is the input of the converter 40 to convert 1fh · to 2f _a . The output of the voltage-controlled oscillator 232 is divided by a value of 32 to provide a second input signal at a suitable frequency for the phase comparator 228. The output of the divider 234 is a timing signal 1f _and REF fed to the widescreen processor 30 and converter 40 for 1f _and 2f _s . The timing signals 32fn REf and 1f _H REF are applied to a splitter 400 where they are divided by 16. The output 2fs is then applied to a pulse width modulation circuit 402. Controlling the splitter 400 by the 1f _and REF signals provides synchronization of the splitter operation with the phase locked-loop input loop of the video input portion. The pulse width modulation circuit 402 provides a suitable pulse width of the 2fs REF signal for proper operation of a phase comparator 404, such as CA1391, which is part of a second phase locked-loop feedback loop, further comprising a lowpass filter 406 and a voltage controlled oscillator 408 at 2h. The voltage-controlled oscillator 408 produces an internal timing signal at 2fn used to drive the sequentially spaced display. Another input signal to phase comparator 404 is the deflection pulses 50 or the corresponding timing signal. The use of a second phase locked-loop feedback loop comprising a phase comparator 404 ensures that each decay period given by 2fH is symmetrical within each period 1fh of the input signal. Otherwise, the display could have a raster interruption, for example one in which one half of the image lines is shifted to the right and the other half of the image lines is shifted to the left.

A block diagram of the interleaved image conversion system 900 is shown in FIG. 20. The circuit 900 may be implemented as an integrated circuit and perform all of the signal processing functions required to convert the interleaved image signals to progressive non-interlaced format. In addition, for signals that need to, the circuit 900 performs noise reduction in an adjustable range. The circuit shown may be used for Y, U, and V signal components in conjunction with an integrated circuit RAM image memory 902, such as the HM53051P.

The color components U_C and V_C of the signal are converted to a voltage corresponding to logic zero by one pulse delay of the internally forced pulses. Analog multi23 plexi obcd 908, coupled to the outputs of the keying circuits 904 and 906, alternately samples each of the chrominance components at a frequency of 2 MHz. These samples are then converted to an 8-bit digital signal by a fast analog-to-digital converter 910 operating at a frequency of 4MHz. The samples further pass the chrominance noise reduction circuit 912 to the accelerator memory 914. This memory stores only the active portion of each incoming video line of 53 microseconds, so that only 106 samples of each chrominance component are stored therein simultaneously. The memory contents are read at a rate that is twice the write speed, creating two identical lines of color information. The signal is set to zero by the blanking circuit 916 during the interval when no samples are available at the memory output. The two color components are then separated in the demultiplex circuit 918 and converted into an analogue form by means of two digital-to-analog converters 920 and 922. The reference base for the digital-to-analog converters 920 and 922 is adjustable via a serial bus connected to the bus control circuit 924 and, if desired, can be used to adjust the color saturation.

The luminance signal Y_C is converted internally to a level that can be adjusted via the serial control bus by the keying circuit 926 during the rearward pulse delay. This signal is converted from an 8-bit digital format using a fast analog-to-digital converter 928 operating at a frequency of 16 MHz. Thereafter, this signal passes through circuit 930, which can be used to automatically adjust the black level if necessary. The brightness is filtered by means of a low pass filter 932, the characteristic of which is given by the following formula:

Η (Ζ) = (1 + z-p p (1 + ζ ~ Ό ^: / 16) This filtered signal is then additionally sampled in circuit 934 at 4 MHz. The additional sampled signal is interpolated by interpolator 936 back to 16 MHz using the same low-pass characteristics and subtracted from the delayed version of the original luminance signal at summation point 938 to produce a signal that contains only high-frequency luminance components, and the high-frequency luminance signal then passes through the nonlinear deadband circuit 940 to remove low amplitude noises. The breakpoints of the non-linear characteristic can be set by the serial control bus.

The additionally sampled low frequency signal passes through the noise attenuation circuit 942 and is then interpolated by the interpolator 944 back to a 16 MHz frequency, whereupon the 9 summation point 946 is added to the noise-free high frequency signal. The luminance signal is then converted to a sequential or interlaced format by the accelerator 948. The memory stores only 53 milliseconds of the signal, which corresponds to 848 samples. The content of this luminance memory is read twice for each incoming image line. Further, the smaller accelerator memory 950 includes information representing the difference between interpolated luminance signals for the intermediate row and the incoming luminance signal. The smaller accelerator memory 950 contains only low frequency information about 212 samples. When the luminance signal acceleration memory 948 is read for the first time, the difference signal from the second acceleration memory 950 is interpolated to full intensity by the interpolator 952 and added to the luminance signal at the summit point 970. This produces a signal having a low-frequency component that corresponds to the interpolated luminance signal and a high-frequency component that corresponds to the incoming luminance

25 · signal. When the contents of the memory 948 are read a second time, the difference signal is not added. The output is then a signal at twice the speed of the input.

Circuit blanking 954 is inserted during an interval when no data from the accelerator memories is available. The level of this blanking is adjustable by the microprocessor of the chassis using a serial control bus. Three signals are required: DATA, CLOCK and ENABLE. The accelerated digital signals are converted into an analog form by the digital-to-analog converter 956. The reference base for the converter is adjustable via the control bus.

Line interpolation of low-frequency luminance information is performed completely at a reduced sampling rate (4 MHz) using motion adaptive processing. The 1 Mbit RAM • * external image memory 902, used as a frame memory, stores two half frames of an 8-bit low-frequency luminance signal and one half-frame of a three-bit motion signal. The connection to the RAM image 302 is made by the frame memory interface 964. Each of the fields stored in the memory represents a maximum of 256 active image lines, each containing 212 active samples. Passing the low-noise luminance signal with reduced noise through the 958 lfn delay circuit generates spatial interpolation (used in motion areas), whereupon the delayed and non-delayed signals are averaged in circuit 960. The output of the 958 lfa delay circuit is also stored in frame memory 902. 0 without one half line later, this output is recalled as a field delayed signal. This generates a time-interpolated signal for the stationary areas.

The field delayed signal is again stored in frame memory 982 and recalled after another 26 field, reduced by one-half of the line. The result is a net delay of one frame. The frame delay signal is then compared with a sample delayed sample by pattern in motion detector 962. Here, a three-bit motion signal is generated representing eight different levels of motion. The motion signal is also stored in the frame memory 902, from which it is recalled by one field, enlarged by one half of the line, later.

The delayed field motion is compared to the non-delayed motion, and a signal representing a higher level of motion is selected in circuit 978. This motion signal is used to control the soft switch or fader 966, which selects between spatially interpolated and time interpolated signals in eight different gray gradations.

The non-delayed low-frequency luminance signal at subtraction point 968 is subtracted from the output of the fader 966, producing a signal representing the difference between the interpolated and the incoming low-frequency luminance signal. The difference signal is then stored in a separate acceleration memory 950 as described above.

The noise damping circuit 942 can be implemented as shown in the block diagram of FIG. 21. The input signal at summation point 980 is subtracted from the output signal delayed by the delay circuit 986. If the delay value is selected correctly, the input is most signals almost the same as the delayed output and the difference is small. This difference then passes through the limiter 382 without limitation (without limiting, the limiter has a gain of 7/8). When the output of the restrictor 982 is added to the circuit input at the summation point 984, most of the input signal is suppressed, being replaced by a delayed output signal. This will suppress small changes, especially the show. If the input is significantly different from the delayed output, a limitation is applied. The resulting output is then almost equal to the input. The threshold at which the limitation occurs is adjustable via the serial control bus, and the noise attenuation rate can be varied from zero (zero threshold) to any desired value.

To reduce the noise of the low-frequency luminance signal, the delay in the circuit described above is equal to one frame time. Thus, the noise of still images is attenuated by a temporary low-pass filter.

The noise attenuation circuit is a cascade consisting of two of these circuits, one with a delay equal to one sampling interval (0.5 microseconds) and the other with a delay equal to one raster line (64 microseconds). The first circuit filters the noise in the horizontal direction, while the second circuit filters in the vertical direction.

Circuit 900 may comprise a converter 40 for converting f H to 2f _H, which is shown in more detail in FIG. 27. The reference numerals used in Fig. 27 are therefore shown in FIG. 20, in the bottom left corner. The timing signals used in the circuit are derived from an oscillator 238 which operates at a 32 MHz frequency and is synchronized by a phase lock with 1024 times the horizontal deflection frequency of the display unit. These signals are complemented by a deflection circuit return signal to input 2f '. The center frequency of the oscillator 238 is controlled by the external LC-circuit 974, while the external loop RC-filter 406 controls the phase locked loop characteristic. Phase of internal Timing signals (staging gates, blanking, etc.) can be set relative to input * 2h via serial bus.

The line input must also detect which of the 2f- _n pulses appear at the beginning of the incoming row and which at the center of the incoming row.

A vertical pulse input, such as f _Vn , is used to detect the start of the field so that the correct lines are stored in the frame memory. The number of rows that elapses between the vertical pulse face and the start of memory operation is adjustable via a bus command. A circuitry for generating an internal 2fh signal for generating a horizontal deflection system has already been described. Phase 2fn output relative to Iih input can be adjusted using serial bus.

The deflection circuit 50 is shown in more detail in FIG. 22. The circuit 500 is designed to adjust the vertical dimension of the grid, in accordance with the required amount of vertical overshoot needed to create different image formats. As shown schematically, the current source 502 generates a constant amount of current Iramp, which is provided by the vertical flip capacitor 504. Transistor 506 is connected in parallel to capacitor 504 and periodically discharges it in response to the vertical reset signal. If no adjustment is made, the Iramp current generates the maximum available vertical grid size. This may correspond to the amount of vertical overshoot needed to fill the wide screen display unit with an extended 4x3 display format signal source as shown in Fig. 1 (a). If a smaller vertical grid size is required, the adjustable current source 508 removes a variable amount of current Iadj from the Iramp current so that the vertical flip capacitor 504 charges more slowly and at a lower peak value. The adjustable variable current source 508 operates in response to a vertical dimension control signal, e.g., in an analog form, formed by the vertical dimension control circuit 1030 shown in FIG. 49. The vertical dimension adjustment circuit 500 is independent of the manual vertical dimension adjustment 510 which can be formed by a potentiometer or adjusting knob in the rear panel. In both cases, the excitation coil or coils 512 are provided with an appropriate excitation current. The horizontal deflection is provided with a phase adjustment circuit 518, an east-west correction circuit 514, a phase locked feedback loop 520 of 2fh · and a horizontal output circuit 516.

The color interface 60 is illustrated in more detail in FIG. 25. The signal to be finally displayed is selected between the output of the converter 40 for converting lfs to 2f-rf and the input of the external color signal. For the purpose of the described wide-screen color television according to the invention, the external input of the color signal is assumed to be a source of a progressively scanned widescreen picture signal. The external color signals and the complete blanking signal from the video signal input circuit 20 are inputs of the converter 610 after the RGB signal is converted to a YUV signal, which is shown in more detail in Fig. 26. is the input of the external synchronization signal separator 600. The vertical sync signal is selected by the switch 608. The horizontal sync signal is selected by the switch 604. The video signal is selected by the switch 606. Each of the switches 604, 606, and 608 is controlled by an internal / external control signal generated by the widescreen microprocessor 340. The choice of internal or external video sources is made by the user. However, if the user selects a lot of external color signal source and is not connected or turned on, or if the external source fails, the vertical screen will collapse and the screen or screens may be seriously damaged. Therefore, the presence of an external synchronization signal is controlled by an external synchronization detector 602. If the required signal is not present, a blocking control signal is transmitted to each of the switches 604, 606 and 608 to prevent the selection of an external color signal source. The RGB to YUV signal converter 610 also receives control signals from the widescreen microprocessor 340.

The converter 610 is shown in more detail in FIG.

26. Synchronization components of the color signals are separated by respective circuits 612, 614 and 616. The signals are further algebraically combined in summation circuits 618, 620 and 622 to produce RY (U), BY (V) and Y signals. Multipliers 628 and 634 the bit rates change the phase of the RY and BY signals so that the effective color of the signals changes, even if the phase is not entirely suitable for the RY and BY phasers. Multipliers 640 and 638 then similarly change the phase to alternate the effective color tone regardless of the deflection of the R-Y signals. and B-Y from the correct phase angle. The color and tone control signals may be generated by a widescreen image microprocessor 340 controlled by the TV microprocessor 216. This allows easy control of the color and tone characteristics of the external color signal without the need for additional circuits or adjustment of the external color signal source alone.

For the Y signal, the difference is 7.5 IRE relative to the correctly defined black level. Compensation is made by a correction blanking circuit 648 which inserts an offset of 7.5 IRE. The KEY signal is a control signal produced in the front delay of the video signal after the rear of the vertical sync signal and before the start of the active image. The KEY signal determines when keying should be performed in circuit 646. The delay circuits 624 and 626 determine the exact phase relationship of the R-Y, B-Y, and Y signals, despite subsequent changes due to the color control instruction and the color tone.

An overall block diagram of a widescreen television 11 according to the invention, adapted for operation with line frequency decomposition at 1fs, is shown in Fig. 4. The same components of the television 11 that correspond substantially to their counterparts in the television 10 shown in Fig. 2 are assigned the same reference signs. The television 11 generally comprises an input circuit 21 for receiving video signals, a TV microprocessor 216, a widescreen image processor 31, a horizontal deflection circuit 52, a vertical deflection circuit 56, a matrix circuit 241, a screen driver 242, a direct observation or projection type screen 244 and a power supply 70. The lfn to 2fs converter and RGB interface are not used. Accordingly, measures are provided for displaying an external color signal of a wide-screen format at a scanning frequency of lfh. The grouping of different circuits into functional blocks is provided for convenience of description and is therefore not intended to limit the relative physical position of these circuits.

The video signal input circuit 21 is adapted to receive a plurality of complete video signals from different sources. The video signals may be selectively switched to be displayed as main and auxiliary video signals. The radio frequency switch 204 has two antenna inputs ΝΤΙΝΤΙ and ANT2. These represent inputs for both outdoor antenna and cable reception. High-frequency switch

204 determines which of the antenna inputs is routed to the first tuner 206 and which to the second tuner 203.

The output of the first tuner 206 is the input of a single-chip circuit 203 which performs a number of functions related to tuning, horizontal and vertical deflection, and video signal control. The particular single-chip circuit shown is called TA8680. The baseband VIDEO OUT video signal generated in the single-chip circuit 203 from the signal supplied from the first tuner 206 is both the input of the video signal switch 200 and the input of the TV1 of the widescreen image processor. The other baseband video inputs to the video switch 200 are designated AUX1 and AUX2. These inputs can be used for camcorders, VCRs and similar devices. The output of the video signal switch 200, which is controlled by the TV microprocessor 216, is labeled SWITCHED VIDEO, which is at the same time another input of the widescreen processor 31.

As shown in FIG. 5, the widescreen processor switch SW1 selects the TV1 and SWITCHED VIDEO signals, outputting a SEL COMP OUT video signal applied to the Y / C input of the decoder 210. The decoder may be implemented as an adaptive row comb filter. Another SI video source is also input to the Y / C decoder 210. The SI source is an S-VHS source and consists of separate luminance and chrominance signals. The switch, which may be implemented as part of a decoder 210 in any of the adaptive row comb filters or as a standalone switch, responds to the microprocessor TV signals 216 and selects one of the luminance and chrominance signal pairs, designated as Y_M and C_IN outputs. The selected pair of luminance and chrominance signals is then considered to be the main signal and is processed in the paths of the main signal path. The decoder / demodulator arranged in the widescreen processor 301 produces the color difference signals U_M and V_M. The signals Y_M, U_M and V_M are then converted into a digital form in the widescreen processor 31 for further processing in the gate array 300.

The second tuner 208, which is functionally delimited as part of the widescreen image processor 31, generates a baseband video signal TV2. The switch SW2 selects between the signals TV2 and SWITCHED VIDEO as the Y / C inputs of the second decoder 220. The second decoder 220 may be implemented as an adaptive row comb filter. The switches SW3 and SW4 make a choice between the luminance and chrominance outputs of the decoder 220, the luminance and chrominance signals of the external video source indicated by Y_EXT / C_EXT, and the signals Y_M, C_IN. The signals Y_EXT / C_EXT correspond to the S-VHS input S1. The decoder 220 and the switches SW3 and SW4 may be combined, for example, in adaptive row comb filters. The output of switches SW3 and SW4 is then considered as an auxiliary signal and is further processed in the auxiliary signal path circuits. The selected brightness output is indicated by Y_A. The selected chrominance signal is converted to color difference signals U_A and V_A. The signals Y_A, U_A and V_A are then converted to digital form for further processing. The arrangement of the apparatus for switching the video signal sources into the main and auxiliary signal paths provides maximum flexibility in making the choice of sources for different parts of different display formats.

The widescreen processor 31 includes a picture-in-picture processor 320 that processes the auxiliary picture signal. - The term image · .- in the image is sometimes abbreviated as PIP or pix-in-pix. Gate field

300 combines main and auxiliary video signal data into a variety of display formats, some of which are shown in FIGS. 1 (b) to 1 (c). The picture-in-picture processor 320 and the gate array 300 are controlled by a wide-angle microprocessor 340. The microprocessor 340 is in communication with the TV microprocessor 216 via a serial bus. The serial bus contains four signal lines for data, clock pulses, opening signals and setting signals. Further, the widescreen image processor 31 generates a complete vertical blanking and adjustment signal in the form of three-level sandcastle signals. Alternatively, vertical blanking and adjustment signals can also be generated as separate signals. The complete blanking signal is then routed through the input section for receiving video signals to the RGB interface.

The horizontal and vertical sync components of the main signal are formed in the synchronization signal separator 286 which forms part of the demodulator 288 arranged in the widescreen processor 31. The horizontal sync component is the input of the phase locked feedback loop 290 at 1fh ·· forms in the sync signal separator 250 arranged in the widescreen processor 31. The horizontal deflection circuit 52 operates in conjunction with the single-chip circuit and responds to the east / west settings and the horizontal phase control signals of the widescreen microprocessor 340. The vertical deflection circuit 56 is controlled by the vertical dimension control circuit 54. The vertical dimension control circuit 54 responds to the vertical dimension control signals emitted by the widescreen microprocessor 340 ' and operates in a manner similar to the vertical dimension control circuit for the 2fs frequency of the television described above.

The widescreen processor 31 is shown in more detail in Fig. 5. The main components of the widescreen processor 31 are the gate array 300, the picture-in-picture circuit 301, analog-to-digital converters, second tuner 208, widescreen microprocessor 340 and output encoder 227 Widescreen image. Further details of the widescreen image processor 31, which are common to both lfn and 2fa, such as an image-in-picture circuitry, are shown in Fig. 6. The image-in-picture processor 320 that forms a substantial part of the image-forming circuit 301 In the image, it is shown in more detail in FIG. 7. The gate field 300 is shown in more detail in FIG.

8. A number of the components shown in FIG. 3 and forming parts of the main and auxiliary signal processing path circuits have been described in detail above. a number of other components, such as a second tuner 208, a widescreen image processor 340, interconnection outputs, analog to digital and digital to analog converters, gate array 300, image imaging circuit 301, and phase locked feedback loop 374 operate essentially as explained 3, so that their detailed description is not repeated.

The main video signal is fed to the widescreen processor 31 in an analog form, as Y_M and C_IN signals. The signal C_IN is decoded by the demodulator 288 into color difference signals U_M and V_M. The main signals are then converted from analog to digital by analog-to-digital converters 342 and 346, which are illustrated in more detail in FIG. 6. The auxiliary image data is also in analog and YUV format, as signals designated

Y_A, U_A, and V_A. In the PIP 301, these auxiliary signals are converted to digital form, whereupon the data is compressed and stored in a field memory for synchronization with the main signal, and then passed to the gate array 300 where it is combined with the main signal to produce the selected display format, for example by grouping rows. The operation of the PIP 301 is explained in more detail with reference to FIG. 6. The PIP 301 and / or the gate array 300 may also include means for improving the resolution of the auxiliary data, despite being compressed. The analogue signals, designated Y, U, and V, are routed to encoder 227 to produce Y_OUT_EXT / C_OUT_EXT widescreen output signals, which in this case are inputs to single-chip circuit 203. The encoder receives only C_SYNC_MN signal from gate array 300. The SW5 selects the Y_M and C_SYNC_AUX signals as analog-to-digital converter inputs. The single-chip circuit 203 generates YUV signals for the RGB mabrix circuit 241, which generates RGB signals for the display drivers 242 from the Y_OUT_EXT and C_OUT_EXT signals.

Giant. 6 is a block diagram illustrating further details of widescreen image processors 30 and 31 common to 1fa and 2fa, as shown in FIGS. 3 and 5. Signals Y_A, U_A and V_A are inputs of an image-forming processor 320 that may include circuit 370 control of resolution. The widescreen television of the invention may compress and stretch the image. These particular effects, represented by the various associated display formats shown in Fig. 1, are generated by the picture-in-picture processor 320 that can receive the processed Y_RP, U_RP and V RP data signals from the resolution control circuit 370. The resolution processing may not be used all the time, but only during the selected display formats. The PIP 320 is shown in more detail in FIG. 7. The main components of the P 320 are the analog-to-digital converter section 322, the input section 324, the switch and bus section 326, the timing and control section 328, and the digital-to-analog converter section 330. The timing and control section 328 is shown in more detail in FIG. 14.

The picture-in-picture processor 320 may be embodied as an improved variation of a CPIP-type base chip. It allows a number of special functions or effects, of which the following are illustrative. The basic special effect is a large image, part of which is covered by a smaller image, as shown in Figure 1 (c). Large and small images may be created from the same video signal or different video signals and may be interchanged or moved. Generally, the audio signal always switches to match the large picture. The small image may be moved to any position on the image or may advance through a number of predetermined positions. The zoom function allows the size and size of a small image to be scaled up or down, for example to any predetermined size range. At some point, for example, in the format shown in Figure 1 (d), the small and large images are substantially the same size.

In single-image mode, for example, the formats shown in Figures 1 (b), 1 (e) or 1 (f), the user can zoom in on the content of a single image, for example, in steps of 1.0. : 1 by 5.0: 1, while in traction zoom mode, the user can view or pan the image content, while the shaded image can move through different areas of the image. In both cases, a small image or a large image or zoom image may be displayed as a still image (still image format). This function also allows a stroboscopic format in which the last nine pictures can be repeated on the screen. The frame rate can be varied from thirty frames per second to zero frames per second.

The picture-in-picture processor 320 used in the widescreen television of the invention is somewhat different from the basic embodiment of the CPIP type chip. If a CPIP base chip was used on a 16x9 TV without using an image acceleration circuit, the embedded images would have a distorted aspect ratio due to 4/3 times the horizontal stretching resulting from the wider screen degradation.

The objects in this image would be horizontally elongated. Using an external acceleration circuit would not distort the aspect ratio, but the image would not fill the screen.

Existing picture-in-picture processors, which are based on a basic CPIP-type chip and are used in conventional television sets, have certain undesirable characteristics. The incoming video signal is sampled using clock impulses at 640fn, which are coupled to the horizontal synchronization signal of the main video source. In other words, the data stored in the RAM image memory merged with the CPIP chip is not sampled orthogonally to the incoming auxiliary signal source. This is the basic limitation of half-frame synchronization using the basic CPIP chip design. The unorthogonal nature of the forging speed input pattern 39 results in parallelogram distortions of the sampled data. The limitation is due to the RAM image memory used with the CPIP chip, which must use the same clock pulse for both write and retrieve data. When data from an image RAM, such as a RAM image 350, is displayed, the parallelogram distortions appear as random vibration along the vertical edges of the image, and are generally considered completely unacceptable.

The picture-in-picture processor 320 of the present invention, different from the basic embodiment of the CPIP chip, is adapted to asymmetrically compress the image data in one of a number of selectable display modes. In this operating mode, images are compressed at a 4: 1 ratio in the horizontal direction and a 3: 1 ratio in the vertical direction. This asymmetric compression mode produces distorted aspect ratio images that are stored in RAM image memory. Objects in the pictures are compressed horizontally. However, these images are normally taken out of memory for subsequent display on a 16 x 9 aspect ratio screen, for example by channel scanning. The image fills the screen and its aspect ratio is not distorted. The asymmetric compression according to this aspect of the invention allows the creation of special display formats on a 16x9 screen without the need for an external set of acceleration circuits.

Giant. 14 is a block diagram of a timing and control circuit 328 of an image-in-picture processor 320, for example, a modified version of the above-described CPIP type chip. The timing and control section 328 includes a decimation circuit 328C that performs asymmetric compression as one of a number of selectable display modes. Auxiliary images of different sizes can be performed with the remaining display modes. Each of the horizontal and vertical decimation circuits includes a counter that is programmed for a compression coefficient selected from a value table controlled by a widescreen microprocessor 340. The value ranges may be 1: 1.2: 1, 3: 1, etc. The compression coefficients may be symmetric - or unsymmetrical. , depending on the table build. The control of the compression ratios can also be performed by fully programmable universal decimation circuits controlled by a widescreen image microprocessor 340. The decimation circuit 328C is shown in more detail in Figures 15 to 18.

Giant. 15 is a block diagram of a circuit for performing horizontal compression. The circuit comprises a decimation circuit formed by a counter 850 denoted by MOD_N_CNTR1. The numeric value at input N is the horizontal coefficient N, denoted by HOR_N_FACTOR. The horizontal coefficient N refers to the extent to which the size of the picture represented by the image data of the auxiliary signal will be reduced to be displayed as picture in picture or as picture off picture. This coefficient is also a measure of the speed at which the pixels in a row are sampled. The numeric input for the input value is set to 0. The asynchronous output (RCO) is a horizontal line sampling opening signal. Giant. 16 is a block diagram of a circuit for performing vertical compression. The circuit comprises a decimation circuit formed by a counter 858 designated M0D_N_CNTR2. The numeric value on input N is the vertical coefficient N. denoted by VERT_N_FACTOR. The vertical coefficient N also refers to the extent to which the size of the image represented by the auxiliary signal image data will be reduced. to be displayed as PIP or PIP, but in this case, ¹ is a measure of how many lines are selected for sub-sampling. The numeric input for the input value is determined by a numerical calculation based on the vertical value of N corresponds to the vertical compression of the horizontal table at the coefficient N. The vertical coefficient N is added by 2 ”, the sum is then divided by two resolution of the upper and lower half of the image. The counter 358 outputs a vertical line sampling opening signal.

The horizontal and vertical coefficients N are generated by the circuit 859 shown in FIG. 17. The input is a N_FACTOR value that is in the range of 0 to 7. Each pair of ratios as shown in FIG. 18. N_FACTOR values are generated by a wide-screen microprocessor 340. Circuit 859 includes multiplexing circuitry 862 and 864 and circuit 860 for comparison with a value of 6. For each N_FACTOR value other than 6, the horizontal and vertical compression ratios are symmetrical due to the zero inputs of the multiplexing circuit when N_FACTOR is 6, keying as outputs multiplex circuit inputs. The result of these inputs is asymmetric compression, 4: 1 in the horizontal direction and 3: 1 in the vertical direction.

The counters in the decimation circuits are represented as integer decimators. However, the processing need not be limited to compressing the images in integer increments, provided that the horizontal compression coefficient is 4/3 times the vertical compression coefficient. Also, asymmetric compression is not limited to 16x9 wide format widescreen devices. If the aspect ratio of the format is for example 2: 1, the horizontal compression coefficient would be

3/2 times the vertical compression coefficient.

The control of the compression ratios can also be performed by fully programmable universal decimation circuits controlled by a microprocessor 340 ' widescreen image as shown in FIGS. 19 (a) and 19 (b). The horizontal compression coefficients are formed by the circuit shown in Fig. 19 (a), which consists of a summation point 866. an array 868 of eight OR-type gates and a storage 870. Each bit of the 8-bit output of the gate array 868 has a logic one when H_RESET signal is applied. If the H_RESET signal is zero, the field output 868 is equal to the field input that is the output of the summation point 866. The vertical compression coefficients are generated by the circuit of Fig. 19 (b) consisting of the summation point 872, the multiplexing circuit 874 and the accumulator 876. In each circuit, the summation point transmission input C1 is coupled to a voltage for a constant level 1 logic signal. In each circuit, the summation point CO output is a corresponding sample opening signal. In the circuit of FIG. 19 (b), the one input of the multiplexing circuit is coupled to ground to obtain a constant level 0 logic signal. The horizontal and vertical compression coefficients may be input from a widescreen image microprocessor 340.

In full-screen picture-in-picture modes, the picture-in-picture processor receives, in conjunction with the freely oscillating oscillator 348, a decoder signal, such as an adaptive line comb filter, as the Y / C input, decodes this signal into Y, U, V color components. and vertical sync pulses. These signals are processed in the picture-in-picture processor for various full-screen modes, such as zoom, still image, or channel scanning. For example, during channel degradation mode, the horizontal and vertical sync components supplied from the video signal input section have many discontinuities because the sampled signals (different channels) have different sync pulses and are switched at seemingly random moments.

Therefore, the sample clock signal (and the read and write clock signal in the image RAM) is determined by a freely oscillating oscillator. For still image or zoom modes, the sampling clock is coupled to the horizontal synchronizing component of the incoming video signal, which in these special cases is the same as the clock frequency of the display.

Again, as shown in FIG. 6, the Y, U, V, and C_SYNC (Sync Mix) outputs of the PIP 320, which are in analogue form, can again be encoded into Y / C components by a coding circuit 366. , which is in conjunction with an oscillator 380 at a frequency of 3.58 MHz. This signal, designated Y / C_PIP_ENC, may be connected to a Y / C switch (not shown) which allows the Y / C components of the main signal to be replaced by recoded Y / C components from the coding circuit. From now on, the encoded Y, U, V picture-in-picture signals and the synchronization signals are the basis for horizontal and vertical timing in the rest of the apparatus. This mode of operation is suitable for performing an in-picture zoom mode based on the operation of the interpolator and operator memories in order of arrival arranged in the main signal path circuits.

In a multi-channel mode such as that shown in Fig. 1 (i), twelve small images of twelve channels may be displayed simultaneously in accordance with a predetermined decomposition order, the PIP 320 has an internal clock source, controlled by an oscillator 348 at a frequency 3.58 MHz. The incoming auxiliary signal is converted from analog to digital, and, depending on the special effect selected, it is loaded into the RAM image type 350. In the prior art, the compiled special effect is converted back into an analogue form in the PIP by an analog form, then combined with the main signal data. However, in the widescreen television described, partly due to the limitation of the number of feasible different clock rates, the auxiliary data is the direct output of the RAM image type 350 without being further processed by the PIP 320. Preferably, however, minimizing the number of clock signals reduces the noise that occurs in television circuits.

As further illustrated in FIG. 7, the image-forming processor 320 includes an analog-to-digital converter section 322, an input section 324, a quick switch and a bus section 326, a timing and control section 328, and an analog-to-analog converter section 330. The picture-in-picture processor 320 generally digitizes the video signal into a luminance signal Y and color difference signals U, V, additionally sampling the results and storing them in a 1 megabit RAM image memory 350 as explained above. The RAM image memory 350 associated with the processor 320 has a capacity of one megabit, which is not sufficient to store the entire field of image data in 8-bit patterns. Increasing memory capacity is expensive and may require a more complex set of control circuits. A smaller number of bits per sample in the auxiliary channel, on the other hand, represents a reduction in the quantization resolution or bandwidth relative to the main signal, which is processed exclusively in 8-bit samples. This effective bandwidth reduction is usually not a problem if the additionally displayed image is relatively small, but can cause difficulties if the additional image is larger, for example the same size as the main image. The resolution control circuit may optionally perform one or more schemes to improve the quantization resolution or effective bandwidth of the auxiliary image data. A number of data reduction and recovery schemes have been developed, including, for example, compressing pairs of pixels, adding and subtracting coded signals. The coded signal addition circuit would be functionally arranged behind the RAM image memory 350, for example in an auxiliary signal path in the gate array 300 as explained in more detail. further. In addition, different sequences of encoded signals comprising different bit counts, and different methods of compressing pixel pairs at different bit counts are contemplated. One of these data reduction and recovery schemes may then be selected by the widescreen image microprocessor 340 to achieve maximum display resolution for each individual kind of display format.

The resolution control circuits are explained in more detail in connection with Figs. 56 to 70.

The luminance signals and color difference signals are stored in the 6-bit components Y, U, V at a ratio of 8: 1: 1. In other words, each component is quantized into six-bit samples and there are eight luminance samples per pair of color difference samples. The picture-in-picture processor 320 operates in a mode in which the incoming image data is sampled at a clock rate of 640fs, which in this case is coupled to the synchronization component of the incoming video signal. In this mode, the data stored in the RAM image is sampled orthogonally. If the data from the picture memory 350 of the picture-in-picture processor 320 is read, it happens. thus, using the same clock frequency 640f ». coupled to the incoming video assist signal. However, although these data are sampled and stored orthogonally and can be read orthogonally, they cannot be orthogonally displayed directly from the RAM 350 due to the asynchronous nature of the main and auxiliary video signal sources. Sources of the main and auxiliary video signals could be considered synchronous only if they displayed signals from the same video source.

Further processing is needed to synchronize the auxiliary channel, which is the data output of the RAM 350, with the main channel. Again, as shown in FIG. 6, two four-bit stacks 352A and 352B are used to recreate the eight-bit data blocks by combining the four-bit output of the image RAM 350. Four-bit storage also reduces the data clock pulse frequency from 1280ζη to 640f _a .

The display unit and the deflection assembly are generally synchronized with the main video signal. The main video signal must be accelerated to fill the wide screen, as explained above.

The auxiliary video signal shall be vertically synchronized with the first video signal and the display unit. The auxiliary video signal may be delayed in the field memory by a fraction of the field period, and then expanded in the row memory. Briefly, the synchronization of the auxiliary image data with the main image data is performed using the RAM image memory 350 as a field memory and the line memory 354 with the operator in the order of arrival that the signal is expanded. The auxiliary signal path interpolator 359 may correct acceleration in memory 354. The size of the operator memory 354 in the arrival order is

The problems that may arise in the synchronization of the master and sub-signals are the collisions of the read and write pointers in the memory 354 with the operator in order of arrival in the auxiliary signal path, and in maintaining interleaving integrity. A field synchronization system that prevents such read / write pointer conflicts and that maintains the field integrity of the fields is explained with reference to Figures 28 to 36.

The gate array 300 is common to both the widescreen processors, i.e. both the processor 30 and the processor 31. The main signal path 304, the auxiliary signal path 306, and the output signal path 312 are shown in the block diagram of FIG. and a widescreen microprocessor decoder 310. The data and address outputs of the widescreen microprocessor decoder 310, referred to as WSP DATA. they are routed to each of the main circuits and paths mentioned above, as well as to the PIP 320 and the resolution control circuit 370. Obviously, whether or not certain circuits are defined as being part of the gate array is largely due to the need to facilitate explanation of particular embodiments of the invention.

The gate array 300 is configured to stretch, compress, and trim the image data of the main image channel and, if necessary, to perform various display formats. The luminance component Y_MN is stored in the operator memory row 356 in the order of arrival for a period of time depending on the type of interpolation of the luminance component. The combined color components U / V_MN are stored in the memory 358 with the operator in the order of arrival. The luminance and chrominance components of the auxiliary signal Y_PIP, U_PIP, and V_PIP are generated by the demultiplexing circuit 355. The luminance component is subjected to the discriminating processing in circuit 357 (if necessary) and then expanded as necessary by interpolator 359, outputting the Y_AUX signal.

In some cases, the additional image is as large as that of the main signal, such as shown in Figure 1 (d). The capacity limitation of the RAM type of image RAM 350 associated with the PIP 320 may not provide a sufficient number of data points or pixels to fill such a large display area. 2a, a resolution control circuit 357 may be used to restore pixels of the auxiliary video signal that will replace the pixels lost when the data is compressed or reduced. The resolution processing may correspond to the processing performed by circuit 370 shown in FIG. 6. For example, circuit 370 may be a coded signal adding circuit and circuit 357 may be a coded signal reading circuit. The auxiliary signal interpolation may be performed in the auxiliary signal path 306, which is illustrated in more detail in FIG. 12. The PIP 301 shown in FIG. 6 controls a half-frame memory for the 6-bit components Y, U, V stored in FIG. 8: 1: 1 ratio, which is 350 RAM. The image RAM 350 always holds two frames of image data in a plurality of memory locations. Each memory location stores eight bits of data. One 8-bit Y pattern (brightness), sampled at 640fn, and 2 additional bits are stored at each 8-bit location. These two bits contain either additional data for fast switching (FSW_DAT) or part of a U or V sample (sampled at '80f _H). FSW_DAT values as follows. I suggest which type of field was written to RAM:

FSW_DAT = 0: no image,

FSW_DAT = 1: upper (odd) half frame, a

FSW_DAT = 2: lower (even) half frame.

The fields in the RAM image occupy spatial positions whose boundaries are defined by the horizontal and vertical addresses, as shown in the memory location diagram in FIG. 37. The boundary at these addresses is defined by changing the fast switch data from no picture to active field and vice versa. . These quick switching data transitions define the perimeter of the picture embedded in the picture, also referred to as the clipboard or the picture-in-picture overlay. Obviously, the aspect ratio of the display of objects in the picture embedded in the picture can be controlled independently of the aspect ratio of the clipboard format or the overlay of the picture in the picture, eg 4x3 or 16 x 9. a read pointer of the image RAM at start of the decomposition. Since two RAM frames of data are stored in the RAM image and the entire RAM image 350 is read during the display period, both frames are read during the display decomposition. The picture-in-picture circuitry 301 determines which field will be read from the display memory, using fast switching data and a read pointer start position. It may seem logical that if the display unit that is coupled to the main video source is just displaying the top field of the main image, then that portion of the RAM image corresponding to the top half of the auxiliary image frame would be read and converted to analogue. data and views.

This would be feasible for about half of all possible phase relationships between main and auxiliary video sources. However, problems arise because reading RAM of picture RAM is always faster than writing pictures compressed into this picture-in-picture mode. The memory read pointer may override the write pointer if the same field type is read and written at the same time. The consequence would be a 50% probability of tearing motion at some point in the small picture. Therefore, the picture-in-picture circuit always reads a field of the opposite type to the half-frame being written to overcome the problem of tearing motion. If the type of frame currently being read is the opposite of the field type being displayed, then the even field stored in RAM is inverted by deleting its upper row when it is read out of memory. As a result, a small image maintains proper interleaving without jerking movement. The end result of this field synchronization is that the CPIP chip produces a signal that is called PIP_FSW. This is an overlay signal that the PIP produces an analog switch that switches the Y / C signals of the main and sub channel (brightness and modulated color image information).

The auxiliary image input data is sampled at a frequency

640 fa and are stored in the RAM image type 350. Auxiliary data read from this memory is labeled VRAM_0UT. The picture-in-picture circuitry 301 is also able to reduce the additional image by integer coefficients equal in both horizontal and vertical directions as well as asymmetrically. As further shown in Fig. 12, the auxiliary channel data is buffered and synchronized with the digital video signal of the main channel by the four bit accumulators 352A and 352B, the auxiliary memory 354 in the arrival order, the timing circuit 369 and the synchronization circuit 371. The VRAM_OUT data is sorted by the demultiplexer circuit 355 into Y (brightness), U, V (color components) and FSW-DAT (fast switching data). FSW_DAT indicates which type of half frame was written to the RAM image. The PIP_FSW signal is received directly from the PIP circuit and is routed to the output control circuit. Here, it is coded which of the fields read from the RAM is to be displayed. Finally, the data of the auxiliary video channel components to be output is selected using the three multiplexing circuits 315, 317 and 319 shown in Fig. 8. Instead of superimposing a small picture in the picture using an analog switch in a mating or Y / C connection A wide-angle microprocessor 340 performs picture-in-picture overlay digitally. However, as described below, the PIP_FSW control signal is used to control the digital overlap together with the FSW_DAT signal.

The slave channel is sampled at 640 f «, while the main channel at 1024 íhh · The memory 354 in the arrival order is 2048 x 8 and converts the data from the subchannel sample rate to the main channel clock frequency. In this process, the video signal is subjected to a compression ratio of 8/5 (1024/640), which is more than the compression ratio of 4/3 required to correctly display the auxiliary channel signal. Therefore, the auxiliary channel must be expanded by an interpolator to correctly display a small 4x3 image. The required range of expansion by the interpolator is 5/6. The expansion coefficient X is determined as follows:

- X = (640/1024) x (4/3) = 5/6

Thus, a small picture can be correctly displayed in a 4x3 format by adjusting the interpolator 359 to perform a 5/6 stretching (5 input samples, 6 output samples), regardless of how it is scaled down by the image-in-picture processor.

The PIP_FSW data does not provide a sufficient interpretation of which field of the RAM image associated with the CPIP type chip should be displayed because the PIP data is horizontally rasterized to maintain the correct PIP ratio. Although the correct interleaving would be retained for a small picture in the picture, the overlap region of the picture in the picture would generally have an incorrect horizontal dimension. The only case where the size of the PIP area would be correct would be 5/8 stretched using interpolator 359, resulting in a small 16x9 image. For all other settings of interpolator 359, the overlap circumference would remain 16 x 9 format, while the embedded image would change horizontally. The PIP_FSW signal contains insufficient amount of information about the correct horizontal dimension of the PIP. The data stored in the picture memory is read before the picture-in-picture circuit completes the synchronization algorithm. Thus, the FSW_DAT fast switching data contained in the VRAM-OUT data stream from the RAM image corresponds to the type of field written to the RAM. Although the image component data (Y, U, V) stored in the RAM is corrected to prevent jitter and correct interleaving, the FSW_DAT signal is not modified.

In accordance with the invention, the PIP is the correct size since the FSW_DAT information is stretched and interpolated along with the image data Y, U, V. The FSW_DAT signal contains information to correctly determine the size of the overlap area, but does not indicate which of the fields is the correct field to display. PIP_FSW and FSW_DAT signals can be used together to solve the problem of maintaining interleaving integrity and the correct size of overlap. In normal operation, when a CPIP-type chip is used in 4x3 TVs, the placement of the frames in the RAM is arbitrary. Fields can be aligned vertically or horizontally or not aligned at all. In order to achieve functional compatibility of the widescreen processor, it is necessary that the positions of the picture-in-picture fields are not stored in the memory on the same vertical lines. In other words, half-frames of the PIP may not be programmed using the same addresses for the top and bottom fields. From a programming point of view, it is desirable to store the picture-in-picture fields in the picture memory 350 RAM vertically aligned as shown in Fig. 37.

The PIP_OVL signal controls the output control circuit 321 so that the auxiliary data is displayed when the signal is active, i.e., if it has a logic one level. A block diagram of the PIP_OVL signal generating circuit is shown in FIG. 38. Circuit 680 includes a JK type flip-flop 682 whose output Q is one of the inputs of the multiplexing circuit 688. The output of the multiplexing circuit 688 is an input of the D-type flip-flop 684. The PIP_FSW and SOL (line start) signals are respectively inputs J and K of flip-flop 682. The non-equivalence circuit 686 has two inputs for the fast switching data bits FSW_DATO and FSW_DAT1. Values (1,0) and (0, 1), which are logically exclusive inputs, indicate a valid field as even or odd. Values (0.0) and (1.1) that are not logically exclusive indicate the absence of valid data. The transition from one of the pairs (0,1) or (1,0) to one of the pairs (0,0) or (1,1), or vice versa, indicates a boundary defining the perimeter or overlap of the picture in the picture. The output of the non-equivalence circuit 686 is the second input of the product gate 690. The third input of the product gate 690 is the RD_EN_AX signal, which is a read enable signal for the slave auxiliary memory 354 in the order of arrival. The product gate 690 outputs the PIP_0VL signal. Circuit 680 introduces a one-line delay (one line field delay) from when PIP_FSW becomes active to actually enable the overlap area. This is also counted in the image data path because the in-service memory 354 also introduces a one-line field delay for the image data in the image. The picture-in-picture overlay is therefore perfectly aligned with the image data, even though it is delayed by one line of the field to be programmed in the picture-in-picture circuitry. The RD_EN_AX signal allows the picture in picture to be overlapped only if valid auxiliary data has been read from the operator memory 354 in the arrival order. This is necessary because the data from the memory 354 can be retained even after the reading is finished, which may cause the PIP overlay logic to determine that the overlay is active outside the valid PIP. Enabling picture-in-picture overlay with RD_EN_AX ensures that picture-in-picture data is valid. In accordance with the present invention, the overlay of the small additional image is correctly positioned and sized regardless of how the auxiliary video signal has been expanded, compressed, or interpolated. This applies to signal sources of small picture formats

4x3 and 16 χ 9 and many other formats.

The color components U_PIP and V_PIP are delayed by circuit 36 for a period of time depending on the kind of interpolation of the luminance component at which the U_AUX and VAUX signals are generated as outputs. The respective components Y, U and V of the main and auxiliary signals are combined in respective multiplexing circuits 315, 317 and 319 arranged in the output signal path 312 so as to control the read-out enable signals 354, 356 and 358 with the operator in the order of arrival. The multiplexing circuits 315, 317 and 319 are controlled by the multiplexer output control circuit 321. The multiplexer output control circuit 321 is controlled by the clock signal CLK, the line-start SOL signal, the H_COUNT signal, the vertical blanking adjustment signal, and the output of the PIC processor 320 and the widescreen microprocessor 340. The multiplexed luminance and chrominance components The low-pass filters 361, 363 and 365 shown in FIG. 6 are arranged downstream of the digital-to-analog converters. The various functions of the PIP 320, the gate panel 300, and the data reduction circuit are provided. they are controlled by the widescreen microprocessor 340. The widescreen microprocessor 340 performs responses to the signals of the TV-microprocessor 216 to which it is connected via the serial bus. The serial bus may be four-wire, as shown, having a line for data, clock signals, enable signals, and set signals. The widescreen microprocessor 340 is coupled to the various circuits of the data field 300 via a decoder 310.

In one case, it is necessary to compress the NTSC video signal in 4x3 format using a 4/3 coefficient in order to obscure the aspect ratio of the displayed image. In the latter case, the image may be stretched to perform horizontal zoom functions, which are usually accompanied by vertical zoom. Horizontal zoom up to 33% can be performed by reducing the compression to less than 4/3. A sample interpolator is used to recalculate the incoming video signal to the new pixel positions, since the bandwidth of the luminance component of the video signal (for S_VHS format is up to 5.5 MHz) occupies a significant percentage of the frequency which is 1024 fn for the clock signal of 1024 fn. MHz.

As shown in FIG. 8, the luminance data Y_MN is conveyed by an interpolator 337 arranged in a main signal path 304 that recalculates sample values based on image compression or stretching. The function of the switches or directional selectors 323 and 331 is to reverse the topology of the main signal path 304 relative to the relative position of the in-memory memory 356 in the order of arrival and the interpolator 337. Thus, these switches select whether interpolator 337 is upstream of memory 356. or whether the memory 356 precedes the interpolator 337, which is required for expansion. Switches 323 and 331 are controlled by a direction control circuit 335 which is controlled by a widescreen microprocessor 340. Note that in small picture modes, the auxiliary video signal is compressed when stored in the image memory of 350 RAM, and for practical purposes only expansion. Therefore, similar switches are not needed in the auxiliary signal path 306.

The main signal path 304 is shown in more detail in Fig. 11 (a). The switch 323 is formed by two multiplexing circuits 325 and 327. The switch 331 is formed by a multiplexing circuit 333. The three multiplexing circuits are controlled by a direction control circuit 335 which is controlled by a widescreen microprocessor 340. The horizontal timing and synchronization circuit 339 generates clock signals that control write and reading from the operator's memory in the order of arrival as well as the accumulators 347 and 351 and the multiplexing circuit 353. The clock signal CLK and the signal. Line start SOLs are generated by timing and synchronization circuit 320. The analog-to-digital converter control circuit 369 is controlled by the Y_MN signal, the widescreen microprocessor 340, and the highest valid bit of the UV_MN signal.

The interpolation control circuit 349 generates pixel position (K) values, interpolation compensation filter weighing (C) and CGY clock keying information for luminance component and CGUV for chrominance components. The clock looping information omits (decimates) or repeats the data stored in the operator's memories in the order of arrival, allowing samples to not be written (to create compression) or read several times (to create stretch) at some clock pulses.

Such compression is illustrated in Fig. 11 (b). The LUMA_RAMP_IN line represents linearly increasing luminance data written to the operator memory in the order of arrival. The WR_EN_MN_Y signal is active at the logical one level, which means that if the signal is logical one, the data is written to memory. Every fourth sample is prevented from being registered. The serrated line LUMA_RAMP_OUT represents ascending luminance data as it would be read from the operator's memory in the arrival order if it was not interpolated first. The average gradient of the characteristic of the read luminance data is, as is apparent from Fig. 11 (b), 33% more steeper than the gradient of the characteristic of the recorded data. At the same time, the active reading time required is 33% shorter than the data writing time. This creates a 4/3 compression. Interpolate 337 recalculates luminance patterns written to memory 3 by the operator in the order of arrival so that the read data characteristic is smooth and not serrated.

The stretching can be carried out in exactly the opposite way to the compression. When pressed, the clock enable information is attached to the write enable signal in the form of blocking pulses. As the data is expanded, the clock keying information is coupled to the read enable signal. Thereby, a delay is introduced between the data as it is read from the operator memory 356 in the order of arrival, as shown in FIG. 11 (c). The LUMA_RAMP_IN line represents the data before it is written to memory 356, and the wavy line LUMA_RAMP_OUT represents the data when it is read from the memory 356. In this case, the interpolator that is downstream of memory 35 recalculates the sampled data from undulating to smooth . The data must be delayed in the case of stretching when reading from the memory 356 and during clocking in the interpolator 337. This is different from the compression, when the data is clocked continuously when passing through the interpolator 337. In both cases, i.e. when compressed and expanded, the clock keying operations can be easily performed synchronously, i.e., using the ramp edges of the 1024 fa system clock pulses.

This topology of luminance signal interpolation has a number of advantages. Hourly keying operations, i.e. data dropping and repeating, can be performed synchronously. If the switchable image data topology was not used to interchange the interpolator and memory positions, the read or write clock pulses could be doubled or omitted for omitting or repeating, meaning that two data points would have to be written or read in a single clock cycle. The resulting circuitry could not operate synchronously with the system clock pulses, since the write or read frequency would have to be twice as high as the system clock signal. In addition, a switchable topology requires only one interpolator and one operator memory in the order of arrival, which perform both compression and expansion. If the described video signal switching was not used, double clocking could only be avoided by using two operator memories in the order of arrival that would provide both compression and expansion. The expansion memory would have to be located in front of the interpolator and the compression memory downstream of the interpolator.

One condition for proper circuit operation is that the number of data samples written to the operator's memory in the order of arrival must be equal to the number of samples read from the memory for that row for each horizontal row. If the number of recorded and read samples were not the same, the image of the main channel would be. has been greatly skewed as a result of reading and writing line by line. This requirement is due to the fact that the operator's memories in the order of arrival arranged in the main channel are reset once per field. First, the write sync is reset by the vertical sync pulse of the main signal, and then the read pointer is reset one row later.

For read / write indicators, a different number of clock cycles may be required to move across the same number of locations, due to the fact that both image data is compressed and expanded. To ensure that the number of written data samples is always equal to the number of data samples read, regardless of the mode, three register values and two control values are used to generate read and write permission signals in operator memories in the order of arrival for the components Y and UV of the main signal. signals. The two values of the registers WR-BEG-MN and RD_BEG_MN, generated by the wide-angle microprocessor 340, determine the horizontal line position at which to read and write, in conjunction with the H_COUNT value of the number of pixels in the horizontal direction. H_COUNT is a 10-bit counter value used to determine the position of a pixel during a line period. Counter contents are cleared by a SOL start signal. The SOL signal is a one-hour pulse pulse and sets the horizontal H_COUNT counter at the beginning of each line to zero. . The SOL pulse is nominally aligned with the face of the horizontal synchronization component.

The third value of the LENGTH register is used to load the upper eight bits of the 10-bit counter to determine the number of data samples that were actually written to or read by the operator in the order of arrival. The bits of the register value are inverted and the least two valid bits are brought to logical one, resulting in a value of _LENGTH-1. The symbol A that precedes the signal designation indicates a logical inversion. Thus, if the counter is overfilled, the transferred transmission is brought to logical one and the required number of samples is written or read. The actual number of pixel elements written or read is LENGTH x 4 because the register is loaded into the upper eight bits of the counter. The effect of the clock keying is initiated by the keying of the counter access signal. That way it can be. the enable signal for the counter is also used as the enable signal for the operator memory in the order of arrival, ensuring that the number of written or read samples is always LENGTH x 4, regardless of the mode.

Giant. 11 (d) depicts one of three identical circuits used to generate write and read enable signals for operator memories in the order of arrival for storing the Y and UV components, which are designated WR_EN_FIFO_Y (case 1), WR_EN_FIFO_UV (case 2), RD_EN_FIFO_Y and RD_EN_FIFO_UV. When stretching, the RD_EN_FIFO_Y and RD_EN_FIFO_UV signals may be the same and designated as RD_EN_FIFO_Y_UV (case 3). Circuit 1100 is first explained for case 1. Circuit 1100 compares the WR_BEG_MN signal with the upper eight bits of the H_COUNT value in the comparator 1102. The H_COUNT value is a 10-bit counter value used to determine the pixel position in a row period. The counter is cleared by a SOL start signal. The SOL signal is a one-hour pulse pulse and sets the horizontal H_COUNT counter at the beginning of each line to zero. The SOL pulse is nominally aligned with the face of the horizontal synchronization component.

The output of the comparator 1102 is delayed by the circuit 1118 and compared in the NAND gate 1104 with an inverted but not otherwise delayed version of itself. The NAND gate output 1104, which is an active LO signal of one clock cycle width, is the input LDn to the 10-bit counter 1106. The LDn input is also used to input the leading edge of the system clock signal to the 10-bit counter 1106. The LENGTH signal bits are inverted The LENGTH value is used to load the upper eight bits of a 10-bit counter to determine the number of data samples that were actually written to the operator memory in the order of arrival. The output of the inverter array 1110 is routed to the highest bits of the counter 1106 by the LOAD input. The least two valid bits are put into a logical upper level state. The effective value is _LENGTH-1. In order to set aspect -1 of the LENGTH-1 value, counter 1106 is stopped by the transfer signal RCO, which occurs one clock cycle before the length counter 1106 reaches zero. The clock keying information is then added to the NOR gateway 1112 with the RCO conversion transmission signal. The same enable signal is inverted by the gate 1116 and used as the enable signal for the operator memory in the order of arrival. This memory and counter 1116 are thus accessed in exactly the same way, thereby ensuring the correct number of samples to be written. In case 2, the signal WR_BEG_MU is also compared with H_COUNT. However, the CGUV_WR signal is used to produce the output signal WR_EN_FIFO_UV. In case 3, the RD_BEG_MN signal is compared to H_COUNT and the CGY_RD signal is used to produce the output signal RD_EN_FIFO_Y_UV.

The processing of the chrominance components for the main channel image can be carried out in several variants of the arrangement according to the invention. One alternative topology is the arrangement shown in Figures 8 and 11 (a) and explained in connection with Figures 52-55.

13 and explained with reference to FIG. 51. The UV signal path 530 is shown in FIG. 13 as a block diagram. Lane 530 is very similar to the optional luminance data topology in the main signal path 304 shown in FIGS. 8 and 11fa). The most significant difference is the use of the adaptation delay circuit 554 instead of the interpolator 337. Multiplexer circuits 534, 536 and 53_8.

Another topology for the main operator image in the order of arrival precedes the adaptation delay circuit 540, or the path in which the adaptation delay circuit 540 precedes the memory 358. The multiplexing circuits are controlled by the direction control circuit 532. The output of multiplexing circuit 538 is divided into signals U_OUT and V_OUT by demultiplexing circuit 353.

If the interpolation system performs image compression, the data samples must be discarded before being written to memory 358. This is a problem with multiplexed I / O data. If the data stream Y were discarded by the same clock keying pulses as the data stream Y, the UV components would not rotate consistently in the order of U, V, U, V ... etc. For example, if only a sample U was discarded before writing to memory 358, the sequence would be U, V, U, V, V, U, V, etc. Therefore, a second clock clocking signal is required. This signal is called CGUV (or _CGUV if it is logically inverted). This signal is only used during compression, has only half the frequency of CGY pulses and always rejects a pair of UV samples. The compression results in a ratio of 8/5 are shown in Figures 51 (a) and 51 (b).

From this example it is clear how the CG signals for Y (_CGY) and UV (_CGUV) differ from each other. If the _CGY and _CGUV signals are in the logic 1 state, the samples are discarded. The _CGUV signal always starts with sample U and ends with sample V. The UV pair is thus discarded together, avoiding situations in which component V of one pair would be discarded together with component U of the following pair. A comparison of how the UV and Y data is read from respective operator memories 358 and 356 in the order of arrival is shown in Fig. 51 (a> and 51 (b). Obviously, the UV data is skewed relative to the Y data This is due to the fact that the U / V indication data is not stored in the operator's data flow in the order of arrival, but the UV skew slightly deteriorates the color component, but this deterioration is never worse than the 4: 1 system: The effective Nyquist frequency of the UV components is reduced to 2 MHz due to the rejection of the UV pairs - which is still sufficient for the sources of the wide color component I, resulting in maintaining high quality color components. signal even during the removal of UV pairs.

Compressing the image data requires that the clock keying signals to be written to the memories 356 and 358 in the order of arrival are different for the signal paths Y and UV. In principle, samples U and V must be discarded in pairs, since once the sample is discarded, the status information of that sample (whether it was a U or V sample) is lost. For example, if the ninth bit for transmitting the UV state information were added to the memory 358, individual samples U and V could also be discarded. Reading the data from the memory 358 could then properly categorize the interpretation of the state of the ninth bit. However, since this sorting information is not used, the consequence is that UV data must be. being discarded in pairs, and subsequent sorting after reading the contents of memory 358 can be very simple.

Sorting discarded UV pairs requires only a one-bit counter. This counter is synchronously set to a U (zero) state for a clock cycle that begins reading the memory 358 with the operator in the order of arrival. This one-bit counter is accessed by the RD_EN_MN signal, which controls the read-out of the main memories 356 and 358 in the order of arrival. In press mode 65, the HDEN_MH signal is continuously in the logical 1 state from start to end of reading, in each horizontal line. The resulting UV_SEL_OUT signal is an alternating U / V component indicator that drives the demultiplexer circuit 353 selection line. In this way, the UV samples are successfully sorted after reading from the memory 358, even if the UV component synchronization information could not be stored in the memory 358 for later issue.

In performing the stretching of the image, writing to the operator memory 356 and 358 is uninterrupted in the order of arrival from start to end. Reading from these memories is delayed and samples are retained (repeated) when read from memory. This retention or repetition of the samples is performed by means of the clock read-out information that is part of the RD_EN_MN signal and its complement _RD_EN_MN.

Here it is important to point out an important difference compared to compression. The status of the UV sample is known when it is read from the operator's memory 358 in the order of arrival. The UV data is written to the memory 358 with constant alternation of the components U, V, U, V ... etc. When the data is read from memory 358 and then interrupted by delays, a one-bit counter is also paused, which generates a UV_SEL_OUT signal to account for the fact that the data in the memory has been retained. This ensures proper sorting by the demultiplexer circuit 353.

The one-bit counter is paused at the right time because the RD_EN_MN signal is sent to its opening input. This ensures that when the memory 358 is paused, the UV_SEL_OUT signal is also paused. Executing the stretching does not require that the read signals of the Y and UV components read for the handlers 35 and 35S in the order of arrival are separate because the clock read signal for data

The UV, which is the CGUV signal, is now identical to the clock read-out signal for the Y data, the CGY signal. Expansion is easier to perform than compression. In addition, the Nyquist frequency of the chrominance component is not degraded when stretched, and the 2: 1: 1 signal quality is fully maintained.

The described topology of the multiplexed color component has a number of advantages. The method is efficient and ideally matched to the operation of the broadband brightness raster mapping system. Circuit complexity is minimized while maintaining a high level of color signal quality. These advantages are partly due to the following improvements. The UV pairs are discarded at the memory input 358 for the UV components. This eliminates the need to keep clock-wise information through this memory, which would require the operator memory in the order of arrival to be 1 bit wider than the true accuracy of the UV data. The UV component interpolator, which would operate analogously to the interpolator 337, is replaced by a delay matching circuit. This eliminates a very complex mathematical function. In addition, by creating the gate array in an integrated circuit, approximately 2000 gates are saved. Finally, even in the worst case, the quality of the UV signal is not reduced below the 4: 1: 1 color channel arrangement (Y, U, V) when compressed and remains at a 2: 1: 1 ratio after stretching.

8 and 11 (a), no delay adaptation circuit is required. Instead, the operator memory in the order of arrival is controlled in a way that achieves the same results. Giant. 52 (a) and 52 (b) illustrate portions of the luminance and color paths in the gate array 300. FIG. 52 (a) represents an optional topology corresponding to the compression of the image in front of the memory

356, interpolator 337 is included. In the color path, only the operator's memory 353 in FIG. 52 (b) is shown in the order of arrival.

Giant. 53 (a) to 53 (1) illustrate an example of image compression. For the purposes of this example, it is assumed that the luminance and color components were correctly adjusted before the analog-to-digital conversion and that the interpolator has a delay of 5 clock cycles, although the actual interpolator delay is 20 clock cycles and the luminance and chrominance signals are not time aligned. The UV_MUX selection line for the analog switch or demultiplex circuit 344 is an 8 MHz signal derived by dividing the clock pulses of the system by two. As shown in Fig. 53 (a), at the beginning of a line having a width of one clock pulse, the SOL pulse sets the UV_MUX signal synchronously to zero at the beginning of each horizontal video line, as shown in Fig. 53 (b). The UV_MUX signal then flips its status in the horizontal line with each clock cycle. Since the line length represents an even number of clock cycles, the state of the once triggered UV_MUX signal will still flip continuously between levels 0 and 1. The UV and Y data flows from the A / D converters 346 and 342 are shifted because each of the A / D converters has delayed one hour cycle. To compensate for this data shift, the clock clutter information CCY shown in FIG. 53 (e) and CGUV shown in FIG. 53 (f) must likewise be delayed from the interpolation control circuit 349 (see FIG. 9). The UV_FIFO_IN data of the UV component shown in Fig. 53 (d) and stored in the operator's memory 353 in the order of arrival is ahead of the Y-FIFO_IN .. data of the Y component shown in Fig. 53 (c) as the luminance data passes through the interpolator

337 and color components are not interpolated. The reading of the UV_FIFO data from the UV component memory 358 is delayed by 4 hours as shown in Figure 53 (h) relative to the reading of the Y_FIFO data from the memory component 356 shown in Figure 53 (g), thereby matching the above displacement. This is given by a delay of four hours between the rising edge of the read permission signal RD_EN_MN_UV for the UV component storage shown in Figure 53 (j) and the rising edge of the read permission signal RD_EN_MN_Y for the storage component Y shown in Figure 53 (i) . The resulting data streams Y and UV are shown in Figures 53 (k) and 53 (1). The most unfavorable non-matching of the Y and UV components is 1 hour cycle, which is the same result that can be achieved by a more complex system, such as one in which the relative memory positions with the operator can be interchanged in the order of arrival and delay adaptation circuit.

It should be noted that reading from the memory of the UV components 358 is delayed by 4 hour cycles in the exemplary embodiment, although the interpolator delay is 5 hour cycles. The most preferred setting of the number of hourly cycles of the UV component memory delay is an even value that is not greater than the interpolator delay. Expressing in computer language C and marking the delay as DLY_RD_UV:

DLY_RD_UV = (int) ((int) INTERP_DLY / 1) *. 2, wherein INTERP_DLY is the interpolator delay expressed as the number of clock cycles.

In practice, the interpolator may have a delay of 20 clock cycles (INTERP_DLY = 20) and the luminance and chrominance components are not adjusted. The luminance and chrominance signals can be offset in many ways. The colorant components are usually delayed beyond the luminance signal due to demodulation. The raster mapping system according to the invention has the advantage that any non-adaptation of the Y and UV components can be overcome by delaying the interpolator. In the case of image compression, the DLY_RD_UV delay in reading the UV component memory 358 can be set in the range of 0 to 31 hours cycle. Since the luminance signal interpolator 337 has an inherent delay of 20 clock cycles and each clock cycle has a length of approximately 62 nanoseconds, the raster mapping circuit described can make corrections for the chrominance delay relative to the luminance signal up to 1.24 microseconds (62 nanoseconds x 20). In addition, the raster mapping system can perform luminance signal delay corrections relative to the chrominance component up to 682 nanoseconds (62 nanoseconds x [31-20]). This provides an extremely high degree of flexibility for connecting external analog video circuits.

The same different delay as is performed by the interpolator in the luminance channel when the image is compressed can also be realized when the image is stretched. Giant. 54 (a) and 54 (b) show portions of the luminance and color components of the signal in the gate array 300. FIG. 54 (a) represents an optional image stretching corresponding topology where interpolator 337 is downstream of the operator memory 356 in the arrival order. The path of the UV component containing the operator's memory 358 in the arrival order remains unchanged. In the image stretching example shown in Figures 55 (a) to 55 (1), it is assumed that the interpolator has a delay of 5 clock cycles. The line-start signal SOL, the UV_MUX signal, the luminance data stream input Y_IN to the memory 356 and the chrominance data stream input UV_IN to the memory 358 are shown sequentially in Figures 55 (a) to 55 (d). In order to correct time equalization of Y and UV data, write (DLY WR_Y) to the component Y memory 356 may be delayed or read (DLY RD_UV) from the UV component memory 358 may be delayed. Delayed reading from the UV component memory 358 is permissible in this case because the memory does not require interpolation coefficients K and C. In the image compression mode, the write could not be delayed as this would tune the alignment of the coefficients K, C with respect to the clock clock information. and the brightness portion of the interpolation would be violated. The correct setting of the DLY_WR_Y value, which delays writing to the Y component by 4 hours cycles, is indicated between the leading edge of the WR_EN_MN_UV write permission signal shown in Fig. 55 (f) and the rising edge of the WR_EN_MN_Y write permission signal of component Y shown in Fig. 55 (g). The clock keying signal CG and the output signal Y_FIFO are shown in FIGS. 55 (i) and 55 (j) respectively. The resulting time alignment of the components Y and UV is shown by the relative positions of the data streams Y_OUT and UV_OUT of Figs. 55 (k) and 55 (1).

The ability of the raster mapping system to compensate for external misalignments of luminance and chrominance components is equally great for expanding and compressing the image. This is a very important function of the raster mapping system since it eliminates the need to use a variable delay line at the input of the luminance channel to adjust the luminance and chrominance component. The choice of a particular topology may be based on a number of factors, and other circuits may be considered.

The auxiliary signal interpolation takes place in the auxiliary signal path 306. The picture-in-picture circuit 301 controls half the frame memory T> for storing the 6-bit component Y and the components U, V of the incoming image data at a ratio of 8: 1: 1, which is already a RAM image type 350. The .350 image memory stores two fields of image data in multiple memory locations. Each memory location stores eight bits of data. One 8-bit brightness Y pattern (sampled at 640f _s ) and two additional bits are stored in each 8-bit memory location. The two other bits contain either the fast switching FSW_DAT data or a portion of the sample U or V (sampled at SO SO-rf). The FSW_DAT values indicate which field type was written to the RAM. Since two RAMs of data are stored in the RAM 350 and during the display period the RAM 350 is read completely, both fields are read during image decomposition. The picture-in-picture circuitry 301 determines which of the half frames will be read out of memory for display using fast switching data. The picture-in-picture circuitry 301 always reads a field of the opposite type to the field currently being written to overcome the image tearing problem. If the field being read is of the opposite type to the field currently being displayed, the even field stored in the image RAM of 350 RAM is converted by erasing the upper row. As a result, a small image preserves proper interleaving without tearing the movement.

The timing and synchronization circuit 320 generates read, write, and enable signals required for operation of the memory memory 354, 356, and 358 in the order of arrival. Operator memories in the order of arrival for the main and auxiliary channels are made available to write data of those portions of each line of the image that are required for subsequent display. Data is written from either the main or auxiliary channel, but not both, which is necessary to combine the data from each source into the same line or lines of the image. Memory 354

72, in the order of arrival, arranged in the auxiliary channel, is written synchronously with the auxiliary video signal, but is read synchronously with the main video signal. The main picture signal components are written to the memories 356 and 358 synchronously with the main video signal and read from the memories are also synchronous with the main video signal. The frequency of switching between the main and auxiliary channels is a function of the specific special effect selected.

The creation of various special effects, such as cropped images side-by-side, is accomplished by controlling read and write permission signals for the line memory with the operator in the order of arrival. The procedure for this display format is shown in FIGS. 7 and 8. In the case of cropped images side-by-side, the write enable control signal WR_EN_AX for the memory 354, with the 2048x8 arrival order, arranged in the auxiliary channel active after (1 / 2) x (5/12) = 5/12, or approximately 41% of the active video line period (after acceleration) or 67% of the sub-channel active line period (before acceleration), as shown in Figure 7. 33% (approximately 67% active image) signal stretching by 5/6 interpolation. In the main video signal shown at the top of FIG. 8, the write-enable control signal WR_EN_MN_Y is active for memories 356 and 358, with the order of arrival of 910 x 8 after (1/2) x (4/3) = 0, 67 or 67% of the active image line period. This corresponds to a crop of approximately 33% and a 4/3 compression ratio performed in the main channel image by the operator memories in the order of arrival of 910 x 8.

In each of the operator's memories in the order of arrival, the data is stored in a buffer manner for reading at a particular point in time. The active time area in which data can be read from each memory is determined by the display format selected. In the side-by-side cropped image mode shown, the main channel image is displayed in the left half of the screen and the auxiliary channel image is displayed in the right half of the screen. As shown, the signals of the individual arbitrarily selectable portions of the image have different waveforms for the main and auxiliary channels. The control read signal RD_EN_MN in the 910 x 8 in-hand order of arrival is active for 50% of the active image line period, starting from the beginning of the active image immediately after the rear dwell of the video signal. The read grant control signal RD_EN_AX for the auxiliary channel is active for an additional 50% of the active image line period, beginning at the rear edge of the RD_EN_MN signal and ending at the beginning of the front delay of the main channel video signal. The write enable control signals are synchronous with the respective input data of the operator memory in the order of arrival (main and auxiliary), while the read control enable signals are synchronous with the main channel video signal.

The display format shown in Fig. 1 (d) is particularly needed since it allows the creation of two nearly full images arranged side by side. This display is particularly effective and suitable for a wide screen format, such as 16x9. Most NTSC signals are in 4x3 format, which corresponds to a 12x9 ratio. The same 16x9 screen can hold two images transmitted NTSC and 4x3 formats, either with 33% cropping, or 33% squeezing and introducing · aspect ratio distortion. Depending on the user's preference, any cropping to aspect ratio distortion ratio can be set from 0 to 33%. Two side-by-side images can be created, for example, by squeezing 16.7% while simultaneously cropping by 16.7%

Operation can be described using generally expressed acceleration and trimming ratios. The display means may be considered with a ratio of width and height of the display format expressed as Μ: N, the source of the first video signal may then have an aspect ratio of the display format A: B and the source of the second video signal is considered with an aspect ratio of the display format C: D. the signal may optionally be accelerated by a coefficient in the first range, from about 1 to (M / N - A / B), and optionally trimmed by a coefficient in the second range, from about 0 to [(M / N - A / B) -1] . The second video signal may optionally be accelerated by a coefficient in the third range, from about 1 to (M / N - C / D), and optionally trimmed using a coefficient in the fourth range, from about 0 to [(M / N - C / D) - 1].

The horizontal display time for a 16x9 screen is the same as for a 4x3 screen because the nominal line length is 62.5 microseconds in both cases. Therefore, the video signal transmitted in the NTSC standard must be accelerated by a 4/3 coefficient to maintain the correct aspect ratio without distortion. 4/3 is calculated as the ratio of two display formats: 4/3 »(16/9) / (4/3)

Variable interpolators are used to accelerate the video signals in accordance with embodiments of the invention. In the past, operator-operated memories were used to perform similar functions, having different clock frequencies at the inputs and outputs. If, for comparison, two NTSC signals of 4 x 3 formats are displayed on a single 4 x 3 screen, each of the images (or a combination thereof) must be distorted or cut by 50%. There is no need for an acceleration comparable to that required for widescreen imaging.

The semi-frame synchronization system for preventing read / write co-pointers and maintaining interleaving integrity is explained in more detail with reference to FIGS. 28-36. The picture-in-picture processor operates by sampling auxiliary video data with 640fn clock pulses coupled with the horizontal synchronization component of the incoming video assist signal. This function allows the orthogonally sampled data to be stored in a RAM image 350. The data from the RAM image must be read at the same 640 fn frequency. Due to the generally asynchronous nature of the main and auxiliary video signal sources, data from RAM cannot be orthogonally displayed without modification. To facilitate synchronization of the slave signal with the main signal, a row memory with independent read and write clocks is arranged in the slave signal path after the output of the video RAM 350.

As shown in more detail in FIG. 28, the output of the RAM image memory 350 is the input of the first of the two four-bit accumulators 352A and 352B. The VRAM_OUT output is arranged in four-bit data blocks. The four-bit accumulators are used to combine the auxiliary signal into eight-bit data blocks. The accumulators also reduce the clock frequency to give from 1280 f _H. to 640 .. f _H. The eight-bit data blocks are written to the operator's memory 354 in the order of arrival at the same clock frequency of 640 hodinových, which is used to sample the auxiliary image data when it is stored in the 350 RAM image memory. The size of the operator's memory 354 in the order of arrival is 2048 x8.

The reading of the 8-bit data blocks from the memory 354 is performed by a display clock signal at a frequency of 1024 fsz which is coupled to the horizontal synchronization component of the main video signal. The basic configuration, which uses multiple line memory with independent input read and write clock signals, allows orthogonal display of data that has been sampled orthogonally. The eight-bit data blocks in the multiplex circuit 355 are divided into six-bit luminance samples and differential samples. The data samples can then be interpolated as required for the desired aspect ratio of the display format and written as the output of the image data.

Since reading and writing of data from the operator's memory in the order of arrival arranged in the auxiliary channel are asynchronous, there is a possibility of collision of read / write pointers. These collisions can occur if old data is read from memory before new data can be written to that memory. Pointer collisions can also occur if memory is overwritten with new data before old data could be read from it. It is therefore necessary to maintain the integrity of interleaving.

First of all, a sufficiently large memory must be selected to avoid collisions between the read and write pointers in the operator's memory in the order of arrival arranged in the auxiliary channel. When displaying an image with the normal aspect ratio of the format, cropped by 33%, the operator's auxiliary memory, which is 2048 x 8, is capable of storing 5.9 lines of image data, which is calculated as follows:

N = (2/3) X (0,82) X (640) = 350 L = 2048/350 = 5,9 where N is the number of rows, taking into account the 82% active row period, and L is the length of each row. It has been found that it is not advisable to use higher advance speeds than 2 lines per field. Thus, a five-line memory with an operator in the order of arrival, sampled according to the invention for an auxiliary channel, may be sufficient to avoid collisions of read and write pointers.

The use of operator memory in the order of arrival in the auxiliary channel can be illustrated as shown in Figure 29. Figure 30 is a block diagram of a simplified D-flip-flop circuit for generating line delay (Z ^-1 ) and zero pulses for reading in the operator's memory 354 in the order of arrival arranged in the auxiliary signal path. At the beginning of a new field of the main signal, the write pointer is set to the starting point of the operator memory in the order of arrival. This reset pulse is denoted WR_RST_AX combination of signals sampled using V_SYNC_MN H_SYNC _AX _r. In other words, the pulse WR_RST_AX occurs at the first horizontal synchronization pulse of the auxiliary video signal which is provided after the vertical synchronization pulse of the main signal. Two horizontal lines of the main signal later set the read pointer to the starting point of the memory 354 with the operator in the order of arrival. The corresponding reset pulse is denoted RD_RST_AX and appears at the third horizontal sync pulse of the main video signal, which is provided after the vertical sync pulse of the main signal, or, in other words, at the second horizontal sync pulse of the main signal that appears after pulse WR_RST_AX.

Since the main and auxiliary video signals are asynchronous, there is some ambiguity in exactly where the write pointer is located when the read pointer is reset to zero. It is known that the write pointer is ahead of the read pointer by at least two lines. However, if the horizontal synchronization signal of the auxiliary channel is higher than the frequency of the horizontal synchronization signal of the main channel, then the read indicator will have an advance outside the shown two-line index. This implies that the collision of the pointers is avoided for all signals with an advance speed of less than 2 lines per field. The in-service memory 354, corresponding to the auxiliary channel, is divided into five line sections by means of suitably timed read / write reset signals.

In this scheme, read and write pointers are initiated at the beginning of each of the displayed fields so that they are separated by at least two lines.

If the operator memory in the order of arrival were not five full lines in length, the system would sacrifice the memory distance from the write pointer to the read pointer. This is the case with different compression modes, for example 16%:

N = (5/6) X (0.82) X 640 = 437 L = 2048 (5 X 437) »4.7

In these cases, the length of the operator memory in the order of arrival is less than five lines. When pressed by 16%, the actual memory length is 4.7 lines. A factor of 0.8 in the equation for N when compressed by 33% expresses the functional limitation of the CPIP.

Since the read and write reset signals of the handled memory are separated by a minimum of two lines of active image, the victim79 and gate array 300 of the NTSC are executed at 262.5 lines per load, always allowing the read pointer to catch up with the write pointer. In addition, only 30% of the image line is considered active because the picture-in-picture processor is not able to store more than 512 image samples in the RAM picture 350. In practice, however, a good active image line is still provided. In these cases, the advance rate is sacrificed for more visible image content. In addition, the auxiliary image is more distorted. In the worst case, an advance of one line per field can be tolerated between the main and auxiliary video sources. This is still more than necessary for most video sources, and the advance speed tolerance is sacrificed in those additional modes that are expected to be used least.

Another problem stemming from asynchronous reading and writing of the operator memory in the order of arrival is maintaining the interleaving integrity of the auxiliary channel image. Since the screen is coupled to the main video channel, the type of field currently displayed, that is, the upper or lower field, is determined by the main signal. The type of field that is stored in the RAM of 350 RAM and ready to be read at the beginning of the main channel field may or may not be the same as the type of field displayed. Thus, it may be necessary to change the type of auxiliary fields stored in the RAM picture 350 to adapt it to the main channel image.

The PIP 320 also quantizes half a frame of a 263-line top-field signal (sometimes called even fields). This is due to the fact that the vertical sync component is sampled by the pulses representing the horizontal syn80 chronological component as shown in the diagram in Figure 31. The upper and lower field indicators are 1 for the upper half of the frames and 0 for the lower fields. The lower half-frames contain the even lines 2 to 262. In Fig. 32, the first U / L MAIN SIGNAL field indicator represents the field type of the main video channel. The HSYNC_AX signal represents the horizontal synchronization components for each row of the auxiliary channel.

The half-frame U / L (A) indicator represents the half-frame type stored in the 350 RAM image memory if each auxiliary channel line was written normally. The term normally used herein means that odd lines 1 to 263 are written to the RAM 350 when the upper field is being received and decoded. The field type U / L (B) indicator represents the field type stored in the image RAM 350 if the first line of the field is not written to the memory during reception of the top field. Instead, the first line is actually appended to the last line (number 262) of the bottom field. In this way, the frame type is effectively inverted, since row 2 will be the first row displayed and row 3 will be the second row displayed. The received upper field now becomes the lower field and vice versa. The U / L (C) field type indicator represents the field type stored in the RAM type image memory 350 when the last line of the upper field is added to the memory 350 during the reception of the lower field. This again effectively reverses the field type, since row 263 will be the first row displayed and row 1 will be the second row displayed.

Adding and subtracting rows in modes B and C does not deteriorate the image of the auxiliary channel because those lines appear during vertical reverse or overlap. The order of the displayed lines is shown in Figure 34, where the solid lines represent the lines of the game field and the dotted lines of the lines of the lower field.

As the main and sub-channel signals are avoided, the U / L MAIN SIGNAL indicator will be shifted to the left or right relative to the U / L (A, 3, C) type of sub-channel type field indicators. At the position shown in the diagram, data should be written to the 350 RAM image memory using mode A because the decision edge is in area A. Mode A is convenient because when the PIP receives a vertical sync component, it writes to the image the RAM type 350 of the same type of field as will be required by the display unit for reading from the RAM picture 350 triggered by the V_SYNC_MN signal (the vertical main channel synchronization component). Since the signals are prevented, the mode will change according to their relative positions. The valid modes are shown graphically at the top of Fig. 32 and shown in the table of Fig. 33. There is an overlap between modes B and C, since mode C is valid for most of the time that mode B is in effect, and vice versa. This applies to all 262 lines except two lines. If both modes 3 and C are valid, either of them can be used.

A block diagram of the interleaving integrity circuit 700 of the present invention is shown in FIG. 36. The output signals of the circuit 700 are reset write and read control signals for video RAM 350, a memory 354 in the order of arrival arranged in the auxiliary signal path, and a memory 356 with the arrival order arranged in the main signal path, as shown in FIG. 28. The main picture signal field type is determined by the pair of VSYNC_MN and HSYNC_MN signals. The auxiliary video signal field type is determined by the corresponding pair of VSYNC_AX and HSYNC_AX signals. Each pair of signals has a predetermined phase relationship that is set in the gate array 300. This relationship is shown in Figures 35 (a) to 35 (c), which refer to both signal pairs. In all cases, the HSYNC signal has a square shape whose leading edges correspond to the beginning of the horizontal line of the signal. In all cases, the VSYNC signal has only one leading edge per half-frame, which corresponds to the beginning of the vertical fields of the signal. The relationship between the leading edges of the respective signal pairs is controlled by the circuitry 700 to determine the steps that are necessary (if at all) to match the types of auxiliary signal fields and the main signal. To avoid ambiguity, the leading edges of the main signal pair are never narrower than 1/8 of the horizontal line period. The leading edges of the auxiliary signal pair are never narrower than 1/10 of the horizontal line period. This prevents mutual instability of the leading edges. This relationship is provided by the gate array timing circuits.

The main pair of VSYNC_MN and HSYNC_MN signals are inputs of the first half-frame type determination circuit 702, which includes two D-type flip-flops. In one case, the HSYNC-MN signal is sampled by the VSYNC_MN signal, The output of this flip-flop is the UL_MN indicator of the upper and lower fields for the main signal, which can have a logical one for the upper type of fields and a logical zero state for the lower type of fields, but this association is arbitrary. In the second case, the VSYNC_MN signal is sampled by the HSYNC_MN signal in the same manner as in flip-flop 852 explained in connection with FIG. 30. The respective output Vh of circuit 702 is a vertical output synchronized with the horizontal output.

The auxiliary pair VSYNC_AX and HSYC_AX are inputs of the second field type determining circuit 710, which also includes two type D flip-flops. In one case, the HSYNC_AX signal is sampled by the VSYNC_AX signal, which means that V5YNC_AX is a clock pulse input. The output of this flip-flop is an UL_AX indicator of the upper and lower signals for the auxiliary signal, which may have a logical one for the upper type of field and a logic zero state for the lower type of field, but this assignment is arbitrary. In the second case, the VSYNC_AX signal is sampled by the HSYNC_AX signal, in the same manner as in the flip-flop 352 explained in connection with FIG. 30. The respective output Vh of circuit 710 is a vertical output synchronized with a horizontal output.

The determination of the field type for both signals is shown in Figures 35 (a) to 35 (c). If the edge edge slope occurs in the first half of the horizontal row period, as in Fig. 35 (b), the field is of the lower type. If the edge edge slope occurs in the second half of the horizontal row period, as in Fig. 36 (c), the field is of the upper type.

Output V - for the main signal and the HSYNC_MN signal are delay circuit inputs 704, 706, and 708, which create horizontal line period delay to provide the correct phase relationship of the output signals WR_RST_FIFO_MN, RD_RST_FIFO__MN, and RD_RST_FIFO_AX. The delay that can be performed by the D-type flip-flops is similar to that shown in Figure 30. A delay of two to three horizontal line periods is created between the write and read indicators.

The UL_MN indicator of the upper and lower fields corresponds to the U / L MAIN SIGNAL signal shown at the top of FIG. 32 and is one input of comparator 714 designated UL_SEL. The other inputs of the comparator 714 are the outputs of the UL_AX signal generator 712. The test generator 712 has a UL signal input UL_AX that is the output of circuit 710. Another test generator input 712 is the HSYNC_AX signal as a clock signal. The outputs of the test generator 712 are the U / L (A), U / L (B), and U / L (C) signals shown at the bottom of Figure 36 and corresponding to the three possible modes A, B, and C. L (A),

U / L (B) and U / L (C) are compared to UL_MN at the time of passing the U / L_MN signal edge, which is also shown in Fig. 32. If UL_MN agrees with U / L (A), types of fields, and no measures are required to maintain interleaving integrity.

If UL_MN matches U / L (B), the field types are not matched. To maintain interlace integrity, it is necessary to delay the writing of the upper fields by one line. If UL_MN matches U / L (C), the field types are also not matched. In order to maintain the interleaving integrity, it is necessary to introduce a one-line leading of the lower-field writing.

The result of this comparison is the input of the SEL selection circuit 718 denoted by RST_AX_SEL. Other inputs * of this circuit are three vertical sync signals

RST_A, RST_B, and RST_C generated by generator 716 designated RST_AX_GEN. The three synchronization signals have different phases from each other to take corrective action to maintain interleaving integrity according to the output of the comparator 714. The delay circuit 722 resumes synchronization of the selected synchronization signal with the auxiliary video output signal, thereby producing a WR_RST_VRAM__AX signal. The delay circuit 720 performs a similar function and generates signals RD_RST_VRAM_AX and WT_RST_FIFO_AX. As shown in FIG. 32, modes B and C overlap most of the time. In fact, only two of every 525 comparisons will require only one of Mode 3 or Mode C and not any of them. The comparator 714 may be arranged such that, with the cbou modes in effect, it prefers mode C over mode B. This choice may be arbitrary or may be due to other reasons resulting from circuit arrangement.

The circuit 111 shown in Figure 4 (b) is a modification of the circuit 11 of Figure 4 (a) in which the liquid crystal display system is arranged. The raster mapping methods used in the digital signal processing described above may also be suitable for liquid crystal display systems. The pixel map generated by the matrix address generator 113 is based on the digital multiplexed output Y_MX, U_MX, and V_MX of the gate array 300. The matrix address generator 113 drives the liquid crystal display means 115.

Data reduction or compression and data recovery or expansion may be performed in alternative ways according to various widescreen television arrangements of the invention. In one alternative, an encoded signal is added to the auxiliary signal by the resolution control circuit 370, which is subtracted from the resolution control circuit 357 again. The resolution control circuit 370 may also be considered a data reduction circuit, and the resolution control circuit 357 may be considered a data recovery circuit. Thus, in this resolution control method, the on bit signal is coded by om bit bits, neglecting the least significant bits. . The one-bit coded signal subtraction ob86 and the corresponding one-bit coded signal subtraction circuit are shown in Figs. 39 and 40. The two-bit coded signal addition circuit and the corresponding two-bit coded signal subtraction circuit are shown in Figs. 41 and 42.

As shown in FIGS. 39 and 40, the summation circuit 372 combines the n-bit signal with a one-bit code sequence. The preferred single bit sequence is 01010101, etc. After adding the code sequence to the n-bit signal, circuit 374 discards the least valid bit. The encoded n-1 bit signal is then processed by the PIP module 320, the stacks 352A and 352B, and the operator memory 354 in the order of arrival. Subsequent output of circuit 306B after picture-in-picture decoding is the processed coded signal of n-1 bits. In the data recovery circuit 357, the encoded signal of n-1 bits is passed to the summation circuit 802 and one input of the product gate 804. The signal at the second input of the product gate 804 masks the lowest valid bit of the encoded signal. The output of the product gate 804 is conducted directly to the input of the non-equivalence circuit 308 and delayed by the circuit 806 by one clock pulse or by a pixel, and then routed to the second input of the non-equivalence circuit 808. The output of the non-equivalence circuit 808 is one input of the product gate -810 and at the same time the input of the Y component interpolator 359, this input constituting the new lowest valid bit of the decoded signal. The second input of the product gate 810 is a signal of the same code sequence and the same phase as the coded signal sent to the summing point 372. The output of the product gate 810 is a subtraction circuit input 802. The output of the summing circuit 802 is combined with an additional bit ce, thereby producing an n-bit decoded signal as input of the Y component interpolator 359.

The two-bit coding circuit 370 shown in FIG. 41 includes a summation circuit 376 that combines an n-bit signal with a two-bit coding sequence. According to this arrangement according to the invention, the coding signal can be defined by any repeating sequence of numbers 0, 1, 2, 3, which are in this sequence in any order. This definition includes the following sequences given in Table 1.

Table 1

0123 1023 2013 3012 0132 1032 2031 3021 0213 1230 2102 3120 0231 1203 2130 3102 0312 1302 2301 3201 0321 1320 2310 3210

A two-bit coding sequence that is particularly preferred is 02130213, etc. as shown in Fig. 41. The N-bit signal that is output from the summation circuit 376 has two bits with the least validity trimmed by circuit 378. The encoded signal of n-2 the bits are then processed by the picture-in-picture processor 320, the stacks 352A and 352B, the in-service memory 354, and the picture-in-picture decoding circuit 306B.

The quarter frequency component is usually less preferred than the half frequency component, although the quarter frequency component has a half amplitude compared to the half frequency component. Therefore, the decoding scheme can only be selected to suppress a quarter frequency component. The fixed signal path of the decoding circuit is designed to delay and adjust the amplitudes. The path of the second signal comprises an inverse bandpass filter combined with a limiter. The inverse bandpass filter suppresses the frequency at the center of the passband when added to the delayed and amplitude matched original signal. The limiter ensures that only amplitudes of coded size are suppressed. This decoding arrangement does not act on a signal component having a half frequency compared to the sampling frequency. The half-frequency signal component has a sufficiently low amplitude and a sufficiently high frequency to have a sufficiently low visibility and thus avoid problems.

Fig. 42 shows such a decoding circuit 306EU. The on-2 bit signal, which is output from the picture-in-picture decoding circuit 306B, is the input of the delay circuit 822, which generates a delay of two clock pulses or two pixels, to the second delay circuit 814 and to the summing circuit 812. is a subtraction input of the summation circuit 812, the output of which is an on-bit signal. The encoded signal on-bits is the input of the limiting circuit 816. In this case, the output values of the limiting circuit 816 are limited by an interval (-1.0, 1), that is, an absolute value of one. The two-bit output signal of the limiting circuit 816 is applied to the input of the delay circuit 818 to generate a delay of two clock pulses or two pixels, and at the same time is a subtraction input of the summation circuit 820. The delay circuit 818 and summation circuit 820 form a bandpass filter wherein the frequency is a quarter of the sampling frequency. A two-bit signal is a binary complementary signal. The output of the summation circuit 820 is a three-bit signal that is a subtraction input of the summation circuit

926. The output signal c n-2 bits of the delay circuit 822 is the input of the multiplier 324. The output of the multiplier 824 is the n-bit signal whose two bits with the lowest validity are zero. Summing in circuit 826, these bits are assigned values, possibly some correction. The output of the summation circuit 826 is a partially decoded n bit signal that is input to the Y component interpolator 359.

The resolution of the sky, or more precisely, the quality of the decoded video signal may, under certain circumstances, be improved by a time shift of the coding sequence. This sequence, whether single-bit or double-bit, repeats continuously in a given row, but is phase shifted on different rows. Multiple timeshift schemes can be generated. In order to hide the display errors resulting from the actual coding process, the two shifted sequences shown in Fig. 43 can be particularly advantageous. The offset of the frames by one and two pixels is one in which all rows of one field have the same phase and all rows of the next field are to the first field offset by one or two pixels. The relative offset of the frames transmitted by the two-bit coded signals is most effective in still images. In live images, a certain line structure may be visible where flat areas move. One pixel offset is particularly useful for two-bit codes if the signal is decoded, but for a signal that will not be decoded, a two pixel offset is currently preferred. Whether or not the signal should be decoded depends on the display format.

An alternative to coding for data reduction is to compress pairs of pixels, which is explained with reference to cbr. 44. At the top of FIG. 44, a field containing lines 1, 2, 3, etc. is shown. The pixels of each line are indicated by letters. Each P element will be retained and each P element will be replaced. Permanent and replaced elements are moved one pixel per line. In other words: in odd-numbered lines, the second, fourth, sixth, etc. pixel is exchanged. In even-numbered rows, pixels that are in odd places are exchanged. Two basic alternatives consist in replacing each replacement element with a one-bit or two-bit code. The bits for the codes are taken from a series of bits available to define persistent pixels. This number of bits is limited by the image processor memory capacity. In this case, the CPIP type chip and the RAM image memory 350 represent a limitation of an average of 4 bits per pixel. If each swapped pixel is replaced by a single bit code, then 7 bits are available for each persistent pixel. Similarly, if each exchanged pixel is replaced by a 2-bit code, then 6 bits are available to describe each persistent element. In both cases, each pair of consecutive pixels (one permanent and one replaced) requires a total of 8 bits. Thus, a total of eight bits per pair represents an average of only four bits per pixel. The data reduction ranges from 6: 4 to 7: 4. The sequence with the elements to be replaced is illustrated by a portion of the fields containing three consecutive lines: n-1, n, n + 1. The pixels to be replaced are designated R1, R2, R3, R4 and R5. The elements to be retained are labeled A, B, C, and D.

According to the one-bit code scheme, the pixel to be replaced is replaced by zero if its value is closer to the pixel above it than to the diameter of the pixels that are on either side of it. In the example shown in Fig. 44, the one-bit replacement code for pixel R3 will be zero if the value of pixel R3 is closer to the diameter of the elements B and C than that of pixel A. Otherwise, the one-bit replacement code will be -1. the pixel R3 by its average of the pixel values B and C if the one-bit code is zero. If the one-bit code is equal to one, then the pixel value R3 'will be the same as the pixel value A.

Also shown is the replacement and renewal sequence for the two-bit code. A 2-bit replacement code for pixel R3 is zero if the value of pixel R3 is closest to the value of pixel A. A two-bit replacement code is equal to one if R3 is closest to the average of A and B. the value of R3 closest to the average of A and C, and three if R3 is closest to the average of B and C. The refresh sequence corresponds to the replacement sequence. If the two-bit code is zero, the pixel value R3 'is equal to A. If the two-bit code is equal to one, the pixel value R3' is equal to the average of A and B. If the two-bit code is equal to two, equals the average of pixel values A and C. If the two-bit code is equal to three, then the pixel value R3 'is equal to the average of pixel values B and C.

The one bit code is preferred insofar as the persistent pixels are described with one bit resolution. The two-bit code is advantageous in that the replaced pixels are described with higher resolution. It is advantageous to perform calculations with only two line values, thus minimizing the necessary line memory capacity. On the other hand, by including the D value in the calculations, a more accurate surrogate sequence could be generated, but at the cost of an additional line of image memory capacity. Compression of pairs of pixels may be particularly effective to provide good horizontal and vertical resolution, and in some cases better than encoding and decoding. However, the resolution of diagonal transitions is generally not as good as coding and decoding.

According to the invention, a variety of data reduction and recovery schemes are available, including, for example, compressing pairs of pixels and encoding and decoding. In addition, different coding sequences of different bit counts and different ways of compressing pairs of different bit count pairs are available. A particular data reduction and recovery scheme may be selected by a widescreen microprocessor to achieve maximum resolution for each particular type of display format.

The widescreen processor also has the ability to control vertical deflection to perform vertical zoom. The widescreen processor topology is such that the raster mapping (interpolation) functions are independent of both the auxiliary and the main channel independently of each other and the vertical zoom (which controls the vertical) Due to this topology, it can be stretched both horizontally and vertically to maintain the main zoom However, if the setting of the auxiliary channel interpolators is not changed, the picture in picture (small picture) will be zoomed vertically, but not the deflection) of the main channel horizontally. The auxiliary channel interpolator may therefore be adapted to perform greater horizontal stretching in order to maintain the correct dimension of the sides of the small picture in the picture during vertical stretching.

A suitable example of this procedure is to display a 16 x 9 envelope format, as explained in more detail below. In short, the main horizontal grid mapping is set to 1: 1 (no expansion or compression). The vertical direction is zoomed by 33% (ie stretched in a 4/3 ratio) to avoid black streaks related to the image from the envelope format source. The aspect ratio of the main channel image is now correct. The nominal setting of the auxiliary channel for a 4x3 source without vertical zoom is 5/6. Differential value for the coefficient of expansion X is determined as follows ^- ·

X = (5/6) x (3/4) = 5/8

If the sub channel interpolator 359 is set to 5/8, the correct aspect ratio of the small picture is maintained and the objects within the picture in the picture are not distorted.

A particular advantage of a widescreen aspect ratio television is that the envelope format signals may be stretched to fill the entire wide screen, although it may be necessary to interpolate the signal to provide additional vertical resolution. According to the invention, an envelope size automatic detection circuit is provided that automatically performs stretching of a 4 x 3 aspect ratio signal that includes a 16 x 9 aspect ratio envelope image. The automatic envelope format detector is explained in detail with reference to Figures 45 to 49.

In order to increase the vertical height of the envelope signal, the vertical scanning frequency is increased so that the black areas at the top and bottom of the image are removed or at least substantially reduced. The automatic envelope format detector is based on the assumption that the video signal will generally correspond to the signal shown in Fig. 45. Areas A and C are free of active image, or have low brightness levels that are less than a predetermined brightness threshold. Area B has an active image or at least a luminance level that is higher than a predetermined luminance threshold. The respective region time intervals are a function of the envelope format, which may range from 16 x 9 to 21 x 9. The duration of both the A and C sections is approximately 20 lines for the 16 x 9 format. The envelope format detector checks the brightness levels of areas A and / or C. If an active image or at least a minimum brightness level is detected in areas A and / or C, the envelope format detector outputs an output signal such as logic zero indicating a 4x3 NTSC signal source. pages of display format. However, if the image is detected in area B, but not in areas A and C, then it is assumed to be an envelope signal source. In this case, the output signal would be a logical one.

The operation of the detector can be improved by the hysteresis shown schematically in FIG. 46. Once the envelope format signal has been detected, the minimum number of normal-format signal frames must be detected before changing the display to the display necessary for normal 4x3 signals. Similarly, once a normal 4x3 format signal has been detected, the envelope format for a minimum of half shots must be detected before switching the imaging unit in wide mode. Circuit 1000 includes a row counter 1004, a field counter 1006, and a detection circuit

1002, in which the above-described image signal analysis algorithm is performed.

In another embodiment of the present invention, envelope format detection is performed by calculating two gradients for each line of the image frame. To calculate these two gradients, four values are required: the maximum and minimum values of the line currently being processed and the maximum and minimum values of the previous line. The first gradient, referred to as a positive gradient, is created by subtracting the minimum value of the previous row from the maximum value of the existing row. The second gradient, referred to as a negative gradient, is created by subtracting the minimum value of the current row from the maximum value of the previous row. Both gradients may have a positive or negative value depending on the scene content, but negative values for both gradients may be ignored. This is because only one gradient can be negative at a time, and the gradient size with a positive value will always be greater than or equal to the gradient size with a negative value. This simplifies the circuitry, since the need to calculate the absolute value of the gradients is eliminated. If any of the gradients has a positive value that exceeds the programmable threshold, an image is assumed to be present on either the existing or previous line. These values can be used by the microprocessor to determine whether the image source is in envelope format or not.

Circuit 1010 for performing this envelope format detection method is shown in the block diagram of Fig. 48. Circuit 1010 includes an input luminance filter, a line maximum detector 1020, a line minimum detector 1022, and an output section 1024. The input luminance filter includes stages 1012 and 1014 and the merging circuitry 1016 and 1018. The envelope format detection circuit 1010 de96 processes digital luminance data Y_IN from the widescreen processor.

An input filter is used to improve noise characteristics, making detection more reliable. The filter consists essentially of two stages of the final pulse response having the following transmission characteristics:

H (z) = (1/4) χ (1 + Z-1) χ (1 + Z-3)

The output of each stage is trimmed to eight bits (divided by two) to maintain a unit DC gain.

Row maximum detector 1020 includes two registers. The first register contains the maximum pixel value at an existing point in the line period. At the beginning of each line period, it is initialized with a SOL pulse of one hour pulse width to 80h. A value of 80h is the minimum possible value of an 8-bit number in two complementary formats. The circuit is accessed by a signal labeled LTRBX EN having a logical 1 state of approximately 70% of the active video line. The second register contains the maximum pixel value for the entire previous line and is updated once per line period. The incoming luminance data Y_IN is compared to the current maximum pixel value stored in the first register. If they exceed the register value, the first register is updated in the next clock cycle. At the end of the image line ', this register will contain the maximum value of the entire part of the line that has been made available. At the beginning of the next video line, the value of the first register is loaded into the second register.

The line minimum detector 1022 operates in the same manner, except that its second register will contain the minimum pixel value for the previous line. The minimum pixel value is initialized to 7Fh, which is the maximum pixel value for an 8-bit number in binary complementary format.

The output section 1024 takes the values of the two second registers and stores them in eight-bit accumulators that are updated once per row. Then two gradients are calculated, a positive and a negative gradient. On the first line of the field, where any of these gradients is positive and greater than the programmable threshold, an enable signal is generated that allows the computation value of the existing line to be entered into the first line register. In each row where either of the two gradients is positive and exceeds the programmable threshold, an additional enable signal is generated that allows the computation value of the existing row to be entered in the register of the last row. The last line register will thus contain the last line of the field in which the threshold was exceeded. Both of these enable signals can only act between lines 24 and 250 of each field. This avoids incorrect detection resulting from closed captioning information and VCR switching heads. At the beginning of each field, the circuit is reinitialized and the first and second row register values are fed to the respective envelope register end registers. The LTRBX_BEG and LTRBX_END signals indicate the beginning and end of the signal in the envelope signal.

Giant. 49 illustrates an automatic envelope format detector as part of a vertical dimension control circuit 1030. The vertical dimension control circuit includes an envelope format detector 1032, a vertical display control circuit 1034, and a three-state output circuit 1036. Alternatively, vertical blanking and reset pulses may be transmitted as separate signals. According to the invention, an automatic envelope format detector can automatically translate or stretch a 4 x 3 aspect ratio image signal that contains a 16 x 9 aspect format envelope image when the VERTICAL SIZE ADJ output signal becomes active, enlarges The vertical dimension control circuit 500 shown in FIG. 22 has a vertical deflection height of 4/3, thereby allowing the active image portion of the envelope format signal to fill a wide screen without distorting the aspect ratio. In another alternative not shown in the drawings, the automatic envelope format detector may include a circuit for decoding a code word or signal transmitted by an envelope format signal source, which code identifies the signal it is transmitted as a envelope format signal.

The vertical imaging control circuit 1034 also determines which portion of the screen beyond the image dimension will be displayed on the screen. This is called vertical panning. If the image signal with a larger vertical dimension is not in an envelope format, the conventional image format image will be zoomed, i.e. stretched, to simulate a widescreen format. However, in this case, the cropped portions of the 4/3 image will contain the active image information. Vertical cropping of the image by 1/3 is necessary, regardless of further interventions, the top sixth and bottom sixth of the image will always be cropped. However, the image reach may indicate that it is better to crop more of its upper part than the lower part, or vice versa. For example, if all of the action is at the bottom level, that is, on the ground, the viewer may prefer to crop a larger portion of the sky. Thus, the vertical panning capability allows you to select which portion of the zoomed image will be displayed and which portion will be cropped.

The vertical panning is explained with reference to Figures 23 and 24 (a) to (c). Figure 23 shows a three-level full vertical blanking and resetting signal at the top. These signals can also be generated separately. The vertical blanking pulse starts when the L_COUNT signal is equal to VRT_BLNKO and ends when the L_COUNT signal is equal to VRT_BLNK1. The vertical reset pulse begins when the L_COUNT signal is equal to VRT_PHASE and lasts for 10 horizontal lines. The L_COUNT signal is the output of a 10-bit counter used to keep track of horizontal half-lines relative to the rising edge of the VSYNC_MN signal. The VSYNC_MN signal is a synchronized version of the VDRV_MN signal, which is the vertical synchronization component of the main signal routed to the gate array. The signals VRT_BLNK0 and VRT_BLNK1 are generated by the microprocessor depending on the vertical panning command. The VRT_PHASE signal programs the relative phase of VERT_RS7 output relative to the rising edge of the vertical sync component in the COMP_SYNC output. The COMP_SYNC output is the output of a J-K flip-flop. The state of this flip-flop is determined by decoding the outputs of the L_COUNT and H_C0UNT counters. H_COUNT is a horizontal position counter. The L_COUNT counter is used to divide the COMP_SYNC signal into three segments corresponding to the horizontal sync pulse, the equalization pulse, and the vertical sync pulse.

100 ALIGN!

The vertical deflection current without image overhang, which in fact relates to a normal 6% image overhang, is shown in dashed lines as it is the corresponding vertical blanking signal. The vertical blanking pulse width without image overhang is C. The vertical sync pulse is in phase with the vertical reset pulse. The vertical deflection current is represented by a solid line for the image overlap mode. It is the corresponding vertical blanking pulse of width D.

If the lower projection of the image A is equal to the upper projection of the image B, the image will have the form shown in Fig. 24 (a). If the vertical reset pulse is formed to lag behind the vertical synchronization pulse, the lower image overlap A is less than the upper image overlap B, resulting in the image shown in Fig. 24 (b). This is a vertical pan down, showing the bottom and obscuring the upper third of the defense. Conversely, if the vertical reset pulse is formed to precede the vertical sync pulse, the lower image overlap and is greater than the upper image overlap B, resulting in the representation shown in Figure 24 (c). This is an upward pan, showing the top of the image and dimming the bottom of the image. The phase sync of the vertical sync signal and the vertical reset signal can be controlled by the widescreen microprocessor 340, thereby allowing vertical panning during the overlap of the operating modes image. Obviously, the overlapped image grid remains vertically centered or symmetrical on the screen or screen during vertical panning. The blanking interval can be vertically moved or positioned asymmetrically to the center of the raster, obscuring the larger part of the image at the top than at the bottom or vice versa.

101

A widescreen television according to various embodiments of the arrangement according to the invention may stretch or compress the image using adaptive interpolation filters. The interpolators for the luminance components of the main and auxiliary signals may be time shift correction filters. For example, a four-point interpolator includes a two-point linear interpolator and a combined filter and multiplier that are cascaded to provide amplitude and phase compensation. In total, four adjacent data samples are used to calculate each interpolated point. The input signal is fed to a two-point linear interpolator. The delay of this input is proportional to the delay control signal (K). The amplitude and phase errors of the delayed signal are minimized by using a correction signal obtained by the additional filter and multiplier that are connected in cascade. This correction signal performs a spike that compensates for the frequency response of the point-to-point linear interpolation filter for all values (K). The original four-point interpolator is optimized for use for signals having a pass band f _s / 4, where f _s is the data sampling frequency.

According to another alternative arrangement according to the invention, both channels can be used, which is called a two-step interpolation process. The frequency response of the original interpolation filter variable can be improved by using such a two-step process. This process is hereinafter referred to as two-step interpolation. The two-stage interpolator of the invention comprises a finite pulse response filter of 2n + 4 taps with fixed coefficients and a four-point variable interpolator as shown in Figures 56 and 57. The output of the finite pulse response filter is spatially positioned midway between the input image samples

The output of this filter is combined with interleaving with the original data samples that are delayed to produce an effective sampling rate of 2f ₃ . This is a valid assumption for frequencies in the bandwidth of the final pulse response filter. The result is a significant widening of the effective bandwidth of the original four-point interpolator.

The compensated variable interpolation filter known in the art produces precisely interpolated samples until the frequency components of the signal are greater than about one quarter of the sampling frequency, ie 1/4 fs. For signals having frequency components substantially greater than 1/4 f _s , a two-stage approximation may be used, as shown in the block diagram for the two-stage interpolator 390 in Fig. 58. The DS_A digital sample signal at sampling rate fs is the input of the final pulse response filter For example, a fixed pulse response filter 391 generates a second digital signal DS_B from the DS_A signal that also has a sampling frequency fs but is temporally positioned between the values of the first DS_A signal, for example, at midpoints between these values. The DS_A signal is also an input to the delay circuit 392, which produces a DS_C digital sample signal that is identical to the DS_A signal but time delayed by (N + 1) / f ₃ . The data streams DS_3 and DS_C are combined by interleaving in the multiplexing circuit 393, resulting in a data stream of DS_D values at double the sampling rate, or 2fs. The DS_D stream is the input of the compensated interpolator variable 394.

The fixed final pulse response filter is generally designed to precisely generate a plurality of samples corresponding to the time locations exactly halfway between the half-hour inbound samples. These are then interleaved with delayed but otherwise unmodified samples to form a 2fs sample rate. The final impulse response filter is most commonly generated using an even number of symmetrically balanced taps. An eight-branch filter that has, for example, a branch weight:

-1/32, 5/64, -11/64, 5/8, 5/8, -11/64, 5/64, -1/32, will accurately -interpolate signals having frequency components up to about 0.4 fs. Since the data interleaving frequency is doubled to 2fs, the signal processed by the variable interpolator never contains a frequency component higher than 1/4 of the sampling frequency.

The advantage of the two-stage interpolator is that it enables accurate interpolation of signals with bandwidths approaching one half of the sampling frequency. Thus, the system is best suited for imaging modes that require time stretching, such as zoom, where the goal is to maintain as much of the original bandwidth as possible. This may be possible with widescreen television, especially with an auxiliary channel, where the auxiliary signal is initially sampled at a relatively low frequency, for example 10 MHz. Maintaining as much bandwidth as possible can be important.

The two-stage interpolator 390 'that is suitable for zooming is shown in the block diagram of Fig. 59. The components that are common to interpolator 390 shown in Fig. 17 have the same reference numerals with respect to data flows. The purpose of the two-stage interpolator 390 ¹ is to horizontally zoom the incoming image by a factor m, where m is greater than 2.0. Thus, if the input and output data signals have the same sampling rate ίχκ, m output samples must be generated for each input sample. The signal is stored in the line memory 395 with the ob104 servant in the order of arrival at frequency f; and a portion thereof is then read as a DS_A bitrate at a reduced frequency fs. The clock pulses fs are formed below the set of clock pulses _!t and do not have a uniform period.

The data stream DS_B corresponding to the sample values midway between the existing samples, the data stream DS_A is determined using the fixed pulse response filter 391 and is interleaved with the delayed samples of the data stream DS_C to form a double frequency DS_D data stream. The DS_D stream, which is twice the original sample density, is then processed by the variable interpolator 394 to generate sample values for each period fiN. The storage circuit comprising the accumulator 398 and the summator 399 produces an output that increases by an increment r-2 / m for each hour period fju. The fractional interpolator portion controls the feeding variable value X from a latch 398. The integer carrier output (CO) via the accumulator 397 generates clock pulses 2f _{with the} read operation of memory 395 in the order of arrival and displacement data filter 391 FIR delay circuit 392, multiplexing circuitry 393 and the interpolator 394. The divider 396 makes the 2fs signal into gnalfs.

According to further variants of the arrangement according to the invention interpolators can be used, the advantage being that they store the image of the auxiliary and the main channel in an equalizing manner without additional line memory. The main channel line memory thus becomes also an image memory. Existing variable interpolation filters require double multiplication. The first multiplication is performed by a factor C, which is a two-bit number. The second multiplication is performed by K. factor K. The factor K is a five-bit number, allowing the case where X «16/16. They are

105 two ways to avoid the need for 5-bit multiplication. The first option is to multiply by a factor of 1-K instead of K, never choosing K = 0 as the display point. The second option is to multiply by a factor K, never choosing Κ = 1 as the display point.

Simplified multiplier for the interpolator with resolution of 1/16 or 1/32 is shown in FIG. 61. The multiplexer allows the multiplication of the variable "a five-bit variable b, where b = (b _4, b _3, b :, B _'; B'. ). The expression bo is the least significant bit, and b ₄ is the most valid bit. The values of b are limited to integers between 0 and 16 inclusive, although a similar procedure can be used to create more complex multipliers. For example, a multiplier for integers between 0 and 32 can be derived from the same rule. If b = 10000, the multiplier multiplies the output of the preceding addition circuit by conditionally two. For the arrangement shown, the number and number is on bits. The conditional multiplication function by two may be performed, for example, by a shift register or a multiplexing circuit.

The K and C values may be stored in the memory block and the counter may, depending on the acceleration required, index the read pointer to recall the desired memory location and load the K and C values into the interpolation multipliers. For this reason, it is very advantageous if the C value is encoded into a K value so that a single four-bit or five-bit word can transmit both the K value and the C value. The C value is then a function of the K value. 62, where K is a five-bit number. In the arrangement shown in Fig. 63, a plurality of summation gates may be used to accurately determine C values. The values are shown in the table in Fig. 64.

To achieve different waveforms, functions C = f (K) are

106, as shown in the alternative decoder of FIG. 55. With this decoding scheme, for example, the need for a single-chip lookup table or additional registers for storing values can be avoided by using only a few gates. Factor K can be more easily decoded using the circuit shown in Fig. 66.

The two-step interpolation explained by Figs. 56 to 58 can be optimized to overcome the value of 0.25 fs, where fs is the original sampling rate, in an alternative manner to the method described in connection with Fig. 59. The frequency curves shown in Figs. 67, show that the frequency response deviation is 0.2 dB at 0.25 fs for all K = (0, 1/8, 2/8 ... 1) values of 0.5 dB. If the amplitude responses of the different interpolation filters are more than 0.5 dB apart, visible errors can be expected. In certain simulations, it has been found that visible errors can occur at an amplitude response of more than 1.0 dB. The individual response of the horizontal interpolator should therefore form a response envelope for the selected values of K, such that the response curves are no more than 1.0 dB apart at any frequency as shown in Figure 67. The critical frequency at which it is expected visible errors, is marked f .... In practice, the cut-off frequency or divergence of the frequency curves should be reduced as low as f _c .

According to a further variant of the arrangement according to the invention, the frequency bandwidth of the interpolators can be extended by a 2n + 4 circuit compensating circuit, which extends the value f _c for the whole horizontal interpolation. Such a compensation circuit can additionally be implemented without adding another driver variable and thus without further

107 additional degree of freedom.

The following linear interpolation compensation circuit may extend the critical frequency f.- of the total interpolation to 0.7 xf _s / 2 or 0.35 f _s , using the maximum allowable 0.5dB criterion. If the 1.0 dB criterion is used, the diverging curves at f _s = 0.75 xf _s / 2 = 0.375 f _s . Additionally, if the draft is limited when using K = 0 and K = 1, so that they can not be selected, it may be frequency bandwidth is increased even slightly the value of _f:. In addition, by selecting the C value, the range of pointing can be controlled.

Using a linear interpolator, an eight-point interpolator can be formed with an eight-tap final pulse response filter for amplitude and phase compensation. The total interpolator for K = (0, 1/16, 2/16, ... 1) can be described as follows:

c / 2 - Zi (C - 3/2) + 2-2 (K + C) + Z - 3 (1 - K + C) - Z * (3/2) (C) + (C / 2) ( Z-5).

The relationship between K and C is shown in the table and graph in Figs. 68 and 69. A set of curves shows that the ripple in the transmission band is less than 1.5 dB. The critical frequency for this compensation circuit is at 0.7 X fs / 2.

This embodiment of the invention can be extended to an eight-branch compensation circuit that provides additional usable bandwidth.

The eight-point interpolator may consist of an eight-point final pulse response compensation filter and a two-point linear interpolator, as shown in Figure -70.

Three such compensation circuits can be defined by the following relationships:

(1) -C / 4 + Z ¹ (3/4) (C) + ZX-3/2) (C) + Z-XK + C)

108 + (1 - Κ + C) 2 - + Ζ - 5 (-3/2) (C) + Ζ-- (3/4) (C) +

Z- ⁷ (-C / 4) (2) -C / 8 + Ζ-((5/3) (C) + Ζ-Η-12/8) (C) + Ζ3 (Κ + C) + Z- * (1 - Κ + C) + Ζ ~ ⁵ (-12 / 8) (C) + Z ' ^J (5/8) (C) + Z ~ ⁷ (-C / 8), and (3) -C / S + Z ~ '(C / 2) + Z-2 (-11 / 8) (C) + Z3 (K + C) and Z -' (l - K + C) and Z -? (- ll / 8) (C) + Z - (C / 2) + Z ~ ⁷ (-C / 8), where K = (0, 1/16, 2/16, ... 1)

Each of these circuits has its own specific characteristic bandwidth and advantages. The tables of K and C values are not shown for the arrangement of Fig. 70. The C value may be selected to allow the most favorable set of curves to be obtained for any particular compression or expansion as a whole.

The control signal sends a K value to the linear interpolator. The K value is then decoded to obtain a C value for the compensation circuit multiplier. In all interpolation equations, the multipliers of the C value are the coefficients of the final pulse response. For example, the above equation (1) has tap weights (-1/4, 3/4, -3/2, 1, 1, -3/2, 3/4, -1/4).

This embodiment of the invention can generally be extended to 2n tap finite response filters used as compensation circuits, although using only two linear multipliers to calculate linear interpolation and the associated compensation circuit can be quite difficult. An alternative to a 10-tap final pulse response filter can be, for example, using an 8-tap fixed filter for Z- to Z- ^s taps, with Z- and Z ^{-7 taps} depending on some of K and C. This is feasible because the frequency response needs - additional compensation for widening the passband when K approaches

109 from any direction of 1/2, i.e. if

K = 0 or K = 1.

Fig. 60 is a block diagram of a specific circuit 1150 for generating an eight-point two-stage filter using a four-point interpolator. The luminance image signal to be expanded or compressed is the input of the line delay circuit 1152. The delay circuit outputs designated Z ⁵ , 2 ~ '-, Z ^- -, Z ^-5 , Z ^-4 , Z * -, 2'- And Z ^- , the inputs of the multilink filter 1154 are the final pulse response. This filter produces at least one set of intermediate samples labeled I, for example between actual samples labeled Z. The results can sometimes be improved by using a plurality of finite pulse response filters that generate a plurality of intermediate point sets, although this significantly increases the complexity of the system. Such additional filters, each requiring a delay circuit Z ' ^: are illustrated by multiplying the final pulse response filter 1154 and the delay circuit 1158 for Z ^-1 . Outputs Z 3, Z ⁵ and Z ^-4 are also inputs of a delay matching circuit 1156. The output of the I- direct input circuit 1150 commanding data as well as the version of the I ^- - Delay circuit 1158 outputs Z ^{- 5} *, Z ^- ' ⁴ *' and Z ^_ ' ^? * ⁿ 'are also the inputs of the data selector circuit 1160. The inputs of the data selector circuit 1160 are selected to be as symmetrical as possible with respect to the delay. The number of such inputs is one greater than the number of points of the second stage interpolator, in this case the four-point interpolator 1162. The relative, time position of the data selector 1160 inputs is as follows:

• 7 - · j. 'τ ^r - z - - i + r. 5 T -: 2 -' 5 * '

The data selector circuit 1150 may be formed by a multiplexer pole controlled, for example, by a MUX_5EL dilution signal. The optional sets are diagrammatically indicated and arranged such that each interpolation of interpolator 1162 is based on two real points and two intermediate points. The outputs Y0, Y1, Y2 and Y3 of the data selector circuit 1160 correspond to one of two selectable sets and are the inputs of the four-point interpolator 1162. The operation of the multiplexer control signal MUX_SEL is a function of K values, i.e. MUX_SEL = f (K). The choice of the MUX_SEL signal depends on which of the original points is the intermediate point. The output Yout of the interpolator 1162, which responds to the control values K and C, is an expanded or compressed image luminance signal.

Claims (14)

A display system comprising display means having a first aspect ratio of a display format, means for mapping an adjustable display area in display means, characterized in that the means (304, 206) for processing the first video signal (Y_MM, U_MN, V_MN) and the second video signal (Y_AUX, U_AUX, V_AUX) from input video signals (Y_M, U_M, V_M; Y_A, U_A, V_A) of one of the different aspect ratios of the display format, switching means (SW1, SW2, SW3, SW4) for selectively pooling the sources ( Tuner # 1, Tuner # 2, AUX1, AUX2, S1, S2) of video signals as said input video signals (Y_M, U_M, V_M; Y_A, U_A, V_A), means (312) for selecting the first video signal (Y_MN, U_MN) , V_MN) or a second video signal (Y_AUX, U_AUX, V_AUX) or a combination thereof as output (Y_MX, U_MX, V_MX) and mapping means (.50; 113), video signal (240) for controlling the processing means (304, 305) and the selecting means (312) to adjust the aspect ratio of the display format and the aspect ratio of each picture transmitted by the output video signal (Y_MX, U_MX, The imaging system of claim 1, wherein one of the different aspect ratios of the display format is the same as the first aspect ratio of the display format. 113 3. The display system of claim 1. wherein the processing means is adapted to selectively trim the input video signals (Y_M, U_M, V_M; Y_A, U_A, V_A). 4. Imaging system according to claim 1, confess- čující s e t i. m that mapping means (50) contain means to create raster pro screen (244) • 5. Imaging system according to claim 1, confess- čující s e tim that mapping means contain means (113) for creating an address- dots for the liquid crystal display unit (115). Display system according to claim 1, characterized in that said display region is adjustable in only one dimension. Display system according to claim 6, characterized in that the display area is adjustable only in the vertical direction. The imaging system of claim 1, wherein the processing means (304. 306) is adapted to horizontally interpolate the video signals. The imaging system of claim 1, further comprising means (40) for converting the interlaced image. 114 signals (YY_MX, U_MX, V_MX) to the non-interlaced image format (Y_2fH, U_2H, V_2fH). The display system of claim 1, wherein the video signal sources comprise channel selectors (Tuner # 1, Tuner # 2) and video connections (AUX1, AUX2, 31, 32). Display system according to claim 1, characterized in that the processing means (304, 306) comprise respective interpolation means (337, 359) for the first input video signals (Y_M, U_M, V_M) and the second input video signals (Y_A, U_A) , V_A). Display system according to claim 11, characterized in that the display area is adjustable only vertically, the processing means (304, 306) interpolating the input video signals (Y_M, U_M, V_M; Y_A, U_A, V_A) only horizontally. Display system according to claim 1, characterized in that the mapping means (50: 113) comprise horizontal and vertical deflection circuits (50) for generating a raster, the raster being vertically adjustable and processing means. 115 (304, 306) integrate input U_M, V_X: Y_A, U_A, 7_A) 14. An imaging system having image signals (Y image signals (Y_M, e) horizontally. The interpolation of input (AV) in processing means (304, 306) is performed by selectively stretching or compressing the input video signals (Y_M, U_M, V_M; Y_A, U_A, V_A). 15. Imaging č u j i c i 5 Wednesday (60) for nálem Y_ _MX, U _MX, (R_EXT, G_EXT, 3 Wednesday (50) and z The system of claim 1, characterized in that it comprises a second selection between the output video signal (MX) and the external video signal (EXT) for display by the mapping imaging means (244). The detergent display system (301, 302) of claim 1, wherein said processing means (50: 113) is synchronized.