SI9111276A - Personal computer with drive indentification - Google Patents

Abstract

The present invention relates to personal computers and above all on a personal computer that is equipped for indentifying the storage capacity storage devices for direct access to a removable tool used by the computer. At least defined by a multitude of paths that transmit signals and are stretched between the storage device and the controller for the storage device, is used to be a controller identifies the type of device the controller communicates with.

Description

(57) The present invention relates to personal computers, and in particular to a personal computer, which is equipped to identify the storage capacity of a direct access storage device for a removable means used by the computer. At least certain of the plurality of signal transmitter paths extending between the storage device and the storage device controller shall be used to identify to the controller the type of device with which the controller communicates.

INTERNATIONAL BUSINESS MACHINES CORPORATION

A personal computer with a drive identification

The invention relates to personal computers and, in particular, to a personal computer equipped to identify the memory capacity of a memory device by direct access to a removable means used with a computer.

The invention solves the technical problem of identifying a memory device with direct access for a removable medium that is used by a PC.

PC systems in general, and IBM PCs in particular, have embraced the widespread use of computers in many segments of today's modern society. PC systems can usually be defined as desktops, desktops, or laptops consisting of a system unit that has a single system processor and associated non-existent or existing memory, display monitor, keyboard, one or more floppy drives, non-volatile disk memory, and optional printer. One of the distinguishing features of these systems is the use of a motherboard or system board to interconnect these components. These systems are primarily designed to provide independent computing capability to an individual user and are inexpensively available to individuals or small businesses. Examples of such personal computer systems are IBM XT and AT personal computers and IBM personal computer systems / 2 with models 25, 30, 50, 60, 70 and <80.

These systems can be classified into two general families. The first family, commonly referred to as family I models, use a bus architecture, with IBM being an AT personal computer and other IBM compatible computers. Another family, called family II models, uses the MICRO CHANNEL architecture, for example, models 50 to 80 of IBM's PC system 2. Many Family I models have used the well-known INTEL 8088 or 8086 microprocessor as a system processor. These processors can address 1 MB of memory. Specific Family I and Most Family II models use INTEL 80286, 80386, and 80486 high-speed microprocessors that work in real-time to emulate a slow INTEL 8086 microprocessor or in proprietary mode that extends the address range from 1 MB to 4 GB in some models . Real-mode 80286, 80386, and 80486 processors' capabilities actually provide hardware compatibility with software written for 8086 and 8088 microprocessors.

Such PCs are characterized by their open architecture. This means that the systems are designed and constructed in such a way that additional peripheral devices, such as DASD direct access memory devices, can be selected and added to the systems, or the existing device may be replaced for preparation of another type. The floppy drives mentioned above are one example of DASD direct access memory for removable assets. Many I families were often equipped with a 5.25-inch, high-performance or high-capacity diskette drive that had a memory capacity of 1.2 MB of data per diskette. Such machines, however, could be equipped with a previously known type of DASD direct access memory that used a 5.25 inch floppy disk to store 360 kB of data. Family II machines can have DASD direct access memory using 3.5 inch floppy disks that store 780 kB or 1.44 MB of data. It is known and contemplated that DASD storage devices for other removable assets could be equipped and used with PCs of the general types described.

Until now, typically, a PC of the type described has used a central processing unit to execute instructions and to handle data and a direct access memory device controller operatively placed between the processor unit and DASD direct access memory device to control write data to a removable a DASD direct access memory device or reads data from that removable means. Consideration was given to the identification of the type of DASD memory device with direct access being used and the storage characteristics of the means inserted into such a drive when operating a personal computer. The interested reader should refer to U.S. Patent No. 4,733,036 to Berens et al., Issued September 20, 1988, and to U.S. Patent No. 4,928,193 to Agoglia et al., Both of which are also cited in the scope of the invention described herein. - to view a description of the diskette drive apparatus and procedures and types of asset. The descriptions of these prior patents are hereby incorporated into this description to the extent necessary or appropriate for the understanding of the present invention.

In view of the transitional discussion, it is an object of the present invention to provide a personal computer system that will distinguish between a plurality of direct access memory devices for removable assets used in such a system. In carrying out this task of the invention, at least certain of the plurality of signal communication paths extending between the memory device and the memory device controller is used to identify to the controller the type of device with which the controller communicates.

A further object of the invention is to allow a distinction to be made between a plurality of memory devices with direct access to removable means, while enabling the system to include both older types of memory devices not specifically adapted to the definition described herein and newer types of memory devices specifically equipped for such adjustment. In carrying out such a task of the present invention, the specific identifying information is communicated from the DASD memory device with direct access to the controller, using paths that were used for other purposes as long as they existed in older types of devices.

Some of the objects of the present invention have been defined, and others will become apparent below in the description, bearing in mind the connection with the accompanying drawings showing:

Figure 1 is a perspective view of the personal computer with which the present invention is implemented;

Figure 2 is a perspective view of certain elements in a disassembled personal computer according to Figure 1, which include a housing, a cover, an electromechanical memory device with direct access and a motherboard, and illustrates certain connections between these elements;

Figure 3 is a schematic view of certain components of a personal computer of Figures 1 and 2;

Fig. 4 is a schematic representation of a multiple path interconnection between a controller and a storage medium by direct access to a removable means according to the present invention; and Fig. 5 is a schematic representation of a coding scheme for communicating identification data in accordance with the present invention.

While the present invention will be described in more detail below, with reference to the accompanying drawings showing a preferred embodiment of the present invention, it should be understood at the beginning of the description that follows that those skilled in the art can adapt the invention described herein and will always achieved favorable results according to this invention. Therefore, the description that follows should be understood as a broad, explanatory explanation intended for those skilled in the art, and not as limiting to the present invention.

Referring now specifically to the accompanying drawings, the microcomputer representing the present invention is shown there and generally indicated by 10 (Fig. 1). As mentioned previously, the computer 10 may have an associated monitor 11, a keyboard 12, and a printer or a drawing machine 14. The computer 10 has a cover 15 formed from the ornamental outer portion 16 (FIG. 2) and an internal protective portion 18 that cooperates with housing 19 in defining an enclosed and protected space that receives electrically powered components for data processing and storage. At least some of these components are located on a layered board 20 or on a motherboard that is secured to the chassis 19 and provides electrical interconnection of the computer components 10, including those defined above, and such other related elements as floppy disks, various forms of memory devices with direct access to an access card or board, etc. As will be described in more detail below, the motherboard 20 provides for the input / output signals to be transmitted to and from the operating components of the microcomputer.

The housing 19 has a base marked 22, a front plate 24 and a rear plate 25 (Fig. 2). The front panel 24 defines at least one open latch - in the form presented, and four latch openings - for receiving a memory device, such as a magnetic or optical disk drive, a tape backup drive, or the like. In the form presented, a pair of upper shut-off openings 26, 28 and a pair of lower shut-off openings 29, 30. are mounted. One of the upper shut-off openings 26 is adapted to accommodate first-size peripheral drives - such as drives known as 3.5 inch drives while the second shutter 28 is adapted to accommodate drives of a selected size of two sizes - such as a 3.5 and 5.25 inch drive - and the lower shutters are adapted to accommodate only one size - 3.5 inch drive , One floppy drive is shown at 85 in FIG. 1 and is contained in the upper shut-off port 26 and is a storage device with direct access to a removable means and can accommodate a floppy disk that inserts the disk into it and uses floppy disks that receive, store and send data as is commonly known. The rest of the closures shown are empty.

Before linking the above building to the present invention, it is appropriate to review the summary of the operation of a PC 10 system in general. Referring to FIG. 3, a block diagram of a PC system is shown there showing various components of a computer system, such as the system 10 according to the present invention, including components that are attached to the motherboard 20, and the connection of the motherboard to the output / input windows and the like. hardware of PC systems. A system processor 32 (MICROPROCESSOR) is connected to the motherboard, comprising a microprocessor that is connected to a local bus 34 of a very fast central processing unit via a bus 35 (BUS CONTROL TIMING UNIT) for temporal control of the bus to the memory control unit 36, which is further associated with non-existent read-write memory 38 (RAM; DRAM SIP). While any suitable microprocessor may be used, the 80386 microprocessor sold by INTEL is suitable.

While the present invention is further described with particular reference to the system block diagram of FIG. 3, it should be understood at the beginning of the description which follows that it is contemplated that the apparatus and method according to the present invention may be used with other hardware configurations of the motherboard. The system processor could be e.g. INTEL 80286 or 80486 microprocessor.

Returning now to FIG. 3, a local bus 34 comprising data, address and control components, central processing units, takes care of the connection of the microprocessor 32, the mathematical coprocessor 39 of the CACHE CONTROLLER 40 and the cache 41 (CACHE). A buffer buffer 42 (BUFFER) is also connected to the local bus 34 of the CPU. The buffer 42 is itself associated with a slower - relative to the local central processing unit bus - system bus 44, which also comprises address, data and control components. System bus 44 extends between buffer 42 and buffer 68 (LATCH / BUFFER and DECODER). The system bus 44 is further connected to the BUS CONTROL TIMING UNIT unit 35 for timed bus control and to the unit 48 (DMA) for direct memory access. The direct memory access unit 48 comprises a central arbitration unit 49 (CENTRAL ARBITER) and a direct memory access controller unit 50 (DMA CONTROLLER). The buffer 51 provides an interface between the system bus 44 and the selectable bus

MICRO CHANNEL bus 52. A plurality of input / output windows 54 (I / O SLOTS) are connected to bus 52 to receive MICRO CHANNEL adapter cards and are further connected to the output / input device or memory.

The arbitration control bus 55 connects the controller 50 of the direct memory access unit and the central arbitration unit 49 with the input / output windows 54 and the diskette adapter 56. A memory control unit 36 comprising a memory controller 59 (CONTROL- RAS, CAS DECODE), address divider 60 (ADDRESS MUX) and data buffer 61 (DATA BUFFER). The memory control unit 36 is further coupled to the read-only memory represented as RAM module 38. The memory controller 36 includes logic for mapping addresses to and from the microprocessor 32 into specific areas of read-write memory 38 (RAM). This logic is used to re-request the RAM previously occupied by the BIOS. Further, the memory controller 36 forms a ROM selection signal (ROMSEL), which is used to train or. enable read memory 64 (ROM).

While the microcomputer system 10 is shown with a basic 1 MB read-write module, it is understood that additional memory can be coupled as shown in FIG. 3, using optional memory modules 65 to 67 (DRAM SIP). For purposes of illustration only, the present invention is described with reference to a basic 1 MB memory module 38.

The state buffer 68 is included between the system bus 44 and the motherboard output / input 69. The motherboard output / input bus 69 includes address, data, and control components. Several I / O adapters and other components are connected along the I / O bus 69 of the motherboard, such as the Display Adapter 70 (DISPLAY ADAPTER) - used to drive the monitor 11, CMOS clock 72 (CMOS CLOCK), existing CMOS RAM 74, which it is hereinafter referred to as NVRAM, RS232 adapter 76, parallel adapter 78, timer array 80 (TIMER), diskette adapter 56, interrupt controller 84 (INTERRUPT CONTROLLER), and read memory 64 (ROM). Reader memory 64 includes a basic input / output system, which is used as an interface between the input / output devices and the microprocessor operating system 32. The basic input / output system (BIOS) stored in the read memory 64 can be copied to the read-write memory 38 (RAM) to shorten the run time of the basic BIOS input / output system. Reading memory 64 is further - via signal

ROMSIL - Responsible for memory controller 36. If memory controller 36 qualifies read memory 64, the primary BIOS input / output system is run from read memory. If the memory controller 36 disables read memory 64, the read memory or transponder does not respond to address requests by the microprocessor 32, that is, the primary BIOS input / output system is run from the RAM read-write memory.

The motherboard input / output 69, as described below, comprises portions defined by conductive paths created in the inner layer of the multilayer motherboard 20, and in particular includes some such paths extending in part at the edge of the motherboard 20, which is arranged to extend along the front and back panels of the housing. Such a motherboard design allows the location of a number of input / output connectors along such a side edge to exchange signals with such devices as a monitor, keyboard, and printer.

Clock 72 is used to calculate daylight saving time and NVRAM is used to store system configuration data. NVRAM will therefore include values that describe the system configuration provided. NVRAM e.g. it contains information describing the performance of a non-removable disk or floppy, the type of display screen, the amount of memory, time, date, etc. Above all, NVRAM will include data - they can be single-bit- that is used by the memory controller 36 to determine whether the BIOS is running from ROM or RAM and whether to re-request the RAM that the BIOS RAM will need. This information is further saved to NVRAM whenever a specific configuration program such as the SET configuration program is executed. The purpose of the SET configuration program is to store the values that indicate the configuration for NVRAM.

As mentioned previously, the computer has a cover, generally designated 15, and cooperating with the housing 19, to form a closed and shielded space that accommodates the above components of the microcomputer. The lid is preferably created from an outer ornamental cover body 16 which is a uniformly molded component made of a synthetic moldable material and a metal tank sheet 28 formed in accordance with the configuration of the ornamental cover body. The cover may, however, be manufactured in other known ways and the utility of the present invention m limited to the covers of the type described.

In the general-purpose computers described herein, it has been customary to provide the invention to provide interconnection between controller 56 and memory device by direct access to a removable medium such as a floppy disk drive 85 through multiple paths for communicating with electrical digital signals. Typically, such interconnection has been established either by means of cables connecting the controller and the drive or by directly attaching the DASD memory device with direct access to the system board 20. In previous PCs provided by International Business Machines Corporation or wholly compatible with such machines, an interconnection was established with a set of 34 paths or a conductor, with different of these paths having different adapted functions. Certain such features and paths have been used to date to determine the diskette drive and the type of asset, such as. described in U.S. Patent No. 4,733,036 to Berens et al., issued September 20, 1988, and in U.S. Patent No. 4,928,193 to Agoglie et al., both of which are also mentioned in the joint possession of the invention described herein. Descriptions of these prior patents are hereby incorporated by reference into the description to the extent necessary or appropriate to understand the present invention.

In order to achieve the objectives of the present invention, a pair of translation paths previously used in older types of DASD direct access memory is assigned new features and new features are implemented in a way that allows for the vertical compatibility of older types of drives with acquired new features . By providing new features of translation path pairs, the controller is thus able to distinguish between older and newer types of storage devices. As the controller further recognizes a newer type of preparation, it is trained to distinguish the specific type of such preparation by storage capacity.

In PCs of the types described above, as used before the present invention, the test procedure itself, upon activation, determined the presence of a direct access memory device by issuing commands to each possible drive and detecting the return of a specific signal. As sessions then determine the presence of a drive, the type of drive is determined by issuing a sequence of steps and observing the return of signals to differentiate between devices that have certain storage capacities. Once the storage capacity is determined, the system defaults to a specific type of preparation, based on known and expected preparations that could be installed and have certain storage capabilities.

A personal computer of the types described to carry out the present invention uses a pair of paths that have previously been either reserved or unused or used to return by weight to provide isolation of other signals, to be used to determine for the first time , whether memory devices of older or newer types are installed, and further, if it is determined that newer types of devices are present to allow the storage capacity of the memory devices that are installed to be determined. In particular, route 4 in the schematic representation of FIG. 4 (1-ΒΑΥ B OCCUPIED; 3- + 5 VOLT SUPPLY; 5, 7, 11, 13, 15, 19, 21, 23, 25, 29 in

31- GROUND RETURN; 9-DRIVETYPE 0; 17, 27-RESERVED;

33-DATARATE SEL O; 2-DARARATE SEL 1; 4-DRIVE 1Ε 1;

6- + 12 VOLT SUPPLY; 8-INDEX; 10-ENABLE ENGINE 0;

12-DRIVESELECT 1; 14-DRIVE SELECT 0; 16-ENABLE ENGINE 1; 18-DIRECTION IN; 20-STEP; 22-WRITE DATA; 24-WRITE ENABLE; 26-TRACK00; 28-WRITE PROTECT; 30-READ DATA;

32- HEAD 1 SELECT; 34-DISKETTE CHANGE) switched from a reserved path that has no other use to a path to indicate the first type of drive, while route 9 changed from returning by mass to a path to indicate a second type of drive. The availability of recognition between the absence of a signal of any type of drive in a pair of paths and between combinations of such signals that are characteristic of the storage capacity of a marked device, if it is determined that signals are present, enables these desired results.

The combination described here contributes to the success of certain features of both the controller 56 and the storage device. That is to say, the controller must be able to distinguish between the absence and presence of a device for identifying signals on lanes 4 and 9, and storage devices must be capable of transmitting such signals, both of which must avoid effects that could otherwise be detrimental. These capabilities provide up and down compatibility that will allow both new and old components to be used on the same system. It is thought that the present ability to identify will involve the use of open collector preparations, which will be trained by the DRIVE SELECT input signal from the controller. The use of open collector preparations allows for older storage devices that do not otherwise support this identification scheme, which must be used on the interface without damaging the identification of a qualified storage device.

Typical device identification encodings are schematically illustrated in FIG. 5. The coding scheme assumes that the selected of the two types of DRIVE SELECT signals can be sent as a low signal L or a high signal H. The storage device can respond to the training of identification drivers by receiving DRIVE

SELECT signals with high and low signal patterns after each in a pair of pathways identified here as DRVTYP1 and DRVTYP0. One possible assignment of meaning to the answers is shown.

During operation, the process for determining the system configuration will include the steps of deselecting all storage devices, reading the customized port, and testing the binary combination 11. In the presence of any other combination, it will be indicated that at least one installed storage device does not support the drive identification scheme described here, leading to the conclusion that the returned identification by all installed devices will be considered invalid. If invalid identification is determined, the user would be forced to perform a manual configuration process in which the user would provide the information necessary for the satisfactory use of custom storage devices. If the storage devices were supported to support the drive identification scheme described here, DRIVE SELECT would be sent to all available devices in a row and the qualified identification signals returned would be read to bring the system configuration table up to date.

By providing data to bring the configuration table up-to-date in this way, the present invention makes it possible to distinguish between a plurality of types of storage devices with direct access to removable assets used in such a system, and to include such older types of storage devices that are not specifically adapted to the definition described herein, and newer types of storage devices specifically equipped for such customization. In the drawings and description, a preferred embodiment of the invention has been presented and although specific terms are used, the description given uses terminology only in a generic and descriptive sense and not for limitation.

For

INTERNATIONAL BUSINESS MACHINES CORPORATION:

Claims (7)

1. A personal computer comprising a central processing unit for executing instructions, a direct access storage device for a removable means that receives, stores and transmits data for processing with said central processing unit, and a direct access storage device controller, operatively between said processor unit and said storage device for controlling the operation of said storage device in receiving, storing and transmitting data, said storage device and said controller operatively connected to a plurality of signal transmitter paths and a selected plurality of said paths translates signals that identify said feature controller to said storage devices that are characteristic of the storage features of said storage device, and said controller distinguishes between the absence of signals transmitted by said selected paths by indicating the presence of the first type of storage p and the presence and abundance of different signal combinations that are guided by said selected paths, and indicates the presence of a particular species from the storage group of another group. 2. A personal computer comprising a central processing unit for executing instructions, a direct access storage device for a removable means that receives, stores and transmits data for processing with said central processing unit, and a direct access storage device controller, operatively included between said processor unit and said storage device for directing the operation of said storage device in receiving, storing and transmitting data, said storage device and said controller operatively connected to a plurality of signal transduction paths and one pair of said paths signals that identify to said controller the characteristics of said storage device that are relevant to the storage capacity of said storage device, and said controller distinguishes between the absence of signals transmitted by said pairs of paths by indicating the presence of the first type of storage p and the presence and abundance of different combinations of signals being guided along these paths and provides information on the presence of each group from the groups of another type of storage device. A personal computer according to claim 2, characterized in that it comprises a driver device associated with each of said pairs of said paths, each driver device having the ability to transmit a suitable signal characteristic of the storage capacity of said storage device, and further preventing any adverse effect of said storage device and said controller, which may follow from the inability of said controller to recognize such a signal. A personal computer according to claim 2 or 3, characterized in that said controller emits said storage device along the second of said paths a training signal that triggers signaling along said pair of said paths. 5. A personal computer system having a high-speed system processor compatible with application programs and operating system software designed to run on lower-speed system processors, characterized in that the personal computer system comprises a high-speed microprocessor which has a realistic and secure operating mode and is connected to a high-speed data bus, non-existent memory electrically connected to a high-speed data bus, existing memory electrically connected to a lower-speed data bus; a bus controller for providing communications between the high-speed data bus and the lower-speed data bus, a memory controller electrically connected to said non-existent memory and said persistent memory, said memory controller regulating communications between said non-existent memory and said high-speed microprocessor, storage preparing for direct access to a removable means for receiving, storing and transmitting data for processing with said microprocessor; a direct access storage device controller operatively included between said microprocessor and said storage device for directing the operation of said storage device in receiving, storing and transmitting data, and is electrically coupled to a lower speed data bus and a plurality of paths that transmit signals and operatively link said the storage device and said controller, wherein the pair of said paths translates signals that identify to the said controller the characteristics of said storage device that are characteristic of the storage capacity of said storage device, said controller distinguishes between the absence of signals being guided by said pair of paths, as information on the presence of the first type of storage device and the presence and abundance of different signal combinations guided along said routes, as data on the presence of each group from the groups of other types of storage devices. A personal computer according to claim 5, further comprising a drive device associated with each of said pair of said paths, said drive device having the ability to transmit a suitable signal characteristic of the storage capacity of said storage device, and further, to isolate said storage device and said controller from the adverse effects that would otherwise result from said controller's inability to recognize such a signal. A personal computer according to claim 5 or 6, characterized in that said controller transmits to said storage device via a second of these paths a training signal that triggers the transmission of signals through said pair of said paths. For INTERNATIONAL BUSINESS MACHINES CORPORATION: 22531-I-95-KA SUMMARY A personal computer with a drive identification The present invention relates to personal computers, and in particular to a personal computer, which is equipped to identify the storage capacity of a direct access access storage device for a removable means used by the computer. At least certain of the plurality of signal transmitter paths extending between the storage device and the storage device controller shall be used to identify to the controller the type of device with which the controller communicates. οηη; a -.noL .... · · '' .JA O A FIG. 2