CA2072220A1 - Method and apparatus for interfacing with computer - Google Patents

Abstract

ABSTRACT
A device and method of interfacing peripherals to a host computer having one or more asynchronous ports uses a circuit board having a microprocessor. The device is connected into a bus of the computer so that it emulates the asynchronous port. One or more peripherals are connected to the device and the microprocessor on the device transmits data using ASCII commands between the computer and the peripheral to control the peripheral. There is no need to change the computer bios or to extend the software of the computer. With previous devices to interface peripherals, either the devices are installed between the keyboard and the computer and do not work satisfactorily or they require modifications to the bios and operating system of the computer and extensive software modifications enhancements.

Description

2~72220 This invention relates to a device to inter~ace peripherals to a host computer without changing the bios of the computer.
IBM XT and AT computers and compatibles of these computers are designed with memory map locations for serial co~nunications and parallel communications b~lt they do not have prepared memory map ports for devices such as bar code scanners and cash drawers.
These types of computers will henceforth be referred to as standard computers. The operating system software of standard computers does not deal with specialty application peripherals properly. Point of sale peripherals are presentl~ integrated with standard computers via exclusive or shared access to existing peripheral input/output ports in the computer's memory map. Exclusive access means that one device has exclusive access to the allocated part in the computer's memory map as well as exclusive ; access to the interrupt for that port. Shared access means that the peripheral devices may share a common access point to the computer's memory map, although communication is device specific and low level interface consideration ~e.gO timing, interrupts, error checking, device synchronization) are handled by so~tware resident on the host computer. The architecture for standar~ computers used for point of sale duties may be in the ~orm of a cash register or in the form of a computer. In order to enable peripherals, for example retail speci~ic input devices such as bar code scanners, magnetic stripe readers and cash drawers, to be controlled by a standard computer, it is known to use a keyboard wedge. Input from the device is intercepted and translated into simulated :~ . .... .
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keystrokes through a devlce that "wedges" or is pl~gged between the keyboard and the central processing unit in a standard computer or terminal.
These wedge devices are very simple to integrate rom a software application perspective but have limitations in that they do not provide sufficient data control and se~uence control. For example, when a keyboard wedge is used, the standard computer does not know whether the cash drawer is opened or closed.
Also, if the normal sequence is to operate the bar code scanner before opening the cash drawer and one wanted to reverse these procedures from time to time, that result could not be readily achieved with a keyboard wedge. It is also known that standard computers can be set up to control peripherals for retail implementations by software extensions to the operating system and to the basic input-output system (BIOS) of the computers. Unfortunately, these modifications invalidate the basic integrity of the standard computer and the software enhancements are not generally addres~able through standard software development languages and incorporate "libraries" of programs to access the retail peripherals.
Integration of these libraries o programs is extremely complex and expensive and is sometimes impossible to accomplish.
It is an object of the present invention to provide a device and method for interfacing peripherals to a standard computer without changing the computer bios by emulating an asynchronous port of the computer.
A device to interface peripherals to a standard computer without changing the computer hios where the computer has a bus and at least one 2~7222a asynchronous port is a printed circuit board containing a microprocessor. The circuit board is connected to the bus of the host computer to emulate the as~nchronous port. At least one peripheral is connected -to the device and the microprocessor transmits data between the computer and the peripheral to control the perlpheral.
A method o~ interfacing peripherals to a standard computer without changing the computer bios where the computer has at least one asynchronous port and a bus uses a device that is a printed circuit board and contains a microprocessor. The method comprises installing the device in the bus of the standard computer so that the device will emulate the asynchronous port, connecting at least one peripheral to said device and communicating between the computer and the microprocessor using commands to control said peripheral.
Preferably, the method includes the step of utilizing ASCII commands to communicate between the computer and the microprocessor.
In the drawings:
Figure 1 is a block diagram of the device;
Figure 2 is a circuit diagram of a microprocessor and the address decoder for the device;
Figure 3 is a circuit diagram of a memory circuit of the device;
Figure 4 is a circuit diagram of the AT
interface;
Figure 5 is a circuit diagram of part of a serial input/output multiplexer for the device;
Figure 6 is a circuit diagram of a part of a serial input/output multiplexer for the device;

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Figure 7 is a circuit diagram of a cash drawer interface;
Figure 8 is a circuit diagram of a magnetic card interface of the device;
Figure 9 is a circuit diagram of a power fail detect and battery bac~up for the device;
Figure 10 is a circuit diagram of a keyboard interface for the device; and Figure 11 is a circuit diagram oE a liquid crystal display interface for the device.
The block diagram of Figure 1 provides an overview of the device of the present invention. A
card edge connector connects the device into a bus of a standard computer. The computer is an IBM XT or IBM
AT or a compatible computer. Address, data and control lines are connected from the card edge connector to an AT interace which consists of a COM
or serial communications port emulator. This interface may be set up as any one standard COM ports (1 through 4) of the computer. Data is converted to a serial stream via a universal asynchronous receiver transmitter (henceforth UART) and transmitted to a UART on a microprocessor of the device.
The device is connected to the computer to 2S emulate an asynchronous port to intexface the microprocessor of the device with the standard computer. No bios modifications to the computer or device drivers are required to make the device function.
A set o~ ASCII commands, which can be sent to the device from the computer using its standard communications roots for serial ports allows ~he computer to send and receive data to and from the device. While ASCII commands are preferred, other , ;, , , . ~' , , 2~722~
commands could be utilized. The data can flow from the peripheral to the device and then to the computer or from the computer to the device and then to the peripheral. The peripherals are controlled by the device on a real -time basis and the computer is not burdened with the task o monitoring multiple devices.
The computer can determine if data has been received from a peripheral by sending an enquiry to the device.
A microprocessor or CPU of the device has a memory with power fail detect and battery backup so that any data in the memory is retained during a power failure.
The data is stored in buffers in an on-board static RAM (Random Access Memory).
In utilizing the device, at least one peripheral will be connected to the device.
Preferably, at least one of the peripherals is selected from the group of a bar code scanner, a receipt/journal printer, a coin dispenser, a scales, a display, a credit card verifier, a cash drawer solenoid, a cash drawer, a keyboard, a non-coded magnetic card reader and a liquid crystal display.
This group is specific to the retail industry and is not considered to be exhaustive. Numerous other peripherals can be connected to the device, either one at a time or collectivelY.
The device can contain any number of interfaces which are connected into the data bus of the device. For example, the interfaces can be a serial I/O multiplexer, a cash drawer interface, a keyboard interface, a magnetic card interface and a liquid crystal display interface. It is not necessary that all of these interfaces or any of them be utilized in a particular device. ~ particular device could be manufactured with only one of these . ~ .. , :

~2220 interfaces or with an inter~ace that is different from any of these interfaces.
The serial inputtoutput multiplexer consists of five RS-232 ports. Various devices can be connected into these ports. For example, a bar code scanner, a receipt/journal printer, a coin dispenser, a scales, a customer display, a credit card verifier or other RS-232 devices ~hich can implement an RTS/CTS
(Request to Send/Clear To Send) handshaking protocol.
The cash drawer interface can fire a 12 volt solenoid to open or close a cash drawer. Since the electric current required to drive a cash drawer solenoid is greater than that at which the 12 volt supply on the computer is rated, capacitors are uti~ized to store the energy required to fire the solenoid. The capacitors charge slowly from the computer's power supply after firing the cash drawer solenoid. In addition, the cash drawer interface can sense the status of the cash drawer and transmit that status to the computer on re~uest to indicate whether the cash drawer is open or closed.
The keyboard interface is capable of connecting to a standard IBM AT compatible keyboard, which include not only the standard "101 keyboards"
but also man~ retail specific keyboards. The interface will buffer keystrokes as they are received and transmit them to the P~ on demand.
The magnetic card interface is used to connect a single or dual track non-coded magnetic card reader to the device. This interface will receive the TTL (Transistor-Transistor Logic) data, clock and card present signals from either a single or dual track magnetic card reader. The serial data is input and ,. ~

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stored as ASCII characters to be sent to the computer when requested.
The liquid crystal display interface can be used, for example, to connect a 2 line by 20 character DOT ~ATRIX display to the device. The display is connected via a TTL level paral~el port on the device.
Data to be displayed is sent from the computer to the device along with a command to indicate which line of the display the data is to be placed on.
The peripherals are connected to one of the interfaces of the device via RJ 12 connectors on the back edge of the PC board of the device. The magnetic card reader is connected to a 10 pin dual row header and the display is connected to a 14 pin dual row header.
As shown in Figure 2, the microprocessor ~designated as CPU in Figure 1 and IC 32 in Figure 2) of the device consists of an 8 bit microcontroller with an integrated timer, interrupt controller and UART. A programmable array logic chip (PAL) at IC 12 is used in conjunction with a 3 to 8 decoder (IC 33) to decode the address lines and provide chip select signals necessary for the microcontroller to access its memory and peripheral circuits.
An 8 bit latch (IC 29) is used to provide output control signals to the AT interface (CTS -Clear to Send; DSR - Data Set Ready; DCD - Data Carrier Detect; RI - Ring Indicator). These are the standard control signals found on a standard communications port for a computer. In addition, 3 bits from this latch are used to control the output rate of a baud rate generator circuit (IC 19 and IC 4 used for the serial input/output multiplexer circuit.
The last bit on the latch is used to turn on and off , ., : . .

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the 12 volt programming supply xequired by the flash ROM chip. This output bit contxols transistor Q1 of Figure 3.
The crystal X1 is used to generate the clock signal for the microcontroller as well as feed the baud rate generator circuit to the UART in the AT
interface (IC 13 in Figure 3). The UART con-tained in the microcontroller is used to transmit and receive data to and from the UART in the interface circuit in Figure 4.
In Figure 3, it can be seen that the microprocessor (IC 32 in Figure 2) utilizes an EPROM
(IC 35) and a FLASH ROM (IC 6) to contain its program.
The ROM contains a code to allow the microcontroller to start after a reset and a code to allow the programming of the FLASH ROM. Once the FLASH ROM is programmed, the microcontroller fetches its instructions from the FLASH ROM. This allows the computer to send a new pro~ramming file to update the ~irmware of the device rather than physically replacing the EPROMS. The firmware resident in the FLASH ROM contains the necessary code to interface the desired peripherals to the invention and the protocol used to communicate to the computer via the serial port.
An 8K static ram is located at IC 22 and is used as a buffer to hold data being transferred between the peripherals and host computer.
Transistors Q1 and Q2 are used to turn on and off the 12 volt power supply connected to the FLASH ROM (IC
6). The 12 volts is turned on when the flash is being programmed.
In Figure 4, it can be seen that the AT
interface circuit is the connection between the , : ~ :
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microprocessor on the device and the computer. This interface is designed to emulate a standard serial communications port on a computer. A dual row header at H12 is used as a jumper ~lock to select which o the our COM port addresses within the computer the invention is to reside at. A dual row header at Hll is used as a jumper block to select which interrupt the board will generate to the computer. The board can be set to interrupt 3, 4, 5 or 7. The jumper at Hll will enable one of the four tri-state buffers wi~hin IC 26 and allow a UART at IC 13 to generate the selected interrupt to the computer.
A programmable array logic chip t PAL ) at IC
11 is used in conjunction with the setting from the jumper block H12 to decode the computer's address lines and generate a chip select signal for the UART
at IC 13.
The UART at IC 13 receives parallel data from the computer and converts it into a serial data stream as would a standard serial communications port in a computer. Serial data received by this UART is conve~ted into parallel data and passed to the computer. Normally this serial data would be converted to and from RS-32 signal levels and routed to a connector on the back of the computer. In this invention however~ the serial data is fed to and from the UART on the microprocessor of the device (IC 32 in Figure 2). In this way, the device is interfaced to - the computer in a manner which allows programmers to utilize standard communication routines to access the device from their programs on the computer.
Control lines ( CTS, DSR, DCD, RI ~ are inputs to the UART (IC 13) and are set by an 8 bit latch (IC
9 of Figure 2) which is controlled by the _ g _ 2~2~2~
microprocessor of the device. IC 20 is used to divide the 12 MHz clock signal (X1 Figure 2) down to 4 MHz to provide the input clock for the baud rate generator internal to the UART at IC 13.
In E'igures 5 and 6, the serial input/output multiplexer is used to interEace five serial RS-232 peripherals to the device. The interface between the peripheral and the device consists of the following four signals:
(a) RXD - Receive Data: Serial data is transmitted from the peripheral to the device on this line;
(b) TXD - Transmit Data: Serial data is transmitted from the device to the peripheral on this line;
(c) RTS - Request To Send: The peripheral will set the line when it wishes to transmit data to the device; and (d) CTS - Clear To Send: The device will set this line when it is ready to receive data from the peripheral.
Each of the five RS-232 ports utilize the same circuit design. The design for one of the ports, Port A is described. The serial input/output multiplexer interface in the device uses an RTS/CTS
hardware handshaking protocol. When a peripheral wishes to transmit data to the device, it will set its RTS line. This line is converted from an RS-232 level to a TTL level by IC 25. This TTL level RTS signal connects to a parallel input port ~see Figure 9, IC
27), which can be read by the microprocessor of the device to determine the status of all of the RTS
lines. The signal is also fed to ~ NOR gate (IC 29) which is used in conjunction with the 8 bit latch at ' , , , ,, , , , -.

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IC 10 to disable the RTS signal from any selected ports. By writing a 1 to the corresponding bit in the latch, OKASIS the output of the NOR gate is held at a zero regardless of the state of the RTS line. The output of the NOR gate is ~ed through an open collector inverting buffer. The outputs of these bu~fers axe connected together in a wired OR and fed to interrupt 1 of the microprocessor ~IC 32 of Figure 2).
This system enables any of the RS-232 peripherals to interrupt the microprocessor of the device as long as it is not masked off by the latch setting (IC 10). When the microprocessor receives an interrupt 1, it reads the input port (Figure 9, IC 27) to determine which port is requesting service. The magnetic card reader also generates an interrupt 1 through the card's present line via IC 29 and IC 16.
Data received on the RXT line is converted from RS-232 to TTL level by IC 24. This data is then fed through an 8 to 1 demultiplexer (IC 3). The output of IC 3 goes to the receive data pin on the UART at IC 18 where it is converted into parallel data to be read by the invention CPU. As stated above, the demultiplexer is controlled by 3 bits on the latch at IC 8~
Serial data, as shown in Figure 6, is transmitted from the UART (IC 18, Figure 5~ and converted to RS-232 level by the RS-232 driver IC 2.
This data then passes through a 1 of 8 multiplexer 30 which is controlled by 3 bits on latch IC 9 and is directed to the specified port connector on a TXD
line.
Five bits from an ~ bit latch (IC 8) are used to enable and disable CTS on each of the RS-232 - , ,:

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ports. The outputs from this latch are converted to RS~232 signals by IC 1 and IC 2 and fed to each of the 5 ports. The remaining 3 bits on this latch are used to select which port connector is connected to receive and transmit llnes of the UART at IC 18 of Figure 5.
This system allows multiple RS-232 devices to be connected to a signal UART on the invention.
As described in Figure 7, the cash drawer interface consists of two channels, each capable of firing a 12 volt solenoid and sensing whether a remote switch is opened or closed. By writing to the address selected by the device 2 line with A0, A1 and A2 selected appropriately, the microprocessor or CPU of the device can cause the Y or the Yl output device IC
14 to toggle low. This will create a short pulse on the input on the monostable multivibrator (IC 15) which will create a pulse of sufficient duration ~or a solenoid driver (IC 21) to cause a peripheral solenoid connected to either H6 or H7 to fire. By driving the solenoid in a cash drawer the invention causes the drawer to open. Since the current required to drive the solenoid is above that of the specified rating of the power supply resonant in most computers, capacitors C1 and C2 are used to restore the energy required to fire the solenoids. After firing, the solenoids are charged through resistor 23.
An input line SENSE1 or SENSE2 is also present on cash drawer connectors H6 and H7. This line is normally pulled low but can be pulled to plus 12 volts by a switch internal to the remote cash drawer. The resistor pairs R19, R13, R18 and R14 act as voltage dividers to produce a TT~ level signal at SENSElA and SENSE2A. The signals are fed into 2 bits of a parallel input port on IC 27 in Figure 9.

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As shown in Figure 8, a magnetic card readerinterface is provided via connector H10. This connector provides the necessary signals to inferface a dual track non-coded magnetic card reader to the invention. There are ive signals present on the connector: data and strobe for each of the two tracks and a card present line.
Since each of the two tracks are electrically identical, the description of the circuit will refer to the components for track 1.
The data line is connected directly to a parallel input port (IC 27, Figure 9) where they can be read by the microprocessor of the device. The strobe signal is connected to the clock input of a J-K
lS flip-flop (IC 31). Each time ~he clock toggles, a 1 is latched into the flip-flop. The output of the flip-flop is connected to an output hit of the microprocessor (IC 32 of Figure 2). When a 1 is seen by the microprocessor on this output bit, the data is read via the parallel port (IC 27 of Figure 9). The microprocessor then writes to the address decoder (C14 of Figure 5) which has its Y to select the line connected to the clear input of the flip-flop. This clears the output bit of the flip-flop and the 25 microprocessor will wait for the bit to become a 1 ~-again before reading the net data bit.
When a magnetic stripe card is inserted into ;

the card reader, the reader will set the card present line on the connector H10. This signal is connected to the interrupt 1 line of the microprocessor via an inverter (IC 29 of Figure 4) and an inverting, open collector buffer (IC 16 of Figure 4). When the microprocessor receives this interrupt, it will begin watching the strobe and data lines described above.

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As shown in Figure 9, -the device has a power fail interrupt circuit connected to the microprocessor to provide a battery backup voltage to the static RAM
resident on the device in the case of a power failure.
IC 3~ is used to buffer and invert the reset line from the computer. When power is removed rom the computer, the RESETDRV line will go high and cause the output of IC 34 to go low. This output is connected to the INTERRUPT zero line on the microprocessor of the device. When the microprocessor receives this interrupt, it will perform an orderly shutdown.
The output of IC 34 also feeds another AND
gate which combines this reset line with the reset generated by the power supervisory chip (IC 30) to provide reset (RST) and not reset (/RST) to the rest o the device in case of a power failure.
The power supervisory chip (IC 30) also switches the battery (B1) onto the VRAM line, in place of the computer's 5 volt supply in the event of a power failure. While the circuit is powered, the battery is charged from the computer's 5 volt supply through R20 and D10.
Jumper S2 may be used to permanently engage ~ the /RST line to prevent the loss of data in the `; 25 static RA~ during shippin~ and handling by placing it in the RAM OFF ~osition. This jumper must be placed ; in the RAM ON position prior to installing the ~ invention in a computer.
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`~ The keyboard interface consists of four wires, five volts (SPL1), ground (SPL0), DATA and clock (KEYCLK). The keyboard is connected to the ~ invention via connector H5. Data is transmitted to - and from the keyboard on the data line. Data is transferred from the microprocessor of the device on ~` 2~72220 the KEY DATA OUT LINE to the IC 17 pin 1 and to the microprocessor on the KEY DATA IN LIN~. The microprocessor drives the clock signal via the KEY
CLOCK OUT LINE through IC 17, pin 3 and receives the clock signal on the KEY Cl,OCK IN LINE.
In Figure 11, there is shown a 2 line by 20 character liquid crystal display module connected to the device via connector H9. The data bus to the LCD, DBO-DB7 on H9 is input to and output from the device microprocessor via parallel port on IC 27. IC 27 also provides 3 control line outputs from the 1CD (RS, R/W
and E). RS is used to select the data of an address register of the LCD. R/W determines whether the microprocessor of the device will read data from the lS LCD or write data to the LCD module. E is used to enable the LCD module to receive or transmit data.
The contrast o the LCD is controlled by potentiometer RVl or may be set to a fixed setting by installing R15 and R16 in the place of RVl. IC 27 receives data from and transmits data to the microprocessor of the device (Figure 2, IC 32 and to the 8 bit data bus CPUDATA). IC 27 consists of three ~ separate 8 bit parallel input/output ports. Port A
: (PA0 to PA7) is used to send and receive data to the LCD as described above. Port C (PC5 to PC7) iS used as control lines to the LCD. Port D and the remainder of Port C are utilized in other portions of the circuitry of the device and have been described above.
; In general terms, data received from the computer by the device is passed through to the microprocessor. The microprocessor then processes the data ~ased on a proprietary protocol and passes the required information to the desired peripheral or returns data that it has received from the peripheral ,: , i , ~

2~72220 to the computer. The invention may be operated inpolled mode with the host computer prompting for data or in the interrupt driven mode with the peripheral indicating to the microprocessor that it requires attention. In this case, the microprocessor will cause an interrupt to be enabled on the bus o~ the host computer.
The data coliected from or sent to the peripherals is queued and buffered in the order it is received from said peripherals, allowing input from the peripherals to exceed the speed with which the computer would otherwise be able to handle this data.
The software operating on the computer can re~uest data from the device as it is ready to accept data.
There are two UARTS, one on the host computer's peripheral expansion bus and the other on the data bus of the microprocessor of the device. The UART on the computer is a standard UART used by the computer. For example, on an IBM PC or AT, this would either be an 8250 or a 16450 UART. Da~a is passed between the bus of the microprocessor and the bus of the computer via this pair o~ UARTS. Data received by the microprocessor of the device is processed based on the commands received by the microprocessor~ The data can be sent to any of the periphexals through another UART
(where applicable~ and appropriate interface components such as RS~232 or RS-485 drivers, etc.
Data received from the peripherals passes through the appropriate interface circuitry (i.e. RS-232 receivers, level translators, etc.~ and is sent to store the data in First In First out buffers (FIFO's) to be passed onto the host computer upon request.
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Claims (17)

1. A device to interface peripherals to a standard computer without changing the computer bios, said computer having a bus and at least one asynchronous port, said device comprising a printed circuit board containing a microprocessor, said circuit board being connected to said bus of the computer to emulate said asynchronous port, at least one peripheral being connected to said device, the microprocessor transmitting data between the computer and the peripheral to control said peripheral.

2. A device as claimed in Claim 1 wherein the device has a card edge connector and an AT interface with address, data and control lines connected between the card edge connector and said AT interface, said AT
interface being set up as one of the asynchronous ports of the host computer.

3. A device as claimed in Claim 2 wherein the microprocessor contains a universal asynchronous receiver transmitter to communicate with the computer.

4. A device as claimed in Claim 3 wherein a memory is connected to the microprocessor to store data transmitted between the peripherals and the computer.

5. A device as claimed in Claim 4 wherein the memory has a battery backup circuit connected thereto.

6. A device as claimed in Claim 5 wherein there is a data bus connected to the microprocessor, said data bus containing at least one interface which is connected to said at least one peripheral.

7. A device as claimed in Claim 6 wherein each peripheral is connected by a connector to an interface in the data bus.

8. A device as claimed in Claim 7 wherein there are a plurality of peripherals and one connector for each peripheral with a plurality of interfaces in the data bus.

9. A device as claimed in Claim 8 wherein the interfaces in the data bus are at least one selected from the group of a serial input/output multiplexer, a cash drawer interface, a keyboard interface, a magnetic card interface and a liquid crystal display interface.

10. A device as claimed in Claim 9 wherein the at least one peripheral is selected from the group of a bar code scanner, a receipt/journal printer, a coin dispenser, a scales, a display, a credit card verifier, a cash drawer solenoid, a cash drawer, a keyboard, a non-decoded magnetic card reader and a liquid crystal display.

11. A device as claimed in Claim 10 wherein the microprocessor is an eight bit microcontroller with an integrated timer, interrupt controller and universal asynchronous receiver transmitter.

12. A method of interfacing peripherals to a standard computer without changing the computer bios where the computer has at least one asynchronous port and a bus using a device that is a printed circuit board and contains a microprocessor, said method comprising installing the device in the bus of the computer so that the device will emulate said asynchronous port, connecting at least one peripheral to said device and communicating between the computer and the microprocessor using commands to control said peripheral.

13. A method as claimed in Claim 12 wherein the method includes the step of utilizing ACSII commands for communications between the computer and the microprocessor.

14. A method as claimed in Claim 13 wherein the method includes the step of connecting at least one peripheral to the device, said peripheral being selected from the group of a bar code scanner, a receipt/journal printer, a coin dispenser, a scales, a customer display, a credit card verifier, a cash drawer solenoid, a cash drawer, a keyboard, a non-decoded magnetic card reader and a liquid crystal display.

15. A method as claimed in any one of Claims 12, 13 or 14 wherein the device has a memory and the method includes the steps of monitoring the at least one peripheral and storing data received from the at least one peripheral in said memory.

16. A method as claimed in any one of Claims 12, 13 or 14 wherein the method includes the step of controlling the at least one peripheral on a real time basis.

17. A method as claimed in any one of Claims 12, 13 or 14 wherein the device has a memory and the method includes the steps of queuing data from the peripherals in said memory, allowing input from the peripherals to exceed the speed with which the computer can handle this data, operating the computer to request data from the device as it is ready to accept data.