SI2759081T1 - Sistem in postopek za sinhronizacijo urnih signalov - Google Patents

Sistem in postopek za sinhronizacijo urnih signalov

Info

Publication number
SI2759081T1
SI2759081T1 SI201230803A SI201230803A SI2759081T1 SI 2759081 T1 SI2759081 T1 SI 2759081T1 SI 201230803 A SI201230803 A SI 201230803A SI 201230803 A SI201230803 A SI 201230803A SI 2759081 T1 SI2759081 T1 SI 2759081T1
Authority
SI
Slovenia
Prior art keywords
synchronization
systems
methods
clock signals
clock
Prior art date
Application number
SI201230803A
Other languages
English (en)
Inventor
Philip Secker
Emerick Vann
Original Assignee
Aviat Networks, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aviat Networks, Inc. filed Critical Aviat Networks, Inc.
Publication of SI2759081T1 publication Critical patent/SI2759081T1/sl

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0691—Synchronisation in a TDM node
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0647—Synchronisation among TDM nodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/12—Arrangements providing for calling or supervisory signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
SI201230803A 2011-09-22 2012-09-24 Sistem in postopek za sinhronizacijo urnih signalov SI2759081T1 (sl)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201161538089P 2011-09-22 2011-09-22
PCT/US2012/056948 WO2013044249A1 (en) 2011-09-22 2012-09-24 Systems and methods for synchronization of clock signals
EP12833217.8A EP2759081B1 (en) 2011-09-22 2012-09-24 Systems and methods for synchronization of clock signals

Publications (1)

Publication Number Publication Date
SI2759081T1 true SI2759081T1 (sl) 2017-01-31

Family

ID=47914957

Family Applications (1)

Application Number Title Priority Date Filing Date
SI201230803A SI2759081T1 (sl) 2011-09-22 2012-09-24 Sistem in postopek za sinhronizacijo urnih signalov

Country Status (7)

Country Link
US (2) US9014215B2 (sl)
EP (1) EP2759081B1 (sl)
CN (1) CN103988452A (sl)
MY (1) MY164136A (sl)
SG (1) SG11201400861YA (sl)
SI (1) SI2759081T1 (sl)
WO (1) WO2013044249A1 (sl)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108604979B (zh) * 2016-02-02 2021-05-18 马维尔亚洲私人有限公司 用于网络同步的方法和装置
US10476509B2 (en) * 2016-12-07 2019-11-12 Integrated Device Technology, Inc. Time slotted bus system for multiple coupled digital phase-locked loops
WO2020256631A1 (en) * 2019-06-18 2020-12-24 Razer (Asia-Pacific) Pte. Ltd. Method and apparatus for optimizing input latency in a wireless human interface device system
CN112751614B (zh) * 2020-12-24 2022-03-04 北京无线电计量测试研究所 一种基于两站间的阿秒级光纤时间传递方法
CN112948220A (zh) * 2021-03-30 2021-06-11 联想(北京)信息技术有限公司 背板控制方法、装置及计算机设备
CN114640375B (zh) * 2022-03-18 2023-12-26 北京无线电计量测试研究所 一种确定时钟相位调制解调器系统及使用方法

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE514986C2 (sv) * 1995-03-01 2001-05-28 Telia Ab Metod och anordning för synkronisering vid OFDM-system
US5638010A (en) * 1995-06-07 1997-06-10 Analog Devices, Inc. Digitally controlled oscillator for a phase-locked loop providing a residue signal for use in continuously variable interpolation and decimation filters
US6307868B1 (en) * 1995-08-25 2001-10-23 Terayon Communication Systems, Inc. Apparatus and method for SCDMA digital data transmission using orthogonal codes and a head end modem with no tracking loops
US5940137A (en) * 1996-03-01 1999-08-17 Trw Inc. Symbol timing generation and recovery for data transmission in an analog video signal
DE19608666A1 (de) * 1996-03-06 1997-09-11 Bosch Gmbh Robert Verfahren und Anordnung zur Ableitung von mehreren Taktsignalen
US6243369B1 (en) * 1998-05-06 2001-06-05 Terayon Communication Systems, Inc. Apparatus and method for synchronizing an SCDMA upstream or any other type upstream to an MCNS downstream or any other type downstream with a different clock rate than the upstream
US6782007B1 (en) * 1999-01-26 2004-08-24 Samsung Electronics Co., Ltd. TDM bus synchronization circuit and protocol and method of operation
US7227918B2 (en) * 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
GB2369940B (en) * 2000-12-09 2004-10-20 Mitel Corp Multiple input phase lock loop with hitless reference switching
US7043651B2 (en) * 2001-09-18 2006-05-09 Nortel Networks Limited Technique for synchronizing clocks in a network
US7158596B2 (en) * 2002-08-14 2007-01-02 Standard Microsystems Corp. Communication system and method for sending and receiving data at a higher or lower sample rate than a network frame rate using a phase locked loop
WO2004034619A2 (en) 2002-10-09 2004-04-22 Acorn Packet Solutions, Llc System and method for rate agile adaptive clocking in a packet-based network
US7103072B1 (en) * 2002-12-19 2006-09-05 Occam Networks System and method for synchronization of devices across a packet network
US7966422B2 (en) * 2003-02-18 2011-06-21 Broadcom Corporation System and method for communicating between servers using a multi-server platform
US7126378B2 (en) * 2003-12-17 2006-10-24 Rambus, Inc. High speed signaling system with adaptive transmit pre-emphasis
US8019035B2 (en) * 2003-08-05 2011-09-13 Stmicroelectronics Nv Noise shaped interpolator and decimator apparatus and method
CA2454983A1 (en) * 2004-01-07 2005-07-07 Jean Beaucage System for high-speed applications over serial multi-drop communication networks
WO2006029511A1 (en) * 2004-09-13 2006-03-23 Nortel Networks Limited Method and apparatus for synchronizing internal state of frequency generators on a communications network
US7590210B2 (en) * 2004-09-13 2009-09-15 Nortel Networks Limited Method and apparatus for synchronizing internal state of frequency generators on a communications network
US20060221936A1 (en) * 2005-03-31 2006-10-05 Rauchwerk Michael D Timing recovery for modem transmission on IP networks
US7835366B2 (en) * 2005-11-01 2010-11-16 Ciena Corporation Three-way message exchange clock synchronization
US7501867B2 (en) * 2006-09-14 2009-03-10 Rambus, Inc. Power supply noise rejection in PLL or DLL circuits
FR2911460A1 (fr) * 2007-01-16 2008-07-18 Thomson Licensing Sas Initialisation rapide de la base de temps video generant un signal de synchronisation dans un reseau a commutation par paquets
JP4679640B2 (ja) * 2007-02-21 2011-04-27 パナソニック株式会社 最尤復号装置及び情報再生装置
WO2008114205A2 (en) * 2007-03-20 2008-09-25 Nxp B.V. Fast powering-up of data communication system
CN101051836B (zh) * 2007-03-30 2012-01-11 北京中星微电子有限公司 传输流解码与编码定时同步的装置及方法
US7966510B2 (en) * 2007-11-30 2011-06-21 Alcatel Lucent Dynamic frequency adjustment for interoperability of differential clock recovery methods
US7821958B2 (en) * 2007-12-21 2010-10-26 Belair Networks Inc. Method for estimating and monitoring timing errors in packet data networks
US7902928B2 (en) * 2008-02-08 2011-03-08 Mediatek Inc. Phase-locked circuit employing capacitance multiplication
EP2139168A1 (en) 2008-06-25 2009-12-30 Thomson Licensing, Inc. Method and device for time synchronization in a TDMA multi-hop wireless network
US8942561B2 (en) 2008-10-21 2015-01-27 Broadcom Corporation Synchronization transport over passive optical networks
US8467418B2 (en) * 2008-11-10 2013-06-18 Rockstar Consortium Us Lp Differential timing transfer over synchronous ethernet using digital frequency generators and control word signaling
US8258870B2 (en) * 2009-08-14 2012-09-04 That Corporation System and method for digital control of amplifier gain with reduced zipper noise
US8416019B2 (en) * 2009-08-14 2013-04-09 That Corporation System and method for interpolating digitally-controlled amplifier gain
SG178498A1 (en) * 2009-08-21 2012-04-27 Aviat Networks Inc Synchronization distribution in microwave backhaul networks
EP2526623A2 (en) * 2010-01-21 2012-11-28 Rambus Inc. Phase detection circuits and methods
US9077349B2 (en) * 2012-02-21 2015-07-07 Qualcomm Incorporated Automatic detection and compensation of frequency offset in point-to-point communication
US9014322B2 (en) * 2012-05-23 2015-04-21 Finisar Corporation Low power and compact area digital integrator for a digital phase detector
US9036764B1 (en) * 2012-12-07 2015-05-19 Rambus Inc. Clock recovery circuit

Also Published As

Publication number Publication date
EP2759081B1 (en) 2016-11-16
US9608754B2 (en) 2017-03-28
CN103988452A (zh) 2014-08-13
SG11201400861YA (en) 2014-04-28
US9014215B2 (en) 2015-04-21
US20130100967A1 (en) 2013-04-25
EP2759081A1 (en) 2014-07-30
MY164136A (en) 2017-11-30
WO2013044249A1 (en) 2013-03-28
US20150180600A1 (en) 2015-06-25
EP2759081A4 (en) 2015-04-29

Similar Documents

Publication Publication Date Title
EP2788890A4 (en) SYSTEMS AND METHODS FOR AUTOMATIC SYNCHRONIZATION OF RECENTLY MODIFIED DATA
EP2681671A4 (en) SYSTEMS AND METHODS FOR FACILITATING DATA SYNCHRONIZATION
EP2696283A4 (en) METHOD AND SYSTEM FOR SYNCHRONIZING APPLICATIONS BETWEEN DEVICES
EP2734904A4 (en) SYSTEMS AND METHODS FOR NETWORK SYNCHRONIZATION
GB2491757B (en) Method and apparatus for clock synchronization
ZA201403947B (en) Systems and methods for time synchronization of ieds via radio link
SG11201401210XA (en) Time and frequency synchronization
EP2596675A4 (en) METHODS OF MANAGING MULTIPLE TIME ADVANCE GROUPS
EP2717787A4 (en) ADVANCED ENDOVASCULAR CLIP AND METHOD OF USE THEREOF
IL222263A0 (en) Methods of and systems for producing biofuels
PL2550509T3 (pl) Sposób i system synchronizacji czasowej fazy sygnałów dostarczanych z poszczególnych urządzeń pomiarowych
EP2744579A4 (en) CONNECTED MULTIFUNCTIONAL SYSTEM AND METHOD OF USE
HK1208297A1 (en) Methods and systems for clock correction and or synchronization for audio media measurement systems
HK1202754A1 (en) Multi-stage timing and frequency synchronization
ZA201309750B (en) Gasification system and method
EP2738971A4 (en) METHOD AND DEVICE FOR SYNCHRONIZING CLOCKS
HK1181580A1 (zh) 數據同步方法及系統
EP2723684A4 (en) METHOD AND SYSTEM FOR CONTROLLED SYNTHESIS OF NANODIAMANTS
GB201115119D0 (en) Generation of digital clock for system having RF circuitry
SG11201400861YA (en) Systems and methods for synchronization of clock signals
EP2700171A4 (en) SYSTEM AND METHOD FOR CUTTING SIGNALING
ZA201407271B (en) Methods and systems for sacccharification of biomass
ZA201305949B (en) System and method for session synchronization with independent external systems
EP2772087A4 (en) METHOD AND SYSTEM FOR REDUCING INTERFERENCE BETWEEN ADJACENT SATELLITES
HK1165635A1 (en) The receiving method and receiving system of atomic frequency signal