SI23065A - Procedure and circuit for automatic tuning of antenna circuit - Google Patents

Abstract

The antenna circuit (A) is powered by a signal whose frequency shall be tuned, and the capacitance of the antenna circuit shall change gradually according to the algorithm inside the controller (C). During this, at the first and second terminal (1, 2) the voltage phase of the capacitive element featuring one type of reactance inside the antenna circuit is determined, the phase difference of the specified voltage phases is assessed, while the capacitance of the antenna circuit is modified as long as the specified phase difference comes close to Pi/2 closer from the smallest change of phases which can be attained by capacitance modification. The resulting setting is stored as the setting of the antenna circuit tuned to the specified frequency. The tuning of the antenna circuit to the frequency of the carrier signal is by the procedure and circuit according to the invention automatically performed in an effective way from the aspect of time and in particularly in the first application case also very simply, since no analogue-digital conversion of the output signal by the phase detector is required.

Description

AUSTRIAMICROSYSTEMS AG, Schloss Premstatten, A-8141 Unterpremstatten

IDS Ltd., Sojerjeva Street 63, SI-1000 Ljubljana

Procedure and circuit for automatic tuning of the antenna circuit

The invention relates to a method for automatically tuning an antenna circuit, for example in an RFID interrogator, wherein the antenna circuit is fed by a carrier signal at which frequency the antenna circuit is tuned, and the reactance of the antenna circuit is changed step by step until tuned is reached configuration of an antenna circuit whose natural frequency is the same or at least near the frequency of the carrier signal. The invention also relates to a circuit for performing the proposed method.

The invention is classified in class H 04B 01/40 according to the international classification of patents.

The antenna circuit in the RFID interrogator is designed so that its natural frequency is equal to that of the carrier signal. In this way, the carrier signal becomes as strong as possible. The interrogator can then provide sufficient power to the passive transponder via inductive coupling.

The interrogator antenna circuit tunes to the carrier frequency of the RFID system for better overall system performance. It is first tuned during fabrication when the actual values of the antenna circuit components deviate from the nominal values.

RFID interrogators are also known, comprising a means for automatically tuning their antenna circuit to the carrier frequency. The tuning circuit in such an RFID interrogator automatically compensates for environmental influences such as changes in temperature and humidity or the presence of a metal object nearby.

The antenna circuit is tuned to set the value of the capacitive reactance element, the inductive reactance element, or both. Most often, the value of an element with capacitive reactance is set by connecting additional condensates or disconnecting them by means of controlled switches.

A typical circuit diagram for tuning antenna circuit A is shown in FIG. 1. An alternator G with frequency f _{cs of the} carrier signal is connected to the series capacitor cO, cl, ..., one and a co coil, the other end of which is connected to ground through the driver D. The capacitive reactance element is a capacitor cO and connected to it via switches sl to sn, which are controlled by controller C, in parallel connected capacitors cl to cn. The voltage in the joint terminal of the capacitor cO, cl, cn and coil co is detected by a PD detector whose output is connected to controller C via the ADC analog converter C. The natural frequency f _{n of the} co-connected basic capacitor cO and co coil is higher than the frequency f _{cs of the} carrier signal, and approaches the frequency of f _{cs of the} carrier signal when the condensatoi cl to cn are connected. The current i _cs flowing through the antenna circuit A increases and is greatest when the natural frequency f _{n of the} tuned antenna circuit A is equal to or near the frequency f _{cs of the} carrier signal (Fig. 2a). The same applies to the voltage detected by the PD PD detector by which controller C adjusts the sl to sn switches. The sl to sn switches are controlled by the algorithm to obtain the maximum value of said voltage. However, the maximum value of this voltage, which is to be achieved, is by no means known in advance. The voltage value in each step and the corresponding setting of antenna circuit A must be stored each time. The stored voltage value is then compared with the voltage value in the next step. The antenna circuit setup from the previous step may turn out to be the best tuning that can be achieved. It must be stored again. Of course, such an algorithm is not the most time efficient.

Thus, the RFID label interrogator is equipped with a unit that automatically adjusts the interrogator antenna circuit to the natural frequency of the antenna circuit in the RFID label by successive approximations, changing the interrogator antenna circuit against the maximum voltage across it or the maximum current through it (EP 0 625 832 WOULD).

Furthermore, there is a known RFID interrogator which is equipped with a current or voltage detector that is connected to an antenna circuit and a decision circuit that changes the interrogator antenna circuit against the excitation signal to the detector output signal (US 6 650 227 BI).

The RFID interrogator, equipped with signal generators and antenna, adjustable to the maximum radiated power by means of a microprocessor, which is determined by the peak detector on the received label signal (EP 1 770 665 BI).

On the other hand, the following feature of antenna circuit A is also well known as a circuit in which resonance occurs when an electric current is driven through it. The driving voltage u _o cos _QS ts the frequency f _cs (<o _cs = 2Ttf _cs ) of the carrier signal through the antenna circuit drives the current i ₀ cos (b) _C st + <f> _cs ), which at a frequency f _fs below the natural frequency f _{n of the} antenna circuit exceeds the driving voltage and at a value of frequency f _cs above the value of said natural frequency f _n lags behind the driving voltage, and at f _cs = f _n the phase angle (f> _cs equals zero (Fig. 2b). of the capacitor cO, cl, ..., cn the time course of the voltage is equal to the time course of the driving voltage, therefore u _o cosut, and on the second terminal 2 of this capacitor the time course of the voltage is proportional to cos (u _cs t + <f _cs - Tt / Therefore, at f _cs = f _n , the voltage at the capacitor terminal 2 lags the voltage at the condensate terminal 1 by exactly tt / 2. The voltage at the second coil coil co is, at f _cs = f _n, overtaking the voltage at the first terminal of this coil by exactly τ / 2. When the natural frequency f _{n of the} antenna circuit A equals the frequency f _{cs of the} carrier s The phase angle measured between the voltages at the first and second terminals of both the capacitive element and the inductive element is exactly τ / 2 in absolute value. The antenna circuit A is then tuned to the frequency f _{cs of the} carrier signal. The value of said phase angle, as the observable value by which tuning is now sought, is known in advance in the state of tuning of antenna circuit A. It is equal to τ / 2. The aforementioned characteristic of antenna circuit A may therefore enable a more time-consuming algorithm to be used.

It is an object of the invention to propose a method and a circuit for automatically tuning an antenna circuit to a specific frequency, using well known phase conditions in a tuned antenna circuit through which alternating current flows.

The said problem is solved by the method of the invention for automatically tuning the antenna circuit defined by the features of the designating part of the first patent claim and by the circuit of the invention for performing the process of the invention defined by the features of the designating part of the eighth or fourteenth claim, and the sub-claims defining variant embodiments.

The tuning of the antenna circuit to the carrier signal frequency is automatically performed in a time-efficient manner by the method and circuit of the invention. The proposed method and circuit are simply feasible especially in the first embodiment where no analogue-digital conversion of the phase detector output signal is required.

The invention will now be further explained in detail based on the description of the embodiments and the accompanying plan showing in FIG. 3 is a circuit according to the invention for automatically tuning the antenna circuit and the antenna circuit only; FIG. 4a and 4b show a first or second embodiment of a digital phase receiver suitable for carrying out the process of the invention for automatically tuning the antenna circuit, FIG. 5 is a simple phase detector of FIG. 6 is a window primer for the first embodiment of said digital phase primer and FIG. 7a and 7b, in the first and second windows, the timing of the input signals and in the third window, the timing of the output signal of said phase detection for cases where the antenna circuit is or is not tuned.

The procedure for tuning antenna circuit A, powered by a transmitter carrier signal of frequency f _cs and tuning to this frequency, is carried out as before, by varying the reactance of antenna circuit A step by step in accordance with an algorithm that is stored in controller C and approximates antenna circuit A to the tune (Fig. 3).

The invention, however, proposes to determine each time the voltage phase at the first terminal 1 and the voltage phase at the second terminal 2 of an element with a reactance of one type, such as a capacitor cO, cl, ... en with capacitive reactance or coils with inductive reactance.

The next step is to determine the difference between these phases of the mentioned voltages.

The reactance of antenna circuit A is then changed so many times that the said phase difference approaches the value of 7t / 2, closer to the smallest change in phase difference, which is still achievable by changing the reactance of antenna circuit A.

The achieved setting of antenna circuit A is saved as tuning of antenna circuit A tuned to the mentioned frequency f _cs .

After determining the phase difference of said voltages, two variants are proposed according to the process of the invention.

After the first variant embodiment, it is determined whether said phase difference is greater than u / 2, less than 7t / 2, or may already be within the selected phase difference window. This window is selected as follows. The mean window height is equal to the output voltage of this phase detector when it measures a phase difference equal to π / 2. The width of the window is equal to the change in said phase difference, which is caused by the step in which the smallest change in the reactance of the antenna circuit is made. In this case, the two-bit information found is transmitted to controller C.

According to the first variant embodiment, the process can be further simplified to determine each time only whether said phase difference is greater than tt / 2 or less than 7γ / 2. In this case, only one-bit information is transmitted to controller C.

In another embodiment, said phase difference is digitized and the digital value of said phase difference is directed to controller C. Controller C determines the position of the limited20 of its digital value relative to the window about which data is entered into controller C.

Controller C then controls the variation of the antenna circuit reactance A such that said phase difference approaches the value of tt / 2. Preferably, said control is performed according to the sequence approximation algorithm.

Also, the tuning circuit of antenna circuit A, which is fed by a transmitter carrier signal with frequency f _cs and which is tuned to that frequency f _cs , is implemented so far with a controller C and a power circuit comprising generator G of the carrier signal with said frequency f _cs and driver D (Fig. 3). The power circuit supplies antenna circuit A with a carrier signal at which frequency f _cs the antenna circuit A should tune. In a known manner, control switches sl, ... sn are installed in antenna circuit A, by which the reactance of antenna circuit A. is changed step by step. The switches sl, ... sn are controlled according to the algorithm in controller C.

The invention proposes, however, that each of the two terminal blocks 1 and 2 of the reactance element of one type in antenna circuit A, for example capacitor cO, cl, ... cn with capacitive reactance or coils co with inductive reactance, is connected to one from the two input terminals of the PhD phase detector (Figs. 4a and 4b), via the voltage io attenuator VA and the voltage comparator Cl and C2, respectively.

However, the signal at point 2 must normally be attenuated before being fed to the voltage comparator C2. The amplitude of this signal is, at f _n = f _cs, for a factor equal to the Q factor of the antenna circuit A higher than the amplitude of the driving voltage. Signal attenuation is performed in the VA voltage attenuator. However, the voltage attenuator VA must be designed as a capacitor voltage divider, otherwise, in conjunction with the capacitance of the voltage comparator C2, it would rotate the signal phase at point 2.

The first terminals of the voltage comparators Cl and C2 are driven by the voltages a and β from said terminal 1, or through said terminal by the voltage attenuator A.

2. The second input terminal of the voltage comparators in Cl and C2 is connected to ground and their output voltage οί or β ′ is maintained at the input terminal of the PhD phase detector.

The PhD phase detector is shown in Fig. 5. The mentioned voltages ri and / 7 are connected to the inputs of the exclusive OR logic exor gate whose output is connected via the rc termination to the output of the PhD phase detector. This is where a steady-state voltage signal γ occurs.

The time course of the ri and / 7 voltages at the input of the PhD phase detector is shown in the first and second windows of Figure 7, respectively, when the voltages at points 1 and 2 and therefore the cl and fi voltages are offset by each other by π / 2. Given that the phase shift really π / 2 shows the level of the output signal γ in the third window in Figure 7, which is at half the height of the voltage level with the phase detector of the PhD input signals. The same signals are also shown in Figure 8, but for the case where the voltages at points 1 and 2 and are offset relative to each other by a phase angle different from π / 2.

According to the first embodiment of the DPhC digital phase comparator according to the invention, the analog output signal γ of the PhD phase detector is fed to the input of the WC window comparator (Fig. 4a). The output signals OH and OL of the WC window comparator are output to io controller C.

Controller C determines from the state of OH, OL signals at the output of the combinatorial logic circuit CL each time whether the determined phase difference is greater than rr / 2, is less than π / 2, or whether it is inside the window at π / 2.

It is a simpler embodiment of the DPhC digital phase comparator of the invention. This example does not require an analog-to-digital converter. The two digital output signals OH and OL of the WC window comparator transmit sufficient data to controller C to control the tuning of antenna circuit A. with an efficient algorithm.

In one of the possible embodiments, the WC window comparator is shown in the figure

6. The input signal γ is fed to the combinatorial logic circuit CL through voltage comparators C 'and C, the second level of which is determined by the voltage dividers VD' or VD.

The level of the center window in the WC window comparator is equal to the output voltage of this PhD phase detector when it measures a phase difference equal to π / 2. For the width of the window in the window comparator WC, however, a change in said phase difference is selected, which is caused by a step at which the smallest change in the reactance of the antenna circuit A.

In another embodiment of the DPhC 'digital phase primer of the invention, however, the output of the PhD phase detector is connected to the ADC (Fig. 4b). The digital output signal 7d of the ADC ADC is fed to controller C. Controller C now also functions as a window comparator.

Further, the circuit of the first and second embodiments of the invention for automatically tuning antenna circuit A is characterized in that the reactance of antenna circuit A by means of controlled switches sl, ... sn is varied step by step so that a PhD phase detector is determined of the voltage phases at both terminal terminals 1 and 2 of said element cO, cl, ... cn or co approximate the value of rr / 2 at a distance that is less than the smallest change in phase difference still achievable by the changes made to the reactance of antenna circuit A.

Preferably, the sequential approximation algorithm is used to approximate the aforementioned voltage phase difference to the value of τ / 2. The adjustment of antenna circuit A thus obtained is stored as tuning of antenna circuit A tuned to said carrier frequency f _cs .

The antenna circuit A of Figure 3 is a series capacitor and coil circuit, but the technical solution of the invention can be applied to a parallel circuit or mixed circuit of this type with the necessary modifications. Also, the proposed technical solution can be applied to a differential-powered antenna circuit A that connects between two anti-phase drivers.

Only antenna circuit A is usually implemented with high voltage controlled switches sl, ... sn (Fig. 3). The voltage amplitude at point 2 of antenna circuit A is, at f _n = f _cs, for a factor equal to the Q-factor of antenna circuit A higher than the amplitude of the driving voltage. If high-voltage transistors of type p and n cannot be manufactured in antenna circuit technology A, antenna circuit A may be made with high-voltage transistors of type n only, but which are connected to ground and not to the driver.

Claims (17)

Patent claims 1. A method for automatically tuning an antenna circuit according to which the antenna circuit is fed with a signal at which frequency the antenna circuit should tune, and the antenna circuit reactance is changed step by step according to an algorithm in the controller, characterized in that it is determined each time voltage phase at the first and second terminal blocks of an element with one type reactance in the antenna circuit to determine the phase difference of said voltages so that the reactance of the antenna circuit changes so many times that said voltage phase difference approaches the value of tt / 2 closer to the smallest change in difference phase, which is achievable with the changes made to the reactance of the antenna circuit and that the achieved tuning of the antenna circuit is stored as tuning to said frequency of the tuned antenna circuit. Method according to claim 1, characterized in that the difference of said voltage phases is determined each time by phase detection and it is determined whether said phase difference is greater than π / 2, smaller than ir / 2, or whether it is inside a window whose the mean height is equal to the output voltage of this phase detector when it measures the phase difference equal to 7r / 2 and this information is transmitted to the controller. Method according to claim 2, characterized in that the width of said window is equal to the change of said phase difference, which is caused by the step of making the smallest change in the reactance of the antenna circuit. Method according to claim 1, characterized in that the difference of said voltage phases is determined each time by a phase detector, said voltage phase difference is digitized and fed to the controller. Method according to any one of the preceding claims, characterized in that the voltage phases at the two terminals of the capacitive element in the antenna circuit are determined. Method according to any one of the preceding claims, characterized in that the voltage phases at the two terminals of the inductive element in the antenna circuit are determined. A method according to any preceding claim, characterized in that the approximation of said voltage phase difference to the value of 7t / 2 is carried out according to the sequence approximation algorithm stored in the controller. An antenna circuit for automatic tuning (A), wherein the tuning circuit comprises a controller (C) and a circuit (G, D) for supplying the antenna circuit (A) with a signal to which frequency the antenna circuit (A) should tune , and the control switches (sl, ... sn) in the antenna circuit (A) are controlled according to the algorithm in the controller (C) such that the reactance of the antenna circuit (A) is varied step by step, characterized in that each of both terminal blocks (1,2) of element (cO, cl, ... cn; co) with reactance of one type in the antenna circuit (A) connected to one of the two phase detector (PhD) input terminals via voltage receiver (Cl, C2 ), the second input terminal of which is connected to ground so that the phase detector output (PhD) is connected to the controller (C) via window primers (WC), to reactance the antenna circuit (A) by means of controlled switches (Fig, ..). . sn) changes step by step so that the phase detector (PhD) determines the difference in voltage phases at the two terminal blocks (1,2) its element (cO, cl, ... en; co) approximates the value of ir / 2 closer to 5 the smallest phase difference, which is still achievable with the changes made to the antenna circuit reactance (A), and that the achieved setting of the antenna circuit (A) is saved as a tuning to said frequency of the tuned antenna circuit (A). io A circuit according to claim 8, characterized in that the level of the center of the window in the window receiver (WC) is equal to the output voltage of said phase detection (PhD) when it measures the phase difference equal to τ / 2. A method according to claim 9, characterized in that 15 that the window width in the window comparator (WC) is equal to the change in said phase difference, which is caused by the step at which the smallest change in the reactance of the antenna circuit (A) is made. A circuit according to any one of claims 8 to 10, characterized in that 20 that said voltage comparators (Cl, C2) are connected to the terminal (1, 2) of the capacitive element (cO, cl, ..., en). A circuit according to any of claims 8 to 10, characterized in that said voltage primers (Cl, C2) are connected to the inductive terminals 25 elements (co). A circuit according to any one of claims 8 to 12, characterized in that an algorithm for approximating said voltage phase difference to the value of tt / 2 is stored in the controller (C) in successive approximation algorithm. An automatic tuning circuit of an antenna circuit (A), wherein the tuning circuit comprises a controller (C) and a circuit (G, D) for supplying the antenna circuit (A) with a signal to which frequency the antenna circuit (A) should tune , and the controlled switches (sl, ... sn) in the antenna circuit (A) are controlled according to an algorithm in the controller (C) such that the reactance of the antenna circuit (A) is varied step by step, characterized in that each of both terminal blocks (1, 2) of element (cO, cl, ... en; co) with reactance of one type in the antenna circuit (A) connected to one of the two phase detector (PhD) input terminals via voltage receiver (Cl, C2 ), the second input terminal of which is connected to ground so that the phase detection (PhD) output is connected to the controller (C) via an analogue analogue transducer (ADC) to reactante the antenna circuit (A) stepwise by means of controlled switches (fig. .. sn) changes in such a way that the phase detection (PhD) will determine the difference of the voltage phases at the two terminals (1, 2) of said element (cO, cl, ... cn; co) approximate the tc / 2 values closer to the smallest change in phase difference still achievable with the changes made to the antenna circuit reactance (A) and to save the achieved antenna circuit setting (A) as a tuning to said tuned antenna circuit frequency (A) . A circuit according to claim 14, characterized in that said voltage primers (Cl, C2) are connected to the terminal (1, 2) of the capacitive element (cO, cl, ..., cn). 16. A circuit according to claim 14, characterized in that said voltage primers (Cl, C2) are connected to the terminals of the inductive element (co). A circuit according to any one of claims 14 to 16, characterized in that an algorithm for approximating said voltage phase difference to a value% / 2 is a sequential approximation algorithm stored in controller (C).