SG99963A1 - A method to form very high mobility vertical channel transistor by selective deposition of sige or multi-quantum wells (mqws) - Google Patents

A method to form very high mobility vertical channel transistor by selective deposition of sige or multi-quantum wells (mqws)

Info

Publication number
SG99963A1
SG99963A1 SG200200221A SG200200221A SG99963A1 SG 99963 A1 SG99963 A1 SG 99963A1 SG 200200221 A SG200200221 A SG 200200221A SG 200200221 A SG200200221 A SG 200200221A SG 99963 A1 SG99963 A1 SG 99963A1
Authority
SG
Singapore
Prior art keywords
mqws
sige
channel transistor
vertical channel
high mobility
Prior art date
Application number
SG200200221A
Other languages
English (en)
Inventor
Zhen Zheng Jia
Chan Lap
Quek Elgin
Sundaresan Ravi
Pan Yang
Yong Meng Lee James
Keung Leung Ying
Ramachandramurthy Pr Yelehanka
Original Assignee
Chartered Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chartered Semiconductor Mfg filed Critical Chartered Semiconductor Mfg
Publication of SG99963A1 publication Critical patent/SG99963A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66916—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN heterojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
SG200200221A 2001-01-19 2002-01-10 A method to form very high mobility vertical channel transistor by selective deposition of sige or multi-quantum wells (mqws) SG99963A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/765,040 US6455377B1 (en) 2001-01-19 2001-01-19 Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs)

Publications (1)

Publication Number Publication Date
SG99963A1 true SG99963A1 (en) 2003-11-27

Family

ID=25072474

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200200221A SG99963A1 (en) 2001-01-19 2002-01-10 A method to form very high mobility vertical channel transistor by selective deposition of sige or multi-quantum wells (mqws)

Country Status (3)

Country Link
US (1) US6455377B1 (fr)
EP (1) EP1225624A3 (fr)
SG (1) SG99963A1 (fr)

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JP2002237590A (ja) * 2001-02-09 2002-08-23 Univ Tohoku Ｍｏｓ型電界効果トランジスタ
US7176109B2 (en) 2001-03-23 2007-02-13 Micron Technology, Inc. Method for forming raised structures by controlled selective epitaxial growth of facet using spacer
EP1428262A2 (fr) 2001-09-21 2004-06-16 Amberwave Systems Corporation Structures semi-conductrices utilisant des couches de materiaux sollicites a gradients d'impurete definis et procedes de fabrication correspondants
AU2002341803A1 (en) * 2001-09-24 2003-04-07 Amberwave Systems Corporation Rf circuits including transistors having strained material layers
JP2003324197A (ja) * 2002-04-30 2003-11-14 Rohm Co Ltd 半導体装置およびその製造方法
US6900521B2 (en) * 2002-06-10 2005-05-31 Micron Technology, Inc. Vertical transistors and output prediction logic circuits containing same
DE10230715B4 (de) * 2002-07-08 2006-12-21 Infineon Technologies Ag Verfahren zur Herstellung eines Vertikaltransistors
DE102004041035B4 (de) * 2004-04-14 2010-04-29 Steinhauser, Jürgen Verfahren zum Befestigen von Bauteilen auf einem Substrat
US7354814B2 (en) * 2004-09-23 2008-04-08 Freescale Semiconductor, Inc. Semiconductor process with first transistor types oriented in a first plane and second transistor types oriented in a second plane
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8629478B2 (en) * 2009-07-31 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure for high mobility multiple-gate transistor
US9230810B2 (en) 2009-09-03 2016-01-05 Vishay-Siliconix System and method for substrate wafer back side and edge cross section seals
US9818647B2 (en) * 2015-06-03 2017-11-14 International Business Machines Corporation Germanium dual-fin field effect transistor

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4740826A (en) 1985-09-25 1988-04-26 Texas Instruments Incorporated Vertical inverter
US4857971A (en) * 1987-03-23 1989-08-15 Xerox Corporation (IV)x (III-V)1-x alloys formed in situ in III-V heterostructures
US4884119A (en) * 1988-04-22 1989-11-28 American Telephone & Telegraph Company Integrated multiple quantum well photonic and electronic devices
US5179037A (en) * 1991-12-24 1993-01-12 Texas Instruments Incorporated Integration of lateral and vertical quantum well transistors in the same epitaxial stack
US5773328A (en) 1995-02-28 1998-06-30 Sgs-Thomson Microelectronics, Inc. Method of making a fully-dielectric-isolated fet
US6326650B1 (en) * 1995-08-03 2001-12-04 Jeremy Allam Method of forming a semiconductor structure
US5757038A (en) 1995-11-06 1998-05-26 International Business Machines Corporation Self-aligned dual gate MOSFET with an ultranarrow channel
US5689127A (en) 1996-03-05 1997-11-18 International Business Machines Corporation Vertical double-gate field effect transistor
DE19711482C2 (de) * 1997-03-19 1999-01-07 Siemens Ag Verfahren zur Herstellung eines vertikalen MOS-Transistors
US6027975A (en) * 1998-08-28 2000-02-22 Lucent Technologies Inc. Process for fabricating vertical transistors
US6197641B1 (en) * 1998-08-28 2001-03-06 Lucent Technologies Inc. Process for fabricating vertical transistors
DE19846063A1 (de) * 1998-10-07 2000-04-20 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung eines Double-Gate MOSFETs

Also Published As

Publication number Publication date
US20020098655A1 (en) 2002-07-25
EP1225624A2 (fr) 2002-07-24
US6455377B1 (en) 2002-09-24
EP1225624A3 (fr) 2004-11-10

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