SG99298A1 - Phase detector architecture for phase error estimating and zero phase restarting - Google Patents

Phase detector architecture for phase error estimating and zero phase restarting

Info

Publication number
SG99298A1
SG99298A1 SG200000914A SG200000914A SG99298A1 SG 99298 A1 SG99298 A1 SG 99298A1 SG 200000914 A SG200000914 A SG 200000914A SG 200000914 A SG200000914 A SG 200000914A SG 99298 A1 SG99298 A1 SG 99298A1
Authority
SG
Singapore
Prior art keywords
phase
restarting
zero
error estimating
detector architecture
Prior art date
Application number
SG200000914A
Other languages
English (en)
Inventor
B Staszewski Robert
Spagna Fulvio
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of SG99298A1 publication Critical patent/SG99298A1/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10009Improvement or modification of read or write signals
    • G11B20/10046Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
    • G11B20/10055Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom
    • G11B20/10074EPR4, i.e. extended partial response class 4, polynomial (1-D) *(1+D)2
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10009Improvement or modification of read or write signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Algebra (AREA)
  • Pure & Applied Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
SG200000914A 1999-02-25 2000-02-21 Phase detector architecture for phase error estimating and zero phase restarting SG99298A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/258,827 US6587529B1 (en) 1999-02-25 1999-02-25 Phase detector architecture for phase error estimating and zero phase restarting

Publications (1)

Publication Number Publication Date
SG99298A1 true SG99298A1 (en) 2003-10-27

Family

ID=22982302

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200000914A SG99298A1 (en) 1999-02-25 2000-02-21 Phase detector architecture for phase error estimating and zero phase restarting

Country Status (5)

Country Link
US (1) US6587529B1 (ja)
JP (1) JP2000251417A (ja)
KR (1) KR100619192B1 (ja)
SG (1) SG99298A1 (ja)
TW (1) TW548637B (ja)

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Also Published As

Publication number Publication date
US6587529B1 (en) 2003-07-01
KR20000076737A (ko) 2000-12-26
JP2000251417A (ja) 2000-09-14
TW548637B (en) 2003-08-21
KR100619192B1 (ko) 2006-09-08

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