SG66313A1 - Method and apparatus for reducing warpage in semiconductor - Google Patents

Method and apparatus for reducing warpage in semiconductor

Info

Publication number
SG66313A1
SG66313A1 SG1996010110A SG1996010110A SG66313A1 SG 66313 A1 SG66313 A1 SG 66313A1 SG 1996010110 A SG1996010110 A SG 1996010110A SG 1996010110 A SG1996010110 A SG 1996010110A SG 66313 A1 SG66313 A1 SG 66313A1
Authority
SG
Singapore
Prior art keywords
semiconductor
reducing warpage
warpage
reducing
Prior art date
Application number
SG1996010110A
Other languages
English (en)
Inventor
Tan Kok Ping
Wong Siew Kong
Original Assignee
Advanced Systems Automation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Systems Automation filed Critical Advanced Systems Automation
Priority to SG1996010110A priority Critical patent/SG66313A1/en
Priority to PCT/SG1997/000026 priority patent/WO1997049127A1/fr
Priority to EP97929665A priority patent/EP0907962A4/fr
Priority to TW086108575A priority patent/TW420851B/zh
Priority to US08/878,652 priority patent/US6013541A/en
Publication of SG66313A1 publication Critical patent/SG66313A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
SG1996010110A 1996-06-20 1996-06-20 Method and apparatus for reducing warpage in semiconductor SG66313A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
SG1996010110A SG66313A1 (en) 1996-06-20 1996-06-20 Method and apparatus for reducing warpage in semiconductor
PCT/SG1997/000026 WO1997049127A1 (fr) 1996-06-20 1997-06-18 Procede et dispositif pour diminuer le gauchissement dans les boitiers de semi-conducteur
EP97929665A EP0907962A4 (fr) 1996-06-20 1997-06-18 Procede et dispositif pour diminuer le gauchissement dans les boitiers de semi-conducteur
TW086108575A TW420851B (en) 1996-06-20 1997-06-19 Method and apparatus for reducing warpage in semiconductor packages
US08/878,652 US6013541A (en) 1996-06-20 1997-06-19 Method and apparatus for reducing warpage in semiconductor packages

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG1996010110A SG66313A1 (en) 1996-06-20 1996-06-20 Method and apparatus for reducing warpage in semiconductor

Publications (1)

Publication Number Publication Date
SG66313A1 true SG66313A1 (en) 2001-01-16

Family

ID=20429421

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996010110A SG66313A1 (en) 1996-06-20 1996-06-20 Method and apparatus for reducing warpage in semiconductor

Country Status (5)

Country Link
US (1) US6013541A (fr)
EP (1) EP0907962A4 (fr)
SG (1) SG66313A1 (fr)
TW (1) TW420851B (fr)
WO (1) WO1997049127A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429385B1 (en) * 2000-08-08 2002-08-06 Micron Technology, Inc. Non-continuous conductive layer for laminated substrates
US6988879B2 (en) * 2002-10-18 2006-01-24 Asm Technology Singapore Pte Ltd Apparatus and method for reducing substrate warpage
US7172927B2 (en) * 2003-12-18 2007-02-06 Freescale Semiconductor, Inc. Warpage control of array packaging
US7214548B2 (en) * 2004-08-30 2007-05-08 International Business Machines Corporation Apparatus and method for flattening a warped substrate
US7803662B2 (en) * 2007-09-24 2010-09-28 Freescale Semiconductor, Inc. Warpage control using a package carrier assembly
CA2713422A1 (fr) * 2010-09-09 2010-11-16 Ibm Canada Limited - Ibm Canada Limitee Caracterisation de la forme d'un stratifie
US8444043B1 (en) 2012-01-31 2013-05-21 International Business Machines Corporation Uniform solder reflow fixture
WO2016048383A1 (fr) * 2014-09-27 2016-03-31 Intel Corporation Commande de gauchissement d'un substrat à l'aide de verre trempé avec chauffage unidirectionnel
CN105870043A (zh) * 2016-06-16 2016-08-17 苏州工业职业技术学院 一种用于防止引线框架翘曲的装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6457630A (en) * 1987-08-28 1989-03-03 Oki Electric Ind Co Ltd Method and device for preventing warpage of semiconductor device
JPH05226397A (ja) * 1992-02-14 1993-09-03 Toshiba Corp 半導体用熱硬化型自動モールド装置
KR970005713B1 (en) * 1992-07-31 1997-04-19 Nec Kk Process for correcting warped surface of plastic encapsulated semiconductor device
JP3139853B2 (ja) * 1992-09-05 2001-03-05 アピックヤマダ株式会社 樹脂モールドパッケージの徐冷装置
US5641997A (en) * 1993-09-14 1997-06-24 Kabushiki Kaisha Toshiba Plastic-encapsulated semiconductor device
US6388338B1 (en) * 1995-04-28 2002-05-14 Stmicroelectronics Plastic package for an integrated electronic semiconductor device
JPH08213418A (ja) * 1995-02-02 1996-08-20 Hitachi Ltd 半導体装置の製造方法およびその製造方法に用いるモールド金型
JP3099707B2 (ja) * 1995-11-30 2000-10-16 日本電気株式会社 半導体装置の樹脂封止装置
US5825623A (en) * 1995-12-08 1998-10-20 Vlsi Technology, Inc. Packaging assemblies for encapsulated integrated circuit devices

Also Published As

Publication number Publication date
EP0907962A1 (fr) 1999-04-14
TW420851B (en) 2001-02-01
WO1997049127A1 (fr) 1997-12-24
EP0907962A4 (fr) 2000-02-02
US6013541A (en) 2000-01-11

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