SG64973A1 - Programmable read/write access signal and method therefor - Google Patents

Programmable read/write access signal and method therefor

Info

Publication number
SG64973A1
SG64973A1 SG1997000848A SG1997000848A SG64973A1 SG 64973 A1 SG64973 A1 SG 64973A1 SG 1997000848 A SG1997000848 A SG 1997000848A SG 1997000848 A SG1997000848 A SG 1997000848A SG 64973 A1 SG64973 A1 SG 64973A1
Authority
SG
Singapore
Prior art keywords
programmable read
method therefor
write access
access signal
write
Prior art date
Application number
SG1997000848A
Other languages
English (en)
Inventor
Joseph C Circello
James G Gay
Clinton T Glover
Kevin M Traynor
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of SG64973A1 publication Critical patent/SG64973A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
SG1997000848A 1996-04-01 1997-03-19 Programmable read/write access signal and method therefor SG64973A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/627,669 US5872940A (en) 1996-04-01 1996-04-01 Programmable read/write access signal and method therefor

Publications (1)

Publication Number Publication Date
SG64973A1 true SG64973A1 (en) 1999-05-25

Family

ID=24515604

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1997000848A SG64973A1 (en) 1996-04-01 1997-03-19 Programmable read/write access signal and method therefor

Country Status (9)

Country Link
US (1) US5872940A (fr)
EP (1) EP0800139A3 (fr)
JP (1) JPH1055331A (fr)
KR (1) KR970071302A (fr)
CN (1) CN1171577A (fr)
IE (1) IE970147A1 (fr)
IL (1) IL120309A0 (fr)
SG (1) SG64973A1 (fr)
TW (1) TW337564B (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3304895B2 (ja) * 1998-10-08 2002-07-22 日本電気株式会社 補助記録装置の接続方法およびその装置
US6442636B1 (en) * 1999-07-09 2002-08-27 Princeton Technology Corporation Parallel bus system capable of expanding peripheral devices
US6725307B1 (en) * 1999-09-23 2004-04-20 International Business Machines Corporation Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system
US7529799B2 (en) * 1999-11-08 2009-05-05 International Business Machines Corporation Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system
JP3663106B2 (ja) * 2000-02-28 2005-06-22 東芝機械株式会社 データ入出力装置
JP2003015790A (ja) * 2001-06-28 2003-01-17 Oki Electric Ind Co Ltd 半導体集積回路
US7162554B1 (en) * 2001-07-11 2007-01-09 Advanced Micro Devices, Inc. Method and apparatus for configuring a peripheral bus
EP1286270A1 (fr) * 2001-07-24 2003-02-26 Deutsche Thomson-Brandt Gmbh Circuit integré avec interface de communication générique
US6876563B1 (en) * 2002-12-20 2005-04-05 Cypress Semiconductor Corporation Method for configuring chip selects in memories
US7610061B2 (en) * 2003-09-20 2009-10-27 Samsung Electronics Co., Ltd. Communication device and method having a common platform
CN1307571C (zh) * 2004-11-26 2007-03-28 上海广电（集团）有限公司中央研究院 一种低速总线结构及其数据传输方法
US7702839B2 (en) * 2005-04-12 2010-04-20 Nokia Corporation Memory interface for volatile and non-volatile memory devices
CN110781118B (zh) * 2019-09-30 2023-11-03 深圳震有科技股份有限公司 实现并行总线从模式的方法及装置、计算机设备、介质

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5325513A (en) * 1987-02-23 1994-06-28 Kabushiki Kaisha Toshiba Apparatus for selectively accessing different memory types by storing memory correlation information in preprocessing mode and using the information in processing mode
US4933845A (en) * 1987-09-04 1990-06-12 Digital Equipment Corporation Reconfigurable bus
US5265243A (en) * 1989-03-27 1993-11-23 Motorola, Inc. Processor interface controller for interfacing peripheral devices to a processor
US5448744A (en) * 1989-11-06 1995-09-05 Motorola, Inc. Integrated circuit microprocessor with programmable chip select logic
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
KR0181471B1 (ko) * 1990-07-27 1999-05-15 윌리암 피.브레이든 컴퓨터 데이타 경로배정 시스템
JPH04163655A (ja) * 1990-10-26 1992-06-09 Mitsubishi Electric Corp 入出力装置
US5557757A (en) * 1994-02-02 1996-09-17 Advanced Micro Devices High performance integrated processor architecture including a sub-bus control unit for generating signals to control a secondary, non-multiplexed external bus
US5721860A (en) * 1994-05-24 1998-02-24 Intel Corporation Memory controller for independently supporting synchronous and asynchronous DRAM memories
US5535349A (en) * 1994-06-09 1996-07-09 Motorola, Inc. Data processing system and method for providing chip selects to peripheral devices
EP0691616A1 (fr) * 1994-07-08 1996-01-10 Advanced Micro Devices, Inc. Unité de commande de mémoire morte et de mémoire vive

Also Published As

Publication number Publication date
IL120309A0 (en) 1997-06-10
IE970147A1 (en) 1997-10-08
EP0800139A2 (fr) 1997-10-08
JPH1055331A (ja) 1998-02-24
US5872940A (en) 1999-02-16
CN1171577A (zh) 1998-01-28
KR970071302A (ko) 1997-11-07
EP0800139A3 (fr) 1999-03-10
TW337564B (en) 1998-08-01

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