SG174846A1 - Multiple-input comparator and power converter - Google Patents
Multiple-input comparator and power converter Download PDFInfo
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- SG174846A1 SG174846A1 SG2010047041A SG2010047041A SG174846A1 SG 174846 A1 SG174846 A1 SG 174846A1 SG 2010047041 A SG2010047041 A SG 2010047041A SG 2010047041 A SG2010047041 A SG 2010047041A SG 174846 A1 SG174846 A1 SG 174846A1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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- Nonlinear Science (AREA)
- Amplifiers (AREA)
- Manipulation Of Pulses (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
Techniques pertaining to multiple-input comparator and power converter designsare disclosed. According to one aspect, the present invention discloses a multiple-input comparator comprising a pair of differential transistors connected by a resister.The gate terminals of the transistor pair serve as the input terminals of the comparatorfor receiving external voltage for comparison. The terminal of the resistor serves as thecurrent input terminal and is either connected to a current source or a current sink. Apower inverter utilizing the multiple-input comparator is also disclosed. The powerinverter comprises a power switch driven by a PMW signal, a voltage sampling circuit,an error amplifier and a multiple-input PWM comparator.
Description
Muitiple-input comparator and power converter
1. Field of the Invention
The present invention relates to a field of circuit design, more particularly to multiple-input comparator and power converter circuits. 2. Description of Related Art
In the prior art, a pulse width modulation system usually employs a pulse width modulation (PWM) comparator. FIG. 1 is a schematic diagram showing a comparison principle of the PWM comparator. EAO is an error amplifying (output) signal outputted from an error amplifier. Ramp is a saw-tooth or triangular wave signal. The PWM comparator is provided for comparing an error amplifying signal EAO with the triangular wave signal Ramp to produce a pulse width modulation (output) signal
PWMO. When the error amplifying signal EAO is larger than the triangular wave signal
Ramp, the PWM signal PWMO is set at high level. When the error amplifying signal
EAQ is smaller than the triangular wave signal Ramp, the PWM signal PWMO is set at low level. In other words, the signal level of the PWM comparator turns over when the error amplifying signal EAQ is equal fo the triangular wave signal Ramp.
The principle of pulse width modulation is that the PWM system produces the
PWM signal PWMO with different duty cycles along with the error amplifying signal
EAO. It can be seen from FiG1 that the duly cycle of the PWM signal PWMO increases when the error amplifying signal EAO increases, and the duty cycle of the
PWM signal PWMO decreases when the error amplifying signal EAO decreases. For various types of power converters, such as DC-DC converters, DC-AC converters or
AC-AC converters, a feedback loop circuit is usually employed for adjusting the duty cycie of a power switch. If the triangular wave signal Ramp has a fixed frequency, the modulation of pulse width is equivalent io the modulation of the duty cycle.
The triangular wave signal Ramp usually is generated by an oscillator. A conventional oscillator outputs a saw-tooth wave signal as shown in FIG 1. A valley voltage of the saw-tooth wave signal is 0 volt. Using a buck DC-DC converter as an example, a duty cycle is required to equal fo VO/VIN when a loop circuit is stable, where VO is the output voltage and VIN is the input voltage of the DC-DC converter.
When the input voltage VIN is much larger than the output voliage VO | the required duty cycle for stable loop circuit is very small. If the valley voltage of the saw-tooth wave signal Ramp is equal to 0 volt, the error amplifying signal EAQO needs to be near 0 volt when the required duty cycie is very small. Thereby, an output element of the error amplifier may be in the saturation region and the gain of the error amplifier decreased significantly. As a result, the error amplifier does not function normally.
Hence, the saw-tooth wave signal Ramp is required to be enhanced by a certain voltage AV. FIG 2 shows two saw-iooth wave signals before and after voltage enhancement. Ramp1 is the saw-tooth wave signal before voltage enhancement,
Ramp? is the saw-tooth wave signal after voltage enhancement, and AV is an enhancement voltage.
FIG. 3 is a circuit diagram showing a conventional circuit for enhancing a saw-footh wave signal Ramp. Referring to FIG. 3, the circuit comprises an operational amplifier OP1, an oscillator, resistors R1 and R2, PMOS transistors MP1, MP2 and
MP3, and NMOS fransistors MN1, MN2 and MN3. The oscillator produces the unenhanced saw-tooth wave signal Ramp1. An intermediate node 310 between the resistor R2 and the PMOS transistor MP3 is provided as an output terminal for the voltage-enhanced saw-tooth wave signal Ramp2. The saw-tooth wave signal Ramp2 is enhanced by a voltage of V1-(R2/R1) relative {o the saw-tooth wave signal Ramp.
However, the circuit is very complicated and is restricted by the responsive speed of the operational amplifier OP1.
For a conventional current mode power converter, the PWM signal is generated either by adding a sampled inductance current to the saw-tooth wave signal Ramp, and comparing the sum with the error amplifying signal EAO from an error amplifier, or by converting the error amplifying signal into a corresponding current signal, and subtracting the sampled inductance current from the corresponding current signal, then converting the difference back info a voltage signal, and comparing the saw-tocth wave signal after voltage enhancement Ramp with the voltage signal.
FIG. 4 is a schematic circuit diagram showing a conventional circuit for generating the PWM signal by subtracting a sampled inductance current ISEN from an
EAO of an error amplifier and comparing the difference with the voitage-enhanced saw-tooth wave signal Ramp.. Referring to FIG. 4, the circuit comprises an operational amplifier OP2, an oscillator, an enhancement circuit, resistors R3 and R4, PMOS transistors MP11 and MP12, NMOS fransistor MN11, a current sampling current source, and a PWM comparator. The resistance of resistors R3 and R4 may be equal. - In the circuit shown in FIG 4, RampSH is the enhanced saw-tooth wave signal Ramp.
EAQ_ISEN is an output voltage showing the difference between the current sampling signal ISEN and the error amplifying signal EAQ. The PWM comparator is provided for comparing the output voltage EAO_ISEN with the enhanced saw-tooth wave signal
RampSH to produce the PWM signal PWMO. The circuit is very complicated and is restricted by the responsive speed of the operational amplifier OP2.
Thus, improved techniques for a PWM comparator are desired fo overcome the above disadvantages.
According to one aspect, the present invention is a multiple-input comparator comprising a pair of differential transistors connected by a resister. The gate terminals of the transistor pair serve as the input terminals of the comparator for receiving external voltage for comparison. The terminal of the resistor serves as the current input terminal and is either connected io a current source or a current sink. .
According to ancther aspect, the present invention is a power converter utilizing the multiple-input comparator. The power inverter comprises a power switch driven by a PMW signal, a voltage sampling circuit, an error amplifier and a multiple-input PWM comparator.
The present invention may be implemented in many forms. According to one embodiment, the present invention is a multiple-input comparator comprising: a first differential transistor having a gate used as a first voltage input terminal of the multiple-input comparator to receive a first voltage; a second differential transistor, forming a differential transistor pair with the first differential transistor, having a gate used as a second voltage input terminal of the multiple-input comparator to receive a second voltage; and a resistor having a first terminal connected to a source terminal of the first differential transistor and a second terminal connected to a source terminal of the second differential transistor; wherein a node between the first terminal of the resistor and the source terminal of the first differential transistor is used as a current input terminal to connect to a current source, or a node between a second terminal of the resistor and the source terminal of the second differential transistor is used as the current input terminal to connect to a current sink
According to another embodiment, the present invention is a muliiple-input comparator, comprising: a first differential transistor having a gale used as a first voltage input terminal to receive a first voltage; a second differential transistor, forming a differential transistor pair with the first differential transistor, having a gate used as a second voltage input terminal to receive a second voltage; a first resistor having a first terminal connected to a source terminal of the first differential transistor, and a second resistor having a first terminal connected to a source terminal of the second differential transistor and a second terminal connected to a second terminal of the first resistor; wherein a node between the first terminal of the first resistor and the source terminal of the first differential transistor is used as a current input terminal to connect to a current source; or a node between the first terminal of the second resistor and the source terminal of the second differential transistor is used as a current input terminal fo connect to a current sink, .
According to yet another embodiment, the present invention is a power converter, comprising: a power conversion stage comprising a power switch driven by a PMW signal to convert an input voltage to an output; a voltage sampling circuit configured for sampling the output voliage to produce a feedback voltage; an error amplifier configured for amplifying an error between the feedback voltage and a reference voltage fo produce an error amplifying signal, a muitiple-input PWM comparator having a current input terminal connected to a current source or a current sink, a first voltage input terminal coupied with the error amplifying signal and connected to a second voltage input terminal coupled with a saw-tooth wave signal, for comparing the error amplifying signal with the saw-tooth wave signal to produce a
PWM signal.
Comparing to the prior arts, with the implementation of a current input the present invention not only is capabie of performing complicated comparison functions, but also has much simpler circuit structure. Other objects, features, and advantages of the present invention will become apparent upon examining the following detailed description of an embodiment thereof, taken in conjunction with the attached drawings.
FIG. 1 is a schematic diagram showing a comparison principle of a PWM comparator;
FIG. 2 shows two-tooth wave signals before and after voltage enhancement;
FIG. 3 is a circuit diagram showing a conventional circuit for enhancing a saw-tooth wave signal Ramp;
FIG 4 is a schematic circuit diagram showing a conventional circuit to generate a
PWM signal by subtracting a sampled inductance current ISEN from an output signal
EAQ of an error amplifier and comparing the difference with a voltage-enhanced saw-tooth wave signal Ramp;
FIG. 5A is a schematic circuit diagram showing a first exemplary configuration of a multiple-input comparator according to a first embodiment of the present invention,
FIG. 5B is a schematic circuit diagram showing a second exemplary configuration of the multiple-input comparator according to the first embodiment of the present invention;
FIG. 5C is a schematic circuit diagram showing a third exemplary configuration of the multiple-input comparator according to the first embodiment of the present invention;
FIG. BD is a schematic circuit schematic diagram showing a fourth exemplary configuration of the multiple-input comparator according to the first embodiment of the present invention;
FIG. 5E is a schematic circuit diagram showing a fifth exemplary configuration of the &
multiple-input comparator according to the first embodiment of the present invention;
FIG. 5F is a schematic circuit diagram showing a sixth exemplary configuration of the multiple-inpuf comparator according to the first embodiment of the present invention;
FIG. 6A is a schematic circuit diagram showing a first exemplary configuration of the multiple-input comparator according to a second embodiment of the present invention;
FIG. 6B is a schematic circuit diagram showing a second exemplary configuration of the multiple-input comparator according to the second embodiment of the present invention,
FIG. 7 is a schematic circuit diagram showing an exemplary configuration of the muitiple-input comparator according to a third embodiment of the present invention;
FIG. 8A is a schematic circuit diagram showing a first exemplary configuration of a power converter according to one embodiment of the present invention;
FIG. 8B is a schematic circuit diagram showing a second exemplary configuration of the power converter according to one embodiment of the present invention,
FIG. 8C is a schematic circuit diagram showing a third exemplary configuration of the power converter according to one embodiment of the present invention; and
FIG. 8D is a schematic circuit diagram showing a fourth exemplary configuration of the power converter according to one embodiment of the present invention.
FIG. 5A is a schematic circuit diagram showing a first exemplary configuration of a multiple-input comparator 500 according to a first embodiment of the present invention. Referring to FIG 5A, the multiple-input comparator 500 comprises a differential transistor pair (MP51 and MP52), a first resistor R51, a second resistor
R52 and a current source (51. The length-to-width ratio of the first differential transistor
MP51 is equal to that of the second differential transistor MP32.
The first differential transistor MP51 is a PMOS transistor. The gate of the first differential transistor MP51 is used as the first voltage input terminal of the multiple-input comparator 500 to receive the error amplifying voltage EAO. The second differential transistor MP52 is aiso a PMOS transistor. The gate of the second differential transistor MP52 is used as the second voltage input terminal of the multiple-input comparator 500 fo receive the voltage Ramp. One terminal of the first resistor R51 is connected to the source of the first differential transistor MP51, and one terminal of the second resistor R52 is connected fo the source of the second differential transistor MP52. The other terminals of the first resistor R51 and the second resistor R52 are connected to the current source 151 at node Vem.
A node between the first resistor R51 and the first differential transistor MP51 is used as a current input terminal INJ of the multiple-input comparator 500. The current input terminal INJ is connected to a current source. It should be noted that a node connected to a current source means that the current source will inject a current into the node, and that a node connected to a current sink means that the current sink will extract a current from the node.
The multiple-input comparator 500 further comprises NMOS fransistors MN51,
MN52 and MNS53, a current source 152 and an inverter INV51. The NMOS transistor
MN51 has its drain connected to the drain of the first differential transistor MP51, its source grounded, and its gate connected to its drain. The NMOS transistor MN52 has its drain connected with the drain of the second differential transistor MP52, its source grounded, and its gate connected to the gate of the NMOS transistor MNS. The
NMOS transistors MN51 and MN52 form a current mirror of 1:1. The NMOS transistor
MNS53 has its drain connected to the current source 152, its source grounded, and its gate connected to the drain of the NMOS transistor MN52. The inverter INV51 has its input terminal connected to the drain of the NMOS transistor MNS3 and the current source 152, and its output terminal serves as PWMO voltage output terminal.
The multiple-input comparator turns over when the current passing through the second differential transistor MP52 is equal fo the current passing through the NMOS transistor MN52 according to the principle of the comparator. The gate-source voltage
Vgs of the first differential transistor MP51 is equal to the gate-source voltage Vgs of the second differential transistor MP52 because the length-to-width ratio of the first differential transistor MP51 is equal to that of the second differential fransistor MP52, and the NMOS transistors MN51 and MN52 form a current mirror of 1:1. Circuit analysis of FIG. 5A shows the following:
VEAQ=Vem-VR51-VGSupesil,
VRamp=Vem -VR52-|VGSyesz|,
So, VEAC-VRamp=VR52-VR51=R52*(I1+ljy)}-R51*11,
Then, VEAO=VRamp+Vosert, Voriseti= RS2*(11+ Ing)-R51*11 (1) where VEAO is the voltage of the error amplifying signal EAO, VRamp is the voitage of the saw-tooth wave signal, VR51 is the voltage drop on the first resistor R51, VGSyps+ is the gate-source voltage Vgs of the first differential transistor MP51, VGSyes; is the gate-source voltage Vgs of the second differential transistor MP52, Vem is the voltage at node Vem, 11 is the current passing through the first resistor R51, ln is the current injected into the current input terminal INJ, and Vgeerr is the offset voltage.
It can be seen from the formula (1) that the muliiple-input comparator 500 carries out a comparison between VEAO and VRamp+Vime. In a preferred embodiment, the resistance value (R) of the first resistor R51 is set to equal to that of the second resistor R52. Formula (1) is then reduced 10 Vomser=R*hng. That is equivalent to enhance VRamp by R* ly; when lin is a direct current. Furthermore, to add a voltage corresponding to a sampled current ISEN fo VRamp is achieved when
In is the sampled current ISEN. According to another embodiment, the resistance of the first resistor R51 is set to be lower than that of the second resistor R52to enhance
VRamp more easily. The injected current ly may be obtained from any reference current source circuits available in various analog chips. For example, the current source connected to the current input terminal INJ may be a current source generation circuit based on constant-gm type, AVee/R type, Vy/R type. Vae/R type or band-gap reference. Furthermore, the current source based on band-gap reference provides a more stable enhancement voltage, which is proportional to the band-gap voltage.
According to another embodiment, the length-to-width ratio of the first differential transistor MP51 is set to equal to that of the second differential transistor
MP52. The length-to-width ratio of the NMOS transistor MN51 must not be equal to that of the NMOS transistor MN52. As long as the gate-source voltage of the first differential transistor MP51 is equal to that of the second differential transistor MP52, when the multiple-input comparator 500 turns over, the length-to-width ratios of the differential transistor MP51 and MP52 and of the NMOS transistor MN51 and MNS2 can be arbitrarily set.
Comparing with the prior art, the complicated enhancement circuit with imitation on slow responsive speed shown in FIG. 3 and the complicated circuit for subtracting the sampled current ISEN from the error amplifying signal EAO shown in
FIG. 4 are no longer needed in the present invention. With the addition of two resistors and one current input terminal to a conventional comparator, the present invention is able to achieve the same enhancement effects. The disclosed circuit is significantly simplified and the responsive speed is greatly accelerated.
FIG. 5B is a schematic circuit diagram showing a second exemplary configuration of the multipie-input comparator 500 according to the first embodiment of the present invention. Referring to FIGs. 5B and 5A, the mulfiple-input comparator shown in FIG. 5B is substantially similar to that shown in FIG. 5A, except that a node between the second resistor R52 and the second differential transistor MP52 is used as the current input terminal INJ fo connect to a current sink in the multiple-input comparator shown in FIG. 5B. The current sink extracts a current from the current input terminal INJ. Similar to formula (1), VEAC=VRamp+Veerr and Vemsen™ RS2*(11+
Ing)-R51*11 are derived from the multiple-input comparator shown in FIG. 5B, where ling Is modified to indicate the extraction of the sink current.
FIG. 5C is a schematic circuit diagram showing a third exemplary configuration of the muitiple-input comparator 500 according to the first embodiment of the present invention. Referring to FIGs. 5C and 5A, the multiple-input comparator shown in FIG. 5C is substantially similar to that shown in FIG. 5A, except that the first resistor R51 is not used in the multiple-input comparator shown in FIG. 5C, and that the source of the first differential transistor MP51 is used as the current input terminal INJ. Similar to formula (1), VEAC=VRamp+Vfserr and Vigeerr= RE2*(11+ Ipy)-R51*11 are derived for the muitiple-input comparator shown in FIG. 5C. When the resistance of the first resistor R51 is set to 0, formula (1) is modified to be VEAO=VRamp+Vseert and
Voiset:= R52*(11+hny), where [1 is modified io indicate a current flowing into the first differential from the current source 151.
FIG. 5D is a schematic circuit diagram showing a fourth exemplary configuration of the multiple-input comparator 500 according to the first embodiment of the present invention. Referring to FIGs. 5D and 5C, the muliiple-input comparator shown in FIG. 50D is substantially similar to that shown in FIG. 5C, except that a node between the second resistor R52 and the second differential transistor MP52 is used as the current input terminal INJ to connect to a current sink. The current sink extracts a current from the current input terminal INJ. VEAO=VRamp+Vgsert and Vossent™ RB2*(11+1py) are derived for the multiple-input comparator shown in FIG. 5D, where ky is modified to indicate the extraction of sink current.
The differential transistors MP51 and MP52 shown in FIGs. 5A-5D are not limited to PMOS transistors, any other types of transistors such as NMOS transistors may aiso be used.
FIG. 5& is a schematic circuit diagram showing a fifth exemplary configuration of the multiple-input comparator 500 according to the first embodiment of the present invention. Referring to FIGs. 5E, 5A and 5B, the main differences between the multiple-input comparator shown in FIG. 5 and those shown in FIGs. 5A and 5B are: (1) the differential transistor pair shown in FiGs. 5A and 5B is formed by transistors
MP51 and MP52, while in FIGs. 5E is formed by transistors MN51 ang MNS2, ana (2) the PMOS transistors are replaced with the NMOS transistors. Referring to FIG. 5E, the current input terminal connects to a current source when node INJ1 between the first resistor R51 and the first differential transistor MN51 is used as the current input terminal. Analysis of the circuit shows the following:
VEAC=Vem+VR51+|VGSynsi,
VRamp=Vem +VR5Z+IVESynsa|,
So, VEAO-VRamp=VR51-VR52=R51*( 12+l)y,)-R52%12,
Then, VEAC=VRamp+Vyfiset2, Vofisetz= RST 12+1iny)-RE2*12 (2) where 12 is the current passing through the first resistor R51, VGSynst is the gate-source voltage Vgs of the first differential transistor MN51, VGSuns: is the gate-source voltage Vgs of the second differential transistor MN52, li; is the current injected into the current input terminal INJ, and Vesserz is an offset voltage. it can be seen from the formuia (2) that the muitiple-input comparator shown in FIG 5E is capable of achieving the same enhancement effects of the Ramp signal as the multipie-input comparator shown in FIG. 5A., where the offset voltage is modified as the difference of subtracting a voltage drop on the second resistor from a voltage drop on the first resistor. Referring to FIG. 5k, when node INJ2 between the second resistor
R52 and the second differential transistor MN52 is used as the current input terminal, and connects to a current sink, VEAO=VRamp+Vogser, Vomer= RET12+ )-R52%12 are derived, where |v is modified to indicate the extraction of sink current.
FIG. 5F is a schematic circuit diagram showing a sixth exemplary configuration of the multiple-input comparator 500 according to the first embodiment of the present invention, wherein the differential transistors are impiemented by NMOS transistors.
Referring to FIGs. 5F and 5E, the muliiple-input comparator shown in FIG. 5F is substantially similar to that shown in FIG. 55 except that the first resistor R51 is not employed on the multiple-input comparator shown in FIG 5F. When node INJ1 between the first resistor R51 and the first differential transistor MN51 is used as the current input terminal, and connects to a current source VEAO=VRamp+V perp and
Vofrsetz= RE1*(12+1y)-R52%12 are derived, wherein the resistance of the second resistor
R52 is set as 0. Thus, formula (2) is modified to VEAO=VRamp+Voseerz and Vofiser™
R51*(12+1ny), wherein 12 is the current flowing into the current source 151 from the second differential transistor MN52. When a source INJZ of the second differential transistor MIN52 is used as the current input terminal, the current input terminal connects to a current sink. At this time, VEAO=VRamp+Vigeerr and Vogser=
R51*(12+lny) are derived, wherein ly, is the current extracted from the current input terminal INJ2.
FIG. 6A is a schematic circuit diagram showing a first exemplary configuration of a muitiple-input comparator 800 according to a second embodiment of the present invention. Referring to FIGs. 6A, 5A and 5B, comparing the multiple-input comparator 500 shown in FIG. 5A and FIG. 5B, the multiple-input comparator 600 further comprises a first differential transistor MP81, a second differential transistor MP62 to form a differential transistor pair, a first resistor R61, a second resistor R62 and a current source 181. A connection relationship of the electric elements above mentioned is identical with that shown in FIG. BA and FIG. 5B, which is omitted herein for simplicity. in one embodiment, a node INJ1 between the first resistor R61 and the first differential transistor MP81 is used as the current input terminal to connect to a current source. in another embodiment, a node INJ2 between the second resistor R62 and the second differential transistor MP62 is used as the current input terminal to connect fo a current sink.
The multiple-input comparator 600 further comprises PMOS transistors MP63 and MP64, NMOS transistors MN61, MN62, MNB83 and MN64, and an inverter INVGT.
The PMOS transistor MP63 has its source connected to a power supply VDD, a gate connected to the drain. The NMOS transistor MN64 has its source grounded, a drain connected with the drain of the PMOS transistor MP83. The NMOS transistor MNG1 has its drain connected to a drain of the first differential transistor MP61, its source grounded, and a gate connected to the gate of the NMOS transistor MN64. The NMOS transistor MNG2 has its drain connected fo the drain of the second differential transistor MP62, its source grounded. The NMOS transistor MNB3 has its source grounded, a gate connected with the gate of the NMOS transistor MNG2.. The PMOS transistor MP64 has its source connected to the power supply VDD, its gate connected to the gate of the PMOS transistor MP83, and a drain connected to the drain of the
NMOS transistor MN63. The inverter INV61 has an input terminal connected to the intermediate node between the PMQOS transistor MP84 and the NMOS transistor
MNB3, and an output terminal used as a voltage output terminal PWMO of the multiple-input comparator 600. The NMOS transistors MN61 and MN&4 form a current mirror, the NMOS fransistors MN62 and MN63 form a current mirror, and the PMOS transistor MP83 and MP84 form a current mirror.
When the node INJ1 is used as the current input terminal, formula (1)
VEAOC=VRamp+Vgsett and Vomen™ R52*(I1M1+Iny)-R51*11 are derived for the multiple-input comparator 600 shown in FIG. 6A. But, the formula (1) is updated as a formula (3) VEAO=VRamp+Vfser: and Vogsert= RE2*(11+ hing)-RE61*11, wherein fy is an injected current. When the node INJ2 is used as the current input terminal, the formula (3) VEAO=VRamp+Vosser1 and Vemen= RE2*(11+ [W)-R61*11 is also applicable, wherein ly, is the extracted current.
FIG. 6B is a schematic circuit diagram showing a second exemplary configuration of the multiple-input comparator 600 according to the second embodiment of the present invention. Referring to FIG 6B and FIG 6A, the multiple-input comparator shown in FIG. 6B is substantially similar to that shown in FIG.
BA except that the first resistor R61 is not employed in the multiple-input comparator shown in FIG. 6B and the source of the first differential transistor MP61 is used as node INJ1. When the node INJ1 is used as the current input terminal, the formula (3)
VEAOC=VRamp+Vofserr and Vogsen= RB2*(11+iny)-R61*11 is applicable, where the resistance of the first resistor R61 is set as 0. Thus, formuia (3) is modified to
VEAO=VRamp+Vmer1 and Vossen™ RB2*(11+ ling), where I, is a current injected into the current input terminal. When the node INJ2 is used as the current input terminal, the formulas VEAO=VRamp+Vomer1 and Vomen= RE2*(11+ ly) are also applicable, where lin, is a current extracted from the current input terminal.
FIG. 7 is a schematic circuit diagram showing a multiple-input comparator 700 according to a third embodiment of the present invention. Referring to FIG. 7 and FIG.
BA, comparing to the multipie-input comparator 600, the multiple-input comparator 700 further comprises a first differential transistor MP71, a second differential transistor
MP72 forming a differential transistor pair together with a first differential transistor
MP71, a first resistor R71, a second resistor R72 and a current source 171. A connection relationship of the electric elements above mentioned is identical with that shown in FIG. BA, which is omitted herein for simplicity. In one embodiment, a node
INJ1 between the first resistor R71 and the first differential transistor MP71 is used as the current input terminal to connect to a current source. In another embodiment, a node iNJZ between the second resistor R72 and the second differential transistor
MP72 is used as the current input terminal fo connect to a current sink.
The multiple-input comparator 700 further comprises PMOS transistors MP73 and MP74, NMOS fransistors MN71, MN72, MN73 and MN74, a first inverter INV71 and a second inverter INV72. The PMOS transistor MP73 has a source connected to a power supply VDD, a gate connected to the drain thereof, and a drain. The NMOS transistor MN73 has its drain connected with the drain of the PMOS transistor MP73.
The NMOS transistor MN71 has its drain connected to the source of the NMOS transistor MN73, its source grounded. The PMQOS transistor MP74 has ifs source connected to the power supply VDD, and a gate connected io the gate of the PMOS transistor MP73. The NMOS transistor MN74 has a gate connected to the gate of the
NMOS transistor MN73, and a drain connected to the drain of the PMOS transistor
MP74. The NMOS transistor MN72 has its source grounded, a gate connected to the gate of the NMOS transistor MN71, and a drain connected to the source of the NMOS transistor MN74. The first inverter INV71 has an input terminal connected to an intermediate node between the PMOS transistor MP74 and the NMOS transistor
MN74. The second inverter INV72 has an input terminal connected to the output terminal of the first inverter INV71, and an output terminal used as a PWMO voltage output terminal of the multiple-input comparator 700. The PMOS transistors MP73 and
MP74 form a current mirror, the NMOS transistors MN73 and MN74 form a current mirror, and the NMOS transistors MN71 and MN72 form another current mirror.
The formulas VEAO=VRamp+Vggset1 aNd Vogsen™ R72*(I1+ing}-R71711 are also applicable for the multipie-input comparator 700. According to one embodiment, the resistance of the first resistor R71 is set to 0. it can be seen that the multiple-input comparator achieves a comparison between the gate voltage VEAO of the first differential transistor and a sum of the gate voltage VRamp of the second differential transistor and the offset voltage by connecting the first resistor and/or the second resistor to the source terminals of the first differential transistor and/or the second differential transistor. The above configuration can be applied in the input stages of all types of conventional comparators.
According to another embodiment, the differential transistor pair shown in FIGs. 7, 8A and 6B can be implemented with NMOS transistors.
FIG. 8A is a schematic circuit diagram showing a first exemplary configuration of a power converter 800 according to one embodiment of the present invention.
Referring to FIG. 8A, the power converter 800 comprises a multiple-input comparator 810, a power conversion stage 830, a voltage sampling circuit 840 and an error amplifier 850. The multiple-input comparator 810 can be anyone of the multipie-input comparators shown in FIGs. 5A-7. As described above, the multiple-input comparator 810 comprises a first voltage input terminal, a second voltage input terminal and a current input terminal INJ. The current input terminal INJ is connected to a direct current source IDC. An error amplifying signal EAQ is used as the first voltage to couple with the first voltage input terminal. A saw-tooth wave signal Ramp is used as the second voltage to couple with the second voltage input terminal. The multiple-input comparator 810 is provided for comparing the error amplifying sighal EAO with the saw-tooth wave signal Ramp fo produce a PWM signal. The power conversion stage 830, comprising a power switch (not shown), is provided for converting an input voltage to an output voltage under the control of the power switch, which is driven by the PMW signal. The voltage sampling circuit 840 is provided for sampling the output voltage of the power converter to obtain a feedback voltage Vib. The error amplifier 850 is provided for amplifying an error signal between the feedback voltage Vib and a reference voltage Vref fo produce the error amplifying signal EAC. According to one embodiment, the saw-tooth wave signal Ramp is generated by the oscillator OSC, and the PWM signal drives the power switch via a PWM controller 820. The PWM signal outputted from the multiple-input comparator 810 turns over when the error amplifying signal EAO is equal to the sum of the saw-tooth wave signal Ramp and the offset voltage, which is proportional to the current injected into the current input terminal.
FIG. 8B is a schematic circuit diagram showing a second exemplary configuration of the power converter 800 according fo one embodiment of the present invention. Referring to FIGs. 8B and 8A, the power converter shown in FIG. 8B is substantially similar to that shown in FIG. 8A except that the power converter shown in
FIG. 8B further comprises a current sampling circuit 860 for sampling the current passing through the power switch. The current being sampled by the current sampling circuit 860 is coupled to the current input terminal INJ as a current source.
FIG. 8C is a schematic circuit diagram showing a third exemplary configuration of the power converter 800 according to one embodiment of the present invention.
Referring to FIGs. 8C and 8A, the power converter shown in FIG. 8C is substantially similar to that shown in FIG. 8A except that the direct current source IDC is connected to the current input terminal as a current sink.
FIG. 8D is a schematic circuit diagram showing a fourth exemplary configuration of the power converter 800 according to one embodiment of the present invention.
Referring to FIGs. 8D and 8B, the power converter shown in FIG. 8D is substantially similar to that shown in FIG. 8B except that the direct current source IDC and the current sampled by the current sampling circuit 860 are coupled to the current input terminal INJ as a current sink.
As described above, a current input is employed in the comparator in the nresent invention. Thereby, the comparator not only capable of performing complicated comparison functions, but aiso has simpie structure.
The present invention has been described in sufficient details with a certain degree of particularity. It is understood to those skilled in the art that the present disclosure of embodiments has been made by way of examples only and that numerous changes in the arrangement and combination of parts may be resorted without departing from the spirit and scope of the invention as claimed. Accordingly, the scope of the present invention is defined by the appended claims rather than the foregoing description of embodiments.
Claims (1)
- CLAIMS What is claimed is:1. A multiple-input comparator, comprising: a first differential transistor having a gate used as a first voltage input terminal of the multiple-input comparator to receive a first voltage; a second differential transistor, forming a differential transistor pair with the first differential transistor, having a gate used as a second voltage input terminal of the multiple-input comparator fo receive a second voltage; and a resistor having a first terminal connected to a source terminal of the first differential transistor and a second terminal connected to a source terminal of the second differential transistor; wherein a node between the first terminal of the resistor and the source terminal of the first differential transistor is used as a current input ferminal to connect to a current source, or a node between a second terminal of the resistor and the source terminal of the second differential transistor is used as the current input terminal to connect to a current sink.2. The multiple-input comparator according to claim 1, further comprises a current source connected to the source of the first differential transistor, wherein the first differential transistor and the second differential transistor are PMOS transistors.3. The multiple-input comparator according to claim 1, further comprises a current source connected to the source of the first differential transistor, wherein the first differential transistor and the second differential transistor are NMOS transistors,4. The multiple-input comparator according to claim 1, wherein the multiple-input comparator turns over when the first voltage is equal to a sum of the second voltage and a voltage drop across the resistor.5. The muitiple-input comparator according to claim 4, wherein the current source injects a current into the current input terminal causing a voltage drop across the resistor , and wherein the current sink extracts a current from the current input terminal causing a voltage drop on the resistor.8. A multiple-input comparator, comprising: a first differential transistor having a gate used as a first voltage input terminal to receive a first voltage; a second differential transistor, forming a differential transistor pair with the first differential transistor, having a gate used as a second voltage input terminal to receive a second voltage; a first resistor having a first terminal connected to a source terminal of the first differential transistor; and a second resistor having a first terminal connected to a source terminal of the second differential transistor and a second terminal connected to a second terminal of the first resistor; wherein a node between the first terminal of the first resistor and the source terminal of the first differential transistor is used as a current input terminal to connect to a current source; or a node between the first terminal of the second resistor and the source terminal of the second differential transistor is used as a current input terminal to connect to a current sink.7. The multiple-input comparator according to claim 8, further comprising a current source connected fo an intermediate node between the first resistor and the second resistor.8. The multiple-input comparator according to claim 6, wherein the multiple input comparator turns over when the first voltage is equal to a sum of the second voltage and a voltage drop difference across the first resistor and the second resistor.9. The multiple-input comparator according to claim 8, wherein the current source injects a current into the current input terminal causing a voltage drop difference across the first and the second resistors, and wherein the current sink extracts a current from the current input terminal causing a voltage drop difference across the first and the second resistors .10. The multiple-input comparator according to claim 9, wherein a length-to-width ratio of the first differential transistor is equal fo that of the second differential transistor.11. The mulfiple-input comparator according to claim 8, further comprising a first transistor, a second transistor, a third transistor, a current source and an inverter, the first transistor having a drain terminal connected to a drain of the first differential transistor, a source terminal grounded, and a gate connected with the drain terminal, the second transistor having a drain terminal connected to a drain of the second differential transistor, a source terminal grounded, and a gate connected to the gate of the first transistor; the third transistor having a gate connected fo the current source, a source terminal grounded, and a gate connected to the drain of the second transistor; and the inverter having an input terminal connected fo an intermediate node between the current source and the third transistor, and an output terminal used as a voltage output terminal of the multiple-input comparator.12. The multiple-input comparator according to claim 9, further comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and an inverter, the first transistor having a source connected with a power supply, a gate connected with the drain thereof, and a drain; the second transistor having a source terminal grounded, a drain connected {o the drain of the first transistor; the third transistor having a drain connected to a drain of the first differential transistor, a source terminal grounded, and a gate connected fo the gate of the second transistor; the fourth transistor having a drain connected to a drain of the second differential transistor, a source terminal grounded, the fifth transistor having a source terminal grounded, a gate connected to the gate of the fourth transistor; the sixth transistor having a source terminal connected to the power supply, a gate connected to the gate of the first transistor, and a drain connected to the drain of the fifth transistor, the inverter having an input terminal connected {o an intermediate node between the fifth transistor and the sixth transistor, and an output terminal used as a voltage output terminal of the multiple input comparator; and the second and the third transistors, the fourth and the fifth transistors, and the first and the sixth transistor form three separate current mirrors.13. The muitiple-input comparator according to claim 8, further comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first inverter and a second inverter, the first transistor having a source terminal connected to a power supply, a gate and a drain connected together;the third transistor having a drain connected to the drain of the first transistor, the fifth transistor having a drain connected to the source of the third transistor, a source terminal grounded; the second transistor having a source connected to the power supply, and a gate connected to the gate of the first transistor; the fourth transistor having a gate connected to the gate of the third transistor, and a drain connected to the drain of the second {ransistor; the sixed transistor having a source terminal grounded, a gate connected to the gate of the fifth transistor, and a drain connected to the source terminal of the fourth transistor; the first inverter having an input terminal connected fo an intermediate node between the second transistor and the fourth transistor, and an output terminal; the second inverter having an input terminal connected to the output terminal of the first inverter, and an output terminal used as a voltage output terminal of the multiple-input comparator; and the second and the first transistors, the third and the fourth transistors , and the fifth and the sixth transistor form three separate current mirrors.14. A power converter, comprising: a power conversion stage comprising a power switch driven by a PMW signal to convert an input voltage to an output ; a voltage sampling circuit configured for sampling the output voltage to produce a feedback voltage; an error amplifier configured for amplifying an error between the feedback voltage and a reference voltage to produce an error amplifying signal; a multiple-input PWM comparator having a current input terminal connected to a current source or a current sink, a first voltage input terminal coupled with the error amplifying signal and connected to a second voltage input terminal coupled with a saw-tooth wave signal, for comparing the error amplifying signal with the saw-tooth wave signal to produce a PWM signal.15. The power converter according to claim 14, further comprising: a current sampling circuit configured for sampling a current passing through the power switch, wherein the sampled current is coupled with the current input terminal and serves as a current source or a current sink.16. The power converter according to claim 14, wherein the multiple-input comparator comprises: a first differential transistor having a gate used as the first voltage input terminal fo receive a first voltage; a second differential transistor forming a differential transistor pair with the first differential transistor and having a gate used as the second voltage input terminal to receive a second voltage; and a resistor having a first terminal connected fo a source terminal of the first differential transistor and a second terminal connected to a source terminal of the second differential transistor; wherein a node between the first terminal of the resistor and the first differential transistor is used as the current input terminal to connect to the current source; or a node between the second terminal of the resistor and the second differential transistor is used as the current input terminal to connect with the current sink; and wherein the multiple-input comparator turns over when the first voltage is equal to a sum of the second voltage and a voltage drop across the resistor.17. The power converter according to claim 16, wherein the current source injects a current into the current input terminal causing a voltage drop across the resistor, and wherein the current sink extracts a current from the current input terminal causing a voltage drop across the resistor.18. The power converter according to claim 14, wherein the multiple-input comparator comprises: a first differential transistor having a gate used as the first voltage input terminal to receive a first voltage; a second differential transistor forming a differential transistor pair with the first differential transistor and having a gate used as the second voltage input terminal to receive a second voltage; a first resistor having a first terminal connected to a source terminal of the first differential transistor; and a second resistor having a first terminal connecting to a source terminal of the second differential transistor and a second terminal connected to a second terminal of the first resistor; wherein a node between the first terminal of the first resistor and the source terminal of the first differential transistor is used as the current input terminal to connect to the current source; or a node between the first terminal of the second resistor and the source terminal of the second differential transistor is used as the current input terminal to connect fo the current sink; and wherein the multiple-input comparator turns over when the first voltage is equal to a sum of the second voltage and a voltage drop difference between the first resistor and the second resistor.19. The power converter according to claim 18, wherein the current source injects a current into the current input terminal causing a voltage drop difference between the first resistor and the second resistor , and wherein the current sink extracts a current from the current input terminal causing a voltage drop difference between the first resistor and the second.20. A multiple-input comparator, comprising: a first differential transistor having a gate used as a first voltage input terminal to receive a first voltage; a second differential transistor forming a differential transistor pair with the first differential transistor and having a gate used as a second voltage input terminal to receive a second voltage; and a current input terminal where a current is injected or extracted, wherein the multiple-input comparator turns over when the first voltage is equal to a sum of the second voltage and an offset voltage caused by the current.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101442858A CN101847981B (en) | 2010-04-12 | 2010-04-12 | Multi-input comparator and power switching circuit |
| PCT/CN2010/074166 WO2011127686A1 (en) | 2010-04-12 | 2010-06-21 | Multi-input comparator and power switching circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG174846A1 true SG174846A1 (en) | 2011-11-28 |
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ID=42772465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG2010047041A SG174846A1 (en) | 2010-04-12 | 2010-06-21 | Multiple-input comparator and power converter |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN101847981B (en) |
| SG (1) | SG174846A1 (en) |
| WO (1) | WO2011127686A1 (en) |
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|---|---|---|---|---|
| CN101902215B (en) * | 2010-08-02 | 2012-09-26 | 中颖电子股份有限公司 | Four-input terminal comparator |
| CN102447410B (en) * | 2010-10-11 | 2015-11-25 | 北京中星微电子有限公司 | AC-DC power supply changeover device and loop compensation circuit thereof |
| CN102111133A (en) * | 2011-03-29 | 2011-06-29 | 无锡中星微电子有限公司 | Hysteresis circuit |
| CN102420594B (en) * | 2011-12-15 | 2016-03-16 | 无锡中感微电子股份有限公司 | A kind of comparator |
| CN102970008B (en) * | 2012-11-21 | 2015-02-18 | 东南大学 | Rapid transient response pulse duration modulation circuit |
| CN104092360B (en) * | 2014-06-30 | 2017-05-17 | 成都芯源系统有限公司 | Transconductance adjusting circuit, transconductance error amplifying unit and switching power converter |
| CN104617770A (en) * | 2015-03-09 | 2015-05-13 | 王锴 | Switching power converter system and control method thereof |
| CN105610412B (en) | 2015-12-24 | 2018-08-14 | 深圳创维－Rgb电子有限公司 | A kind of comparator and low-power consumption oscillator |
| KR20210019520A (en) * | 2018-06-12 | 2021-02-22 | 칸도우 랩스 에스에이 | Passive multi-input comparator for orthogonal codes on multi-wire buses |
| JP7063753B2 (en) * | 2018-07-13 | 2022-05-09 | エイブリック株式会社 | Voltage regulator and voltage regulator control method |
| CN111355492B (en) * | 2018-12-21 | 2023-03-24 | 瑞昱半导体股份有限公司 | Comparator and analog-digital conversion circuit |
| CN112994697B (en) * | 2021-04-21 | 2021-07-30 | 微龛(广州)半导体有限公司 | Comparator |
| CN116192144B (en) * | 2023-02-13 | 2024-04-02 | 集益威半导体(上海)有限公司 | Asynchronous successive approximation analog-to-digital converter |
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|---|---|---|---|---|
| US4047059A (en) * | 1976-05-24 | 1977-09-06 | Rca Corporation | Comparator circuit |
| JPS63136712A (en) * | 1986-11-28 | 1988-06-08 | Toshiba Corp | Differential comparator |
| JPH06188716A (en) * | 1992-12-21 | 1994-07-08 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
| JP3270327B2 (en) * | 1996-05-24 | 2002-04-02 | セイコーインスツルメンツ株式会社 | Overcharge / discharge detection circuit |
| US6414553B1 (en) * | 2001-08-30 | 2002-07-02 | Koninklijke Philips Electronics N.V. | Power amplifier having a cascode current-mirror self-bias boosting circuit |
| EP1385174B1 (en) * | 2002-07-26 | 2006-07-05 | Alcatel | A fast sample-and-hold peak detector circuit |
| DE102004022991B3 (en) * | 2004-05-10 | 2005-12-08 | Infineon Technologies Ag | Sample differential amplifier and sample amplifier |
| JP4440869B2 (en) * | 2005-10-25 | 2010-03-24 | 富士通マイクロエレクトロニクス株式会社 | DC-DC converter, control circuit for DC-DC converter, and control method for DC-DC converter |
| CN101515800A (en) * | 2008-02-22 | 2009-08-26 | 中芯国际集成电路制造(上海)有限公司 | Low-jitter conversion circuit from CMOS to CML |
-
2010
- 2010-04-12 CN CN2010101442858A patent/CN101847981B/en active Active
- 2010-06-21 WO PCT/CN2010/074166 patent/WO2011127686A1/en active Application Filing
- 2010-06-21 SG SG2010047041A patent/SG174846A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2011127686A1 (en) | 2011-10-20 |
| CN101847981A (en) | 2010-09-29 |
| CN101847981B (en) | 2012-06-06 |
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