SG139694G - Fabricating a semiconductor device with buried oxide - Google Patents

Fabricating a semiconductor device with buried oxide

Info

Publication number
SG139694G
SG139694G SG139694A SG139694A SG139694G SG 139694 G SG139694 G SG 139694G SG 139694 A SG139694 A SG 139694A SG 139694 A SG139694 A SG 139694A SG 139694 G SG139694 G SG 139694G
Authority
SG
Singapore
Prior art keywords
fabricating
semiconductor device
buried oxide
buried
oxide
Prior art date
Application number
SG139694A
Other languages
English (en)
Inventor
Kevin L Mclaughlin
Mark S Birrittella
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to SG139694A priority Critical patent/SG139694G/en
Publication of SG139694G publication Critical patent/SG139694G/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
SG139694A 1985-08-19 1994-09-30 Fabricating a semiconductor device with buried oxide SG139694G (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SG139694A SG139694G (en) 1985-08-19 1994-09-30 Fabricating a semiconductor device with buried oxide

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/766,995 US4717677A (en) 1985-08-19 1985-08-19 Fabricating a semiconductor device with buried oxide
SG139694A SG139694G (en) 1985-08-19 1994-09-30 Fabricating a semiconductor device with buried oxide

Publications (1)

Publication Number Publication Date
SG139694G true SG139694G (en) 1995-01-13

Family

ID=25078158

Family Applications (1)

Application Number Title Priority Date Filing Date
SG139694A SG139694G (en) 1985-08-19 1994-09-30 Fabricating a semiconductor device with buried oxide

Country Status (7)

Country Link
US (1) US4717677A (fr)
EP (1) EP0233202B1 (fr)
JP (1) JPS63500627A (fr)
DE (1) DE3686253T2 (fr)
HK (1) HK14295A (fr)
SG (1) SG139694G (fr)
WO (1) WO1987001238A1 (fr)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4810664A (en) * 1986-08-14 1989-03-07 Hewlett-Packard Company Method for making patterned implanted buried oxide transistors and structures
US4959329A (en) * 1988-03-28 1990-09-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4887143A (en) * 1988-03-28 1989-12-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4988632A (en) * 1990-01-02 1991-01-29 Motorola, Inc. Bipolar process using selective silicon deposition
JP2746499B2 (ja) * 1992-05-15 1998-05-06 三菱電機株式会社 半導体装置及びその製造方法
US5731218A (en) * 1993-11-02 1998-03-24 Siemens Aktiengesellschaft Method for producing a contact hole to a doped region
US5543637A (en) * 1994-11-14 1996-08-06 North Carolina State University Silicon carbide semiconductor devices having buried silicon carbide conduction barrier layers therein
JPH08316223A (ja) * 1995-05-16 1996-11-29 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5869380A (en) * 1998-07-06 1999-02-09 Industrial Technology Research Institute Method for forming a bipolar junction transistor
US6281521B1 (en) 1998-07-09 2001-08-28 Cree Research Inc. Silicon carbide horizontal channel buffered gate semiconductor devices
US6596570B2 (en) * 2001-06-06 2003-07-22 International Business Machines Corporation SOI device with reduced junction capacitance
US7550330B2 (en) * 2006-11-29 2009-06-23 International Business Machines Corporation Deep junction SOI MOSFET with enhanced edge body contacts
US8053327B2 (en) * 2006-12-21 2011-11-08 Globalfoundries Singapore Pte. Ltd. Method of manufacture of an integrated circuit system with self-aligned isolation structures
US9324828B2 (en) 2014-08-12 2016-04-26 International Business Machines Corporation Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure, and methods of forming

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3622382A (en) * 1969-05-05 1971-11-23 Ibm Semiconductor isolation structure and method of producing
US3897274A (en) * 1971-06-01 1975-07-29 Texas Instruments Inc Method of fabricating dielectrically isolated semiconductor structures
US4396933A (en) * 1971-06-18 1983-08-02 International Business Machines Corporation Dielectrically isolated semiconductor devices
DE2507366C3 (de) * 1975-02-20 1980-06-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Unterdrückung parasitärer Schaltungselemente
JPS51135385A (en) * 1975-03-06 1976-11-24 Texas Instruments Inc Method of producing semiconductor device
US4066473A (en) * 1976-07-15 1978-01-03 Fairchild Camera And Instrument Corporation Method of fabricating high-gain transistors
JPS5721856B2 (en) * 1977-11-28 1982-05-10 Nippon Telegraph & Telephone Semiconductor and its manufacture
DE2822911C2 (de) * 1978-05-26 1984-03-01 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Halbleiteranordnung mit mindestens einem pn-Übergang und Verfahren zu ihrer Herstellung
JPS5526660A (en) * 1978-08-16 1980-02-26 Toshiba Corp Semiconductor device and method of manufacturing of the same
JPS5577172A (en) * 1978-12-06 1980-06-10 Oki Electric Ind Co Ltd Semiconductor device
JPS55105366A (en) * 1979-02-06 1980-08-12 Fujitsu Ltd Semiconductor device
DE2946963A1 (de) * 1979-11-21 1981-06-04 Siemens AG, 1000 Berlin und 8000 München Schnelle bipolare transistoren
GB2085224B (en) * 1980-10-07 1984-08-15 Itt Ind Ltd Isolating sc device using oxygen duping
US4601095A (en) * 1981-10-27 1986-07-22 Sumitomo Electric Industries, Ltd. Process for fabricating a Schottky-barrier gate field effect transistor
US4412868A (en) * 1981-12-23 1983-11-01 General Electric Company Method of making integrated circuits utilizing ion implantation and selective epitaxial growth
JPS58111345A (ja) * 1981-12-25 1983-07-02 Hitachi Ltd 半導体装置
US4532003A (en) * 1982-08-09 1985-07-30 Harris Corporation Method of fabrication bipolar transistor with improved base collector breakdown voltage and collector series resistance
US4546536A (en) * 1983-08-04 1985-10-15 International Business Machines Corporation Fabrication methods for high performance lateral bipolar transistors
US4507158A (en) * 1983-08-12 1985-03-26 Hewlett-Packard Co. Trench isolated transistors in semiconductor films
US4706378A (en) * 1985-01-30 1987-11-17 Texas Instruments Incorporated Method of making vertical bipolar transistor having base above buried nitride dielectric formed by deep implantation

Also Published As

Publication number Publication date
EP0233202B1 (fr) 1992-07-29
WO1987001238A1 (fr) 1987-02-26
EP0233202A4 (fr) 1990-06-26
DE3686253D1 (de) 1992-09-03
DE3686253T2 (de) 1992-12-17
EP0233202A1 (fr) 1987-08-26
US4717677A (en) 1988-01-05
HK14295A (en) 1995-02-10
JPS63500627A (ja) 1988-03-03

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