SG139654A1 - Dedicated mechanism for page-mapping in a gpu - Google Patents

Dedicated mechanism for page-mapping in a gpu

Info

Publication number
SG139654A1
SG139654A1 SG200705128-7A SG2007051287A SG139654A1 SG 139654 A1 SG139654 A1 SG 139654A1 SG 2007051287 A SG2007051287 A SG 2007051287A SG 139654 A1 SG139654 A1 SG 139654A1
Authority
SG
Singapore
Prior art keywords
gpu
graphics tlb
address
mapping
page
Prior art date
Application number
SG200705128-7A
Other languages
English (en)
Inventor
Peter C Tong
Sonny S Yeoh
Kevin J Kranzusch
Gary D Lorensen
Kaymann L Woo
Ashish K Kaul
Colyn S Case
Stefan A Gottschalk
Original Assignee
Nvidia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nvidia Corp filed Critical Nvidia Corp
Publication of SG139654A1 publication Critical patent/SG139654A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/654—Look-ahead translation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/125—Frame memory handling using unified memory architecture [UMA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
SG200705128-7A 2006-07-31 2007-07-10 Dedicated mechanism for page-mapping in a gpu SG139654A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US82095206P 2006-07-31 2006-07-31
US82112706P 2006-08-01 2006-08-01
US11/689,485 US20080028181A1 (en) 2006-07-31 2007-03-21 Dedicated mechanism for page mapping in a gpu

Publications (1)

Publication Number Publication Date
SG139654A1 true SG139654A1 (en) 2008-02-29

Family

ID=38461494

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200705128-7A SG139654A1 (en) 2006-07-31 2007-07-10 Dedicated mechanism for page-mapping in a gpu

Country Status (7)

Country Link
US (1) US20080028181A1 (ko)
JP (1) JP4941148B2 (ko)
KR (1) KR101001100B1 (ko)
DE (1) DE102007032307A1 (ko)
GB (1) GB2440617B (ko)
SG (1) SG139654A1 (ko)
TW (1) TWI398771B (ko)

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WO2019237261A1 (zh) * 2018-06-12 2019-12-19 华为技术有限公司 一种内存管理方法、装置及系统
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Also Published As

Publication number Publication date
TW200817899A (en) 2008-04-16
GB0713574D0 (en) 2007-08-22
DE102007032307A1 (de) 2008-02-14
KR101001100B1 (ko) 2010-12-14
TWI398771B (zh) 2013-06-11
US20080028181A1 (en) 2008-01-31
GB2440617B (en) 2009-03-25
KR20080011630A (ko) 2008-02-05
JP2008033928A (ja) 2008-02-14
JP4941148B2 (ja) 2012-05-30
GB2440617A (en) 2008-02-06

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