SG114582A1 - Method and system for managing an allocation of a portion of a memory - Google Patents
Method and system for managing an allocation of a portion of a memoryInfo
- Publication number
- SG114582A1 SG114582A1 SG200206764A SG200206764A SG114582A1 SG 114582 A1 SG114582 A1 SG 114582A1 SG 200206764 A SG200206764 A SG 200206764A SG 200206764 A SG200206764 A SG 200206764A SG 114582 A1 SG114582 A1 SG 114582A1
- Authority
- SG
- Singapore
- Prior art keywords
- allocation
- managing
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/033,778 US6832303B2 (en) | 2002-01-03 | 2002-01-03 | Method and system for managing an allocation of a portion of a memory |
Publications (1)
Publication Number | Publication Date |
---|---|
SG114582A1 true SG114582A1 (en) | 2005-09-28 |
Family
ID=21872383
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200206764A SG114582A1 (en) | 2002-01-03 | 2002-11-08 | Method and system for managing an allocation of a portion of a memory |
Country Status (4)
Country | Link |
---|---|
US (1) | US6832303B2 (ru) |
JP (1) | JP2003216486A (ru) |
KR (1) | KR20030060071A (ru) |
SG (1) | SG114582A1 (ru) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7133972B2 (en) | 2002-06-07 | 2006-11-07 | Micron Technology, Inc. | Memory hub with internal cache and/or memory access prediction |
US7117316B2 (en) | 2002-08-05 | 2006-10-03 | Micron Technology, Inc. | Memory hub and access method having internal row caching |
US6820181B2 (en) | 2002-08-29 | 2004-11-16 | Micron Technology, Inc. | Method and system for controlling memory accesses to memory modules having a memory hub architecture |
US7120727B2 (en) | 2003-06-19 | 2006-10-10 | Micron Technology, Inc. | Reconfigurable memory module and method |
US7260685B2 (en) * | 2003-06-20 | 2007-08-21 | Micron Technology, Inc. | Memory hub and access method having internal prefetch buffers |
US7120743B2 (en) | 2003-10-20 | 2006-10-10 | Micron Technology, Inc. | Arbitration system and method for memory responses in a hub-based memory system |
US7330992B2 (en) * | 2003-12-29 | 2008-02-12 | Micron Technology, Inc. | System and method for read synchronization of memory modules |
US8250295B2 (en) | 2004-01-05 | 2012-08-21 | Smart Modular Technologies, Inc. | Multi-rank memory module that emulates a memory module having a different number of ranks |
US7188219B2 (en) * | 2004-01-30 | 2007-03-06 | Micron Technology, Inc. | Buffer control system and method for a memory system having outstanding read and write request buffers |
US7916574B1 (en) | 2004-03-05 | 2011-03-29 | Netlist, Inc. | Circuit providing load isolation and memory domain translation for memory module |
US7346401B2 (en) * | 2004-05-25 | 2008-03-18 | International Business Machines Corporation | Systems and methods for providing constrained optimization using adaptive regulatory control |
US7519788B2 (en) | 2004-06-04 | 2009-04-14 | Micron Technology, Inc. | System and method for an asynchronous data buffer having buffer write and read pointers |
US7278006B2 (en) * | 2004-12-30 | 2007-10-02 | Intel Corporation | Reducing memory fragmentation |
US7418568B2 (en) * | 2005-01-05 | 2008-08-26 | Sap Ag | Memory management technique |
JP2008529149A (ja) * | 2005-01-31 | 2008-07-31 | エヌエックスピー ビー ヴィ | データ処理システム及びメモリデフラグメンテーション方法 |
US7516291B2 (en) * | 2005-11-21 | 2009-04-07 | Red Hat, Inc. | Cooperative mechanism for efficient application memory allocation |
US9311227B2 (en) * | 2006-10-31 | 2016-04-12 | Hewlett Packard Enterprise Development Lp | Memory management |
US8787060B2 (en) | 2010-11-03 | 2014-07-22 | Netlist, Inc. | Method and apparatus for optimizing driver load in a memory package |
US8516185B2 (en) | 2009-07-16 | 2013-08-20 | Netlist, Inc. | System and method utilizing distributed byte-wise buffers on a memory module |
US8001434B1 (en) | 2008-04-14 | 2011-08-16 | Netlist, Inc. | Memory board with self-testing capability |
US8154901B1 (en) | 2008-04-14 | 2012-04-10 | Netlist, Inc. | Circuit providing load isolation and noise reduction |
US9251149B2 (en) * | 2009-02-03 | 2016-02-02 | Bmc Software, Inc. | Data set size tracking and management |
US9128632B2 (en) | 2009-07-16 | 2015-09-08 | Netlist, Inc. | Memory module with distributed data buffers and method of operation |
WO2015017356A1 (en) | 2013-07-27 | 2015-02-05 | Netlist, Inc. | Memory module with local synchronization |
US11442628B2 (en) | 2018-07-31 | 2022-09-13 | SK Hynix Inc. | Apparatus and method for engaging a plurality of memory systems with each other |
US11249919B2 (en) * | 2018-07-31 | 2022-02-15 | SK Hynix Inc. | Apparatus and method for managing meta data for engagement of plural memory system to store data |
CN110780810B (zh) | 2018-07-31 | 2023-06-27 | 爱思开海力士有限公司 | 用于彼此接合多个存储器系统以存储数据的设备和方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6334175B1 (en) * | 1998-07-22 | 2001-12-25 | Ati Technologies, Inc. | Switchable memory system and memory allocation method |
-
2002
- 2002-01-03 US US10/033,778 patent/US6832303B2/en not_active Expired - Lifetime
- 2002-11-08 SG SG200206764A patent/SG114582A1/en unknown
- 2002-12-05 JP JP2002353401A patent/JP2003216486A/ja not_active Withdrawn
-
2003
- 2003-01-02 KR KR10-2003-0000020A patent/KR20030060071A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
US20030126393A1 (en) | 2003-07-03 |
US6832303B2 (en) | 2004-12-14 |
KR20030060071A (ko) | 2003-07-12 |
JP2003216486A (ja) | 2003-07-31 |
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