SG11202110345XA - Training of artificial neural networks - Google Patents
Training of artificial neural networksInfo
- Publication number
- SG11202110345XA SG11202110345XA SG11202110345XA SG11202110345XA SG11202110345XA SG 11202110345X A SG11202110345X A SG 11202110345XA SG 11202110345X A SG11202110345X A SG 11202110345XA SG 11202110345X A SG11202110345X A SG 11202110345XA SG 11202110345X A SG11202110345X A SG 11202110345XA
- Authority
- SG
- Singapore
- Prior art keywords
- training
- neural networks
- artificial neural
- artificial
- networks
- Prior art date
Links
- 238000013528 artificial neural network Methods 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
- G06N3/084—Backpropagation, e.g. using gradient descent
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
- G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
- G06N3/065—Analogue means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
- G06F2207/4802—Special implementations
- G06F2207/4818—Threshold devices
- G06F2207/4824—Neural networks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/04—Architecture, e.g. interconnection topology
- G06N3/048—Activation functions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biomedical Technology (AREA)
- Biophysics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Molecular Biology (AREA)
- Software Systems (AREA)
- Evolutionary Computation (AREA)
- Data Mining & Analysis (AREA)
- Computational Linguistics (AREA)
- Artificial Intelligence (AREA)
- Mathematical Physics (AREA)
- General Health & Medical Sciences (AREA)
- Neurology (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Complex Calculations (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/413,738 US11531898B2 (en) | 2019-05-16 | 2019-05-16 | Training of artificial neural networks |
| PCT/EP2020/063194 WO2020229468A1 (en) | 2019-05-16 | 2020-05-12 | Training of artificial neural networks |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11202110345XA true SG11202110345XA (en) | 2021-10-28 |
Family
ID=70738523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11202110345XA SG11202110345XA (en) | 2019-05-16 | 2020-05-12 | Training of artificial neural networks |
Country Status (10)
| Country | Link |
|---|---|
| US (1) | US11531898B2 (he) |
| EP (1) | EP3970073A1 (he) |
| JP (1) | JP7427030B2 (he) |
| KR (1) | KR102672586B1 (he) |
| CN (1) | CN113826122A (he) |
| AU (1) | AU2020274862B2 (he) |
| CA (1) | CA3137231A1 (he) |
| IL (1) | IL288055B2 (he) |
| SG (1) | SG11202110345XA (he) |
| WO (1) | WO2020229468A1 (he) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11301752B2 (en) * | 2017-10-24 | 2022-04-12 | International Business Machines Corporation | Memory configuration for implementing a neural network |
| US11562205B2 (en) * | 2019-09-19 | 2023-01-24 | Qualcomm Incorporated | Parallel processing of a convolutional layer of a neural network with compute-in-memory array |
| US11347477B2 (en) * | 2019-09-27 | 2022-05-31 | Intel Corporation | Compute in/near memory (CIM) circuit architecture for unified matrix-matrix and matrix-vector computations |
| US20220269484A1 (en) * | 2021-02-19 | 2022-08-25 | Verisilicon Microelectronics (Shanghai) Co., Ltd. | Accumulation Systems And Methods |
| TWI775402B (zh) * | 2021-04-22 | 2022-08-21 | 臺灣發展軟體科技股份有限公司 | 資料處理電路及故障減輕方法 |
| US20230083270A1 (en) * | 2021-09-14 | 2023-03-16 | International Business Machines Corporation | Mixed signal circuitry for bitwise multiplication with different accuracies |
| JP7209068B1 (ja) | 2021-10-19 | 2023-01-19 | ウィンボンド エレクトロニクス コーポレーション | 半導体記憶装置 |
| KR102517156B1 (ko) * | 2021-12-10 | 2023-04-03 | 인하대학교 산학협력단 | 경계값을 이용한 이진 인공신경망 학습 방법 |
| US11899518B2 (en) | 2021-12-15 | 2024-02-13 | Microsoft Technology Licensing, Llc | Analog MAC aware DNN improvement |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160358075A1 (en) | 2015-06-08 | 2016-12-08 | The Regents Of The University Of Michigan | System for implementing a sparse coding algorithm |
| EP3414702A1 (en) | 2016-02-08 | 2018-12-19 | Spero Devices, Inc. | Analog co-processor |
| CN107533459B (zh) * | 2016-03-31 | 2020-11-20 | 慧与发展有限责任合伙企业 | 使用电阻存储器阵列的数据处理方法和单元 |
| JP6556768B2 (ja) | 2017-01-25 | 2019-08-07 | 株式会社東芝 | 積和演算器、ネットワークユニットおよびネットワーク装置 |
| JP6794891B2 (ja) | 2017-03-22 | 2020-12-02 | 株式会社デンソー | ニューラルネットワーク回路 |
| US10726514B2 (en) | 2017-04-28 | 2020-07-28 | Intel Corporation | Compute optimizations for low precision machine learning operations |
| US20190005035A1 (en) | 2017-05-31 | 2019-01-03 | Semiconductor Energy Laboratory Co., Ltd. | Information search system, intellectual property information search system, information search method, and intellectual property information search method |
| US11348002B2 (en) | 2017-10-24 | 2022-05-31 | International Business Machines Corporation | Training of artificial neural networks |
| US11138497B2 (en) * | 2018-07-17 | 2021-10-05 | Macronix International Co., Ltd | In-memory computing devices for neural networks |
| US11061646B2 (en) | 2018-09-28 | 2021-07-13 | Intel Corporation | Compute in memory circuits with multi-Vdd arrays and/or analog multipliers |
| US11133059B2 (en) * | 2018-12-06 | 2021-09-28 | Western Digital Technologies, Inc. | Non-volatile memory die with deep learning neural network |
-
2019
- 2019-05-16 US US16/413,738 patent/US11531898B2/en active Active
-
2020
- 2020-05-12 JP JP2021568206A patent/JP7427030B2/ja active Active
- 2020-05-12 SG SG11202110345XA patent/SG11202110345XA/en unknown
- 2020-05-12 KR KR1020217036993A patent/KR102672586B1/ko active IP Right Grant
- 2020-05-12 EP EP20726050.6A patent/EP3970073A1/en active Pending
- 2020-05-12 AU AU2020274862A patent/AU2020274862B2/en active Active
- 2020-05-12 IL IL288055A patent/IL288055B2/he unknown
- 2020-05-12 CA CA3137231A patent/CA3137231A1/en active Pending
- 2020-05-12 WO PCT/EP2020/063194 patent/WO2020229468A1/en active Application Filing
- 2020-05-12 CN CN202080034604.1A patent/CN113826122A/zh active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JP2022533124A (ja) | 2022-07-21 |
| US20200364577A1 (en) | 2020-11-19 |
| AU2020274862B2 (en) | 2023-03-09 |
| AU2020274862A1 (en) | 2021-10-14 |
| WO2020229468A1 (en) | 2020-11-19 |
| IL288055B1 (he) | 2024-01-01 |
| IL288055A (he) | 2022-01-01 |
| JP7427030B2 (ja) | 2024-02-02 |
| KR20210154816A (ko) | 2021-12-21 |
| US11531898B2 (en) | 2022-12-20 |
| IL288055B2 (he) | 2024-05-01 |
| CA3137231A1 (en) | 2020-11-19 |
| KR102672586B1 (ko) | 2024-06-07 |
| EP3970073A1 (en) | 2022-03-23 |
| CN113826122A (zh) | 2021-12-21 |
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