SG11202110345XA - Training of artificial neural networks - Google Patents

Training of artificial neural networks

Info

Publication number
SG11202110345XA
SG11202110345XA SG11202110345XA SG11202110345XA SG11202110345XA SG 11202110345X A SG11202110345X A SG 11202110345XA SG 11202110345X A SG11202110345X A SG 11202110345XA SG 11202110345X A SG11202110345X A SG 11202110345XA SG 11202110345X A SG11202110345X A SG 11202110345XA
Authority
SG
Singapore
Prior art keywords
training
neural networks
artificial neural
artificial
networks
Prior art date
Application number
SG11202110345XA
Inventor
Gallo-Bourdeau Manuel Le
Riduan Khaddam-Aljameh
Lukas Kull
Pier Andrea Francese
Thomas Toifl
Abu Sebastian
Evangelos Stavros Eleftheriou
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG11202110345XA publication Critical patent/SG11202110345XA/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/08Learning methods
    • G06N3/084Backpropagation, e.g. using gradient descent
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443Sum of products
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065Analogue means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802Special implementations
    • G06F2207/4818Threshold devices
    • G06F2207/4824Neural networks
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/04Architecture, e.g. interconnection topology
    • G06N3/048Activation functions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Software Systems (AREA)
  • Data Mining & Analysis (AREA)
  • General Health & Medical Sciences (AREA)
  • Computational Linguistics (AREA)
  • Mathematical Physics (AREA)
  • Molecular Biology (AREA)
  • Evolutionary Computation (AREA)
  • Neurology (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Complex Calculations (AREA)
  • Semiconductor Memories (AREA)
SG11202110345XA 2019-05-16 2020-05-12 Training of artificial neural networks SG11202110345XA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/413,738 US11531898B2 (en) 2019-05-16 2019-05-16 Training of artificial neural networks
PCT/EP2020/063194 WO2020229468A1 (en) 2019-05-16 2020-05-12 Training of artificial neural networks

Publications (1)

Publication Number Publication Date
SG11202110345XA true SG11202110345XA (en) 2021-10-28

Family

ID=70738523

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202110345XA SG11202110345XA (en) 2019-05-16 2020-05-12 Training of artificial neural networks

Country Status (10)

Country Link
US (1) US11531898B2 (en)
EP (1) EP3970073A1 (en)
JP (1) JP7427030B2 (en)
KR (1) KR102672586B1 (en)
CN (1) CN113826122A (en)
AU (1) AU2020274862B2 (en)
CA (1) CA3137231A1 (en)
IL (1) IL288055B2 (en)
SG (1) SG11202110345XA (en)
WO (1) WO2020229468A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11301752B2 (en) * 2017-10-24 2022-04-12 International Business Machines Corporation Memory configuration for implementing a neural network
US12026601B2 (en) * 2019-06-26 2024-07-02 Micron Technology, Inc. Stacked artificial neural networks
US11562205B2 (en) * 2019-09-19 2023-01-24 Qualcomm Incorporated Parallel processing of a convolutional layer of a neural network with compute-in-memory array
US11347477B2 (en) * 2019-09-27 2022-05-31 Intel Corporation Compute in/near memory (CIM) circuit architecture for unified matrix-matrix and matrix-vector computations
US20220269484A1 (en) * 2021-02-19 2022-08-25 Verisilicon Microelectronics (Shanghai) Co., Ltd. Accumulation Systems And Methods
TWI775402B (en) * 2021-04-22 2022-08-21 臺灣發展軟體科技股份有限公司 Data processing circuit and fault-mitigating method
US20220414444A1 (en) * 2021-06-29 2022-12-29 Qualcomm Incorporated Computation in memory (cim) architecture and dataflow supporting a depth-wise convolutional neural network (cnn)
US20230083270A1 (en) * 2021-09-14 2023-03-16 International Business Machines Corporation Mixed signal circuitry for bitwise multiplication with different accuracies
JP7209068B1 (en) 2021-10-19 2023-01-19 ウィンボンド エレクトロニクス コーポレーション semiconductor storage device
KR102517156B1 (en) * 2021-12-10 2023-04-03 인하대학교 산학협력단 Learning method of binary artificial neural network using boundary value
US11899518B2 (en) 2021-12-15 2024-02-13 Microsoft Technology Licensing, Llc Analog MAC aware DNN improvement

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160358075A1 (en) 2015-06-08 2016-12-08 The Regents Of The University Of Michigan System for implementing a sparse coding algorithm
EP3414702A1 (en) 2016-02-08 2018-12-19 Spero Devices, Inc. Analog co-processor
CN107533459B (en) * 2016-03-31 2020-11-20 慧与发展有限责任合伙企业 Data processing method and unit using resistance memory array
JP6556768B2 (en) * 2017-01-25 2019-08-07 株式会社東芝 Multiply-accumulator, network unit and network device
JP6794891B2 (en) 2017-03-22 2020-12-02 株式会社デンソー Neural network circuit
US10726514B2 (en) 2017-04-28 2020-07-28 Intel Corporation Compute optimizations for low precision machine learning operations
US20190005035A1 (en) * 2017-05-31 2019-01-03 Semiconductor Energy Laboratory Co., Ltd. Information search system, intellectual property information search system, information search method, and intellectual property information search method
US11348002B2 (en) * 2017-10-24 2022-05-31 International Business Machines Corporation Training of artificial neural networks
US11138497B2 (en) * 2018-07-17 2021-10-05 Macronix International Co., Ltd In-memory computing devices for neural networks
US11061646B2 (en) 2018-09-28 2021-07-13 Intel Corporation Compute in memory circuits with multi-Vdd arrays and/or analog multipliers
US11133059B2 (en) * 2018-12-06 2021-09-28 Western Digital Technologies, Inc. Non-volatile memory die with deep learning neural network

Also Published As

Publication number Publication date
CA3137231A1 (en) 2020-11-19
WO2020229468A1 (en) 2020-11-19
JP2022533124A (en) 2022-07-21
AU2020274862B2 (en) 2023-03-09
IL288055B2 (en) 2024-05-01
AU2020274862A1 (en) 2021-10-14
KR102672586B1 (en) 2024-06-07
CN113826122A (en) 2021-12-21
KR20210154816A (en) 2021-12-21
IL288055B1 (en) 2024-01-01
IL288055A (en) 2022-01-01
JP7427030B2 (en) 2024-02-02
US20200364577A1 (en) 2020-11-19
EP3970073A1 (en) 2022-03-23
US11531898B2 (en) 2022-12-20

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