SG11202109549WA - System for fracturing a plurality of wafer assemblies - Google Patents

System for fracturing a plurality of wafer assemblies

Info

Publication number
SG11202109549WA
SG11202109549WA SG11202109549WA SG11202109549WA SG 11202109549W A SG11202109549W A SG 11202109549WA SG 11202109549W A SG11202109549W A SG 11202109549WA SG 11202109549W A SG11202109549W A SG 11202109549WA
Authority
SG
Singapore
Prior art keywords
fracturing
wafer assemblies
wafer
assemblies
Prior art date
Application number
Other languages
English (en)
Inventor
Didier Landru
Oleg Kononchuk
Mohamed Nadia Ben
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202109549WA publication Critical patent/SG11202109549WA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67023—Apparatus for fluid treatment for general liquid treatment, e.g. etching followed by cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Disintegrating Or Milling (AREA)
SG11202109549W 2019-03-15 2020-02-26 System for fracturing a plurality of wafer assemblies SG11202109549WA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1902680A FR3093716B1 (fr) 2019-03-15 2019-03-15 systeme de fracture d'une pluralitÉ d'assemblages de tranches.
PCT/FR2020/050370 WO2020188170A1 (fr) 2019-03-15 2020-02-26 Système de fracture d'une pluralité d'assemblages de tranches

Publications (1)

Publication Number Publication Date
SG11202109549WA true SG11202109549WA (en) 2021-10-28

Family

ID=67660219

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202109549W SG11202109549WA (en) 2019-03-15 2020-02-26 System for fracturing a plurality of wafer assemblies

Country Status (9)

Country Link
US (2) US12002690B2 (zh)
EP (1) EP3939072B1 (zh)
JP (1) JP7505151B2 (zh)
KR (1) KR20210138056A (zh)
CN (1) CN113574646A (zh)
FR (1) FR3093716B1 (zh)
SG (1) SG11202109549WA (zh)
TW (1) TWI840512B (zh)
WO (1) WO2020188170A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117854950A (zh) * 2024-02-01 2024-04-09 上海理工大学 一种MXene/含氮钛氧化物/碳复合材料及其制备方法和应用

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6382292B1 (en) * 1997-03-27 2002-05-07 Canon Kabushiki Kaisha Method and apparatus for separating composite member using fluid
JP3492142B2 (ja) 1997-03-27 2004-02-03 キヤノン株式会社 半導体基材の製造方法
JP2877800B2 (ja) 1997-03-27 1999-03-31 キヤノン株式会社 複合部材の分離方法、分離された部材、分離装置、半導体基体の作製方法および半導体基体
FR2828337B1 (fr) * 2001-08-02 2003-10-24 Commissariat Energie Atomique Circuit resonant hyperfrequence et filtre hyperfrequence accordable utilisant le circuit resonant
FR2828428B1 (fr) 2001-08-07 2003-10-17 Soitec Silicon On Insulator Dispositif de decollement de substrats et procede associe
JP2004214399A (ja) 2002-12-27 2004-07-29 Sumitomo Mitsubishi Silicon Corp 半導体基板の製造方法およびウェーハ剥離熱処理装置
JP2005079388A (ja) 2003-09-01 2005-03-24 Sumitomo Mitsubishi Silicon Corp 貼り合わせウェーハの分離方法及び分離装置
FR2861497B1 (fr) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Procede de transfert catastrophique d'une couche fine apres co-implantation
FR2919960B1 (fr) 2007-08-08 2010-05-21 Soitec Silicon On Insulator Procede et installation pour la fracture d'un substrat composite selon un plan de fragilisation
TWI564988B (zh) * 2011-06-03 2017-01-01 Ｔｅｌ Ｎｅｘｘ公司 平行且單一的基板處理系統
FR2995440A1 (fr) * 2012-09-07 2014-03-14 Soitec Silicon On Insulator Dispositif de separation de deux substrats

Also Published As

Publication number Publication date
CN113574646A (zh) 2021-10-29
TW202040674A (zh) 2020-11-01
EP3939072B1 (fr) 2023-02-22
FR3093716B1 (fr) 2021-02-12
FR3093716A1 (fr) 2020-09-18
EP3939072A1 (fr) 2022-01-19
JP2022525152A (ja) 2022-05-11
US20220181173A1 (en) 2022-06-09
JP7505151B2 (ja) 2024-06-25
WO2020188170A1 (fr) 2020-09-24
KR20210138056A (ko) 2021-11-18
TWI840512B (zh) 2024-05-01
US20240222158A1 (en) 2024-07-04
US12002690B2 (en) 2024-06-04

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