SG11202107864RA - Memory arrays and methods used in forming a memory array - Google Patents

Memory arrays and methods used in forming a memory array

Info

Publication number
SG11202107864RA
SG11202107864RA SG11202107864RA SG11202107864RA SG11202107864RA SG 11202107864R A SG11202107864R A SG 11202107864RA SG 11202107864R A SG11202107864R A SG 11202107864RA SG 11202107864R A SG11202107864R A SG 11202107864RA SG 11202107864R A SG11202107864R A SG 11202107864RA
Authority
SG
Singapore
Prior art keywords
memory
forming
methods used
memory array
arrays
Prior art date
Application number
SG11202107864RA
Inventor
Bharat Bhushan
Chris Carlson
Collin Howder
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG11202107864RA publication Critical patent/SG11202107864RA/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
SG11202107864RA 2019-02-15 2020-01-28 Memory arrays and methods used in forming a memory array SG11202107864RA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/277,311 US11177269B2 (en) 2019-02-15 2019-02-15 Memory arrays and methods used in forming a memory array
PCT/US2020/015426 WO2020167457A1 (en) 2019-02-15 2020-01-28 Memory arrays and methods used in forming a memory array

Publications (1)

Publication Number Publication Date
SG11202107864RA true SG11202107864RA (en) 2021-08-30

Family

ID=72042296

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202107864RA SG11202107864RA (en) 2019-02-15 2020-01-28 Memory arrays and methods used in forming a memory array

Country Status (8)

Country Link
US (2) US11177269B2 (en)
EP (1) EP3925005A4 (en)
JP (1) JP2022519701A (en)
KR (1) KR102646564B1 (en)
CN (1) CN113424320B (en)
SG (1) SG11202107864RA (en)
TW (1) TWI738211B (en)
WO (1) WO2020167457A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11631740B2 (en) 2020-11-13 2023-04-18 Micron Technology, Inc. Memory array and method used in forming a memory array comprising strings of memory cells
US11996151B2 (en) * 2021-05-10 2024-05-28 Micron Technology, Inc. Memory arrays and methods used in forming a memory array comprising strings of memory cells
US11895835B2 (en) 2021-06-15 2024-02-06 Micron Technology, Inc. Integrated circuitry comprising a memory array comprising strings of memory cells and methods including a method used in forming a memory array comprising strings of memory cells
US20220399363A1 (en) * 2021-06-15 2022-12-15 Micron Technology, Inc. Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Methods Including A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells
US20230057852A1 (en) * 2021-08-23 2023-02-23 Micron Technology, Inc. Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells
TWI809533B (en) * 2021-10-19 2023-07-21 旺宏電子股份有限公司 Memory device

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007281470A (en) * 2006-04-04 2007-10-25 Samsung Electronics Co Ltd Gate structure of integrated circuit memory device having charge storing nano crystals in metal oxide dielectric film and method of forming the same
KR100735534B1 (en) 2006-04-04 2007-07-04 삼성전자주식회사 Nano crystal nonvolatile semiconductor integrated circuit device and fabrication method thereof
US7816727B2 (en) * 2007-08-27 2010-10-19 Macronix International Co., Ltd. High-κ capped blocking dielectric bandgap engineered SONOS and MONOS
JP2009164260A (en) * 2007-12-28 2009-07-23 Toshiba Corp Nonvolatile semiconductor memory
JP5300419B2 (en) 2008-11-05 2013-09-25 株式会社東芝 Nonvolatile semiconductor memory device and manufacturing method thereof
KR101585616B1 (en) 2009-12-16 2016-01-15 삼성전자주식회사 Semiconductor device and method for fabricating the same
KR101660432B1 (en) 2010-06-07 2016-09-27 삼성전자 주식회사 Semiconductor memory device having vertical structure
KR20110135692A (en) 2010-06-11 2011-12-19 삼성전자주식회사 Three dimensional semiconductor memory device and method for manufacturing the same
KR20120068392A (en) 2010-12-17 2012-06-27 삼성전자주식회사 Method for manufacturing non-volatile memory device and contact plug of semiconductor device
KR101206157B1 (en) 2011-04-26 2012-11-28 에스케이하이닉스 주식회사 3d structured non-volatile memory device and method for manufacturing the same
KR20130116607A (en) * 2012-04-16 2013-10-24 삼성전자주식회사 Three dimensional semiconductor memory device and method of fabricating the same
US9698153B2 (en) 2013-03-12 2017-07-04 Sandisk Technologies Llc Vertical NAND and method of making thereof using sequential stack etching and self-aligned landing pad
KR20150067811A (en) * 2013-12-09 2015-06-19 에스케이하이닉스 주식회사 Semiconductor device and method of manufacturing the same
KR102190350B1 (en) 2014-05-02 2020-12-11 삼성전자주식회사 Semiconductor Memory Device And Method of Fabricating The Same
KR102234273B1 (en) * 2014-07-02 2021-04-02 삼성전자주식회사 Semiconductor memory device
KR20160018921A (en) 2014-08-07 2016-02-18 삼성전자주식회사 Semiconductor Memory Device And Method of Fabricating The Same
US9431419B2 (en) 2014-09-12 2016-08-30 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing same
US9368509B2 (en) 2014-10-15 2016-06-14 Sandisk Technologies Inc. Three-dimensional memory structure having self-aligned drain regions and methods of making thereof
US9576971B2 (en) 2014-12-09 2017-02-21 Sandisk Technologies Llc Three-dimensional memory structure having a back gate electrode
US9355727B1 (en) 2014-12-09 2016-05-31 Sandisk Technologies Inc. Three-dimensional memory structure having a back gate electrode
KR101946179B1 (en) 2014-12-09 2019-02-08 샌디스크 테크놀로지스 엘엘씨 Three-dimensional memory structure having a back gate electrode
US9484357B2 (en) 2014-12-16 2016-11-01 Sandisk Technologies Llc Selective blocking dielectric formation in a three-dimensional memory structure
KR20160080365A (en) 2014-12-29 2016-07-08 에스케이하이닉스 주식회사 Electronic device and manufacturing method thereof
KR20160094186A (en) 2015-01-30 2016-08-09 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method thereof
US9627402B2 (en) * 2015-02-11 2017-04-18 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing the same
US9553105B2 (en) 2015-03-10 2017-01-24 Samsung Electronics Co., Ltd. Semiconductor devices including gate insulation layers on channel materials
KR102332359B1 (en) 2015-05-19 2021-11-29 삼성전자주식회사 Vertical memory devices
US9741732B2 (en) * 2015-08-19 2017-08-22 Micron Technology, Inc. Integrated structures
KR102453709B1 (en) * 2015-10-29 2022-10-12 삼성전자주식회사 Vertical memory devices
US9799670B2 (en) * 2015-11-20 2017-10-24 Sandisk Technologies Llc Three dimensional NAND device containing dielectric pillars for a buried source line and method of making thereof
KR102543998B1 (en) * 2015-12-03 2023-06-16 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method thereof
KR102607825B1 (en) * 2016-01-18 2023-11-30 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method thereof
US9859363B2 (en) * 2016-02-16 2018-01-02 Sandisk Technologies Llc Self-aligned isolation dielectric structures for a three-dimensional memory device
JP2017168527A (en) 2016-03-14 2017-09-21 東芝メモリ株式会社 Semiconductor storage device and method for manufacturing the same
US9812463B2 (en) 2016-03-25 2017-11-07 Sandisk Technologies Llc Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof
US9741737B1 (en) 2016-04-15 2017-08-22 Micron Technology, Inc. Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material
US9922716B2 (en) 2016-04-23 2018-03-20 Sandisk Technologies Llc Architecture for CMOS under array
KR102609348B1 (en) 2016-10-26 2023-12-06 삼성전자주식회사 Semiconductor device and method for fabricating the same
US10008570B2 (en) 2016-11-03 2018-06-26 Sandisk Technologies Llc Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
US10128265B2 (en) 2017-01-18 2018-11-13 Micron Technology, Inc. Memory cells, integrated structures and memory arrays
US9978772B1 (en) 2017-03-14 2018-05-22 Micron Technology, Inc. Memory cells and integrated structures
US10170492B2 (en) 2017-04-07 2019-01-01 Macronix International Co., Ltd. Memory device and method for fabricating the same
US10043819B1 (en) * 2017-05-17 2018-08-07 Macronix International Co., Ltd. Method for manufacturing 3D NAND memory using gate replacement, and resulting structures
US10224340B2 (en) 2017-06-19 2019-03-05 Sandisk Technologies Llc Three-dimensional memory device having discrete direct source strap contacts and method of making thereof
CN108807405B (en) 2018-06-12 2020-10-27 长江存储科技有限责任公司 Three-dimensional memory and manufacturing method thereof
US10748922B2 (en) * 2018-11-28 2020-08-18 Micron Technology, Inc. Memory arrays and methods used in forming a memory array
CN109768144B (en) 2018-12-25 2020-03-31 旭宇光电（深圳）股份有限公司 Light emitting device for plant illumination
US11380699B2 (en) 2019-02-28 2022-07-05 Micron Technology, Inc. Memory array and methods used in forming a memory array
US10903237B1 (en) 2019-11-01 2021-01-26 Sandisk Technologies Llc Three-dimensional memory device including stepped connection plates and methods of forming the same

Also Published As

Publication number Publication date
US20200266203A1 (en) 2020-08-20
WO2020167457A1 (en) 2020-08-20
TW202040792A (en) 2020-11-01
KR102646564B1 (en) 2024-03-12
US20210151454A1 (en) 2021-05-20
US11678483B2 (en) 2023-06-13
JP2022519701A (en) 2022-03-24
KR20210116666A (en) 2021-09-27
CN113424320B (en) 2024-04-16
CN113424320A (en) 2021-09-21
EP3925005A4 (en) 2022-11-16
TWI738211B (en) 2021-09-01
EP3925005A1 (en) 2021-12-22
US11177269B2 (en) 2021-11-16

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