SG11202006829UA - Multi-mode standard cell logic and self-startup for battery-indifferent or pure energy harvesting systems - Google Patents

Multi-mode standard cell logic and self-startup for battery-indifferent or pure energy harvesting systems

Info

Publication number
SG11202006829UA
SG11202006829UA SG11202006829UA SG11202006829UA SG11202006829UA SG 11202006829U A SG11202006829U A SG 11202006829UA SG 11202006829U A SG11202006829U A SG 11202006829UA SG 11202006829U A SG11202006829U A SG 11202006829UA SG 11202006829U A SG11202006829U A SG 11202006829UA
Authority
SG
Singapore
Prior art keywords
indifferent
startup
battery
self
standard cell
Prior art date
Application number
SG11202006829UA
Inventor
Longyang Lin
Saurabh Jain
Massimo Alioto
Original Assignee
Nat Univ Singapore
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nat Univ Singapore filed Critical Nat Univ Singapore
Publication of SG11202006829UA publication Critical patent/SG11202006829UA/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
SG11202006829UA 2018-02-09 2019-02-08 Multi-mode standard cell logic and self-startup for battery-indifferent or pure energy harvesting systems SG11202006829UA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG10201801131X 2018-02-09
PCT/SG2019/050075 WO2019156636A1 (en) 2018-02-09 2019-02-08 Multi-mode standard cell logic and self-startup for battery-indifferent or pure energy harvesting systems

Publications (1)

Publication Number Publication Date
SG11202006829UA true SG11202006829UA (en) 2020-08-28

Family

ID=67549160

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202006829UA SG11202006829UA (en) 2018-02-09 2019-02-08 Multi-mode standard cell logic and self-startup for battery-indifferent or pure energy harvesting systems

Country Status (4)

Country Link
US (2) US11196422B2 (en)
CN (1) CN111684723B (en)
SG (1) SG11202006829UA (en)
WO (1) WO2019156636A1 (en)

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02179121A (en) 1988-12-29 1990-07-12 Nec Corp Inverter circuit
JPH05114853A (en) 1991-10-22 1993-05-07 Seiko Epson Corp Low-noise output driving circuit
JP2647587B2 (en) 1991-12-26 1997-08-27 川崎製鉄株式会社 Semiconductor circuit
US6025736A (en) * 1993-01-08 2000-02-15 Dynalogic Fast reprogrammable logic with active links between cells
US6169419B1 (en) * 1998-09-10 2001-01-02 Intel Corporation Method and apparatus for reducing standby leakage current using a transistor stack effect
US6255867B1 (en) 2000-02-23 2001-07-03 Pericom Semiconductor Corp. CMOS output buffer with feedback control on sources of pre-driver stage
JP4409958B2 (en) * 2002-03-27 2010-02-03 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニア Low power high performance memory circuit and related method
US20030218478A1 (en) 2002-05-24 2003-11-27 Sani Mehdi Hamidi Regulation of crowbar current in circuits employing footswitches/headswitches
WO2005057628A2 (en) * 2003-12-08 2005-06-23 University Of South Florida A method and apparatus for reducing leakage in integrated circuits
GB0708324D0 (en) 2007-04-30 2007-06-06 Univ Catholique Louvain Ultra-low-power circuit
KR101252698B1 (en) * 2009-04-29 2013-04-09 퀄컴 인코포레이티드 Clock gating system and method
US8581637B2 (en) 2011-06-29 2013-11-12 Intel Corporation Low-power, low-latency power-gate apparatus and method
US8519775B2 (en) * 2011-07-28 2013-08-27 Arm Limited Voltage regulation of a virtual power rail
JP2014168131A (en) 2013-02-28 2014-09-11 Japan Display Central Co Ltd CMOS inverter circuit
FI20150294A (en) 2015-10-23 2017-04-24 Ari Paasio Low power logic family

Also Published As

Publication number Publication date
WO2019156636A1 (en) 2019-08-15
US11196422B2 (en) 2021-12-07
CN111684723A (en) 2020-09-18
US20200395940A1 (en) 2020-12-17
CN111684723B (en) 2024-05-10
US11799483B2 (en) 2023-10-24
US20220052693A1 (en) 2022-02-17

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