SG11202002450YA - Clocking circuit arrangement and method of forming the same - Google Patents

Clocking circuit arrangement and method of forming the same

Info

Publication number
SG11202002450YA
SG11202002450YA SG11202002450YA SG11202002450YA SG11202002450YA SG 11202002450Y A SG11202002450Y A SG 11202002450YA SG 11202002450Y A SG11202002450Y A SG 11202002450YA SG 11202002450Y A SG11202002450Y A SG 11202002450YA SG 11202002450Y A SG11202002450Y A SG 11202002450YA
Authority
SG
Singapore
Prior art keywords
forming
same
circuit arrangement
clocking circuit
clocking
Prior art date
Application number
SG11202002450YA
Inventor
Jun Zhou
Xin Liu
Jingjing Lan
Original Assignee
Agency Science Tech & Res
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency Science Tech & Res filed Critical Agency Science Tech & Res
Publication of SG11202002450YA publication Critical patent/SG11202002450YA/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/249—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors using clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
SG11202002450YA 2017-10-03 2018-10-01 Clocking circuit arrangement and method of forming the same SG11202002450YA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG10201708122W 2017-10-03
PCT/SG2018/050496 WO2019070196A1 (en) 2017-10-03 2018-10-01 Clocking circuit arrangement and method of forming the same

Publications (1)

Publication Number Publication Date
SG11202002450YA true SG11202002450YA (en) 2020-04-29

Family

ID=65994751

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202002450YA SG11202002450YA (en) 2017-10-03 2018-10-01 Clocking circuit arrangement and method of forming the same

Country Status (3)

Country Link
US (1) US20200228105A1 (en)
SG (1) SG11202002450YA (en)
WO (1) WO2019070196A1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5289060A (en) * 1992-09-16 1994-02-22 Texas Instruments Incorporated Programmable glitch filter
JP2576366B2 (en) * 1993-06-23 1997-01-29 日本電気株式会社 Variable delay buffer circuit
US8384418B1 (en) * 2009-09-08 2013-02-26 Xilinx, Inc. Mitigating the effect of single event transients on input/output pins of an integrated circuit device
CN105897243B (en) * 2016-03-31 2017-06-06 中国人民解放军国防科学技术大学 A kind of clock driver circuit of anti-single particle transient state

Also Published As

Publication number Publication date
US20200228105A1 (en) 2020-07-16
WO2019070196A1 (en) 2019-04-11

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