SG11201908892TA - Memory refresh technology and computer system - Google Patents
Memory refresh technology and computer systemInfo
- Publication number
- SG11201908892TA SG11201908892TA SG11201908892TA SG11201908892TA SG 11201908892T A SG11201908892T A SG 11201908892TA SG 11201908892T A SG11201908892T A SG 11201908892TA SG 11201908892T A SG11201908892T A SG 11201908892TA
- Authority
- SG
- Singapore
- Prior art keywords
- memory
- computer system
- refresh
- rank
- memory refresh
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40618—Refresh operations over multiple banks or interleaving
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Abstract
MEMORY REFRESH TECHNOLOGY AND COMPUTER SYSTEM This application provides a memory refresh technology and a computer system. The memory refresh technology is applied to a computer system including a memory controller and a dynamic random access memory DRAM. According to the memory refresh technology, 5 the memory controller receives access requests. When a quantity of access requests for accessing a first rank in the DRAM that are in the received access requests is greater than 0 and less than a second threshold, the memory controller refreshes the first rank. According to the memory refresh technology provided in this application, the first rank can be refreshed in time even if the first rank cannot be in an idle state. Therefore, impact caused on computer 10 system performance by an increase in passive refreshes caused by refresh postponements is mitigated, memory refresh flexibility is improved, and refresh overheads are reduced. Figure 3 15
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2017/080640 WO2018188085A1 (en) | 2017-04-14 | 2017-04-14 | Memory refreshing technique and computer system |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201908892TA true SG11201908892TA (en) | 2019-11-28 |
Family
ID=63792104
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201908892T SG11201908892TA (en) | 2017-04-14 | 2017-04-14 | Memory refresh technology and computer system |
Country Status (10)
Country | Link |
---|---|
US (1) | US20200066330A1 (en) |
EP (1) | EP3605542B1 (en) |
JP (1) | JP7043515B2 (en) |
KR (1) | KR102258360B1 (en) |
CN (1) | CN110546707B (en) |
AU (1) | AU2017409368B2 (en) |
BR (1) | BR112019021554B1 (en) |
CA (1) | CA3058778C (en) |
SG (1) | SG11201908892TA (en) |
WO (1) | WO2018188085A1 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11244717B2 (en) * | 2019-12-02 | 2022-02-08 | Micron Technology, Inc. | Write operation techniques for memory systems |
KR20220031793A (en) | 2020-09-03 | 2022-03-14 | 삼성전자주식회사 | Memory device, memory system having the same, controller for controlling the same, and operating methed thereof |
US11798604B2 (en) * | 2021-09-01 | 2023-10-24 | Dell Products L.P. | Memory architecture having ranks with variable data widths |
CN113741820B (en) * | 2021-09-18 | 2023-10-03 | 青岛海信传媒网络技术有限公司 | Method for refreshing data from memory to eMMC memory and display device |
US20230236653A1 (en) * | 2022-01-26 | 2023-07-27 | Samsung Electronics Co.,Ltd. | Power reduction for systems having multiple ranks of memory |
US20230359373A1 (en) * | 2022-05-03 | 2023-11-09 | Qualcomm Incorporated | Selective refresh for memory devices |
CN115148248B (en) * | 2022-09-06 | 2022-11-08 | 北京奎芯集成电路设计有限公司 | Deep learning-based DRAM (dynamic random Access memory) refreshing method and device |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0349094A (en) * | 1989-07-18 | 1991-03-01 | Toshiba Corp | Memory controller |
JPH10149311A (en) * | 1996-11-20 | 1998-06-02 | Ricoh Co Ltd | Memory controller |
JP4154010B2 (en) * | 1997-07-17 | 2008-09-24 | キヤノン株式会社 | Memory control device and memory control method |
CN101000798B (en) * | 2007-01-12 | 2010-05-19 | 威盛电子股份有限公司 | Memory updating method and memory updating system |
WO2009139109A1 (en) * | 2008-05-13 | 2009-11-19 | パナソニック株式会社 | Memory control device and information processing device using the same |
US8639874B2 (en) * | 2008-12-22 | 2014-01-28 | International Business Machines Corporation | Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device |
JP5155221B2 (en) * | 2009-03-11 | 2013-03-06 | ルネサスエレクトロニクス株式会社 | Memory control device |
US8489807B2 (en) * | 2010-12-03 | 2013-07-16 | International Business Machines Corporation | Techniques for performing refresh operations in high-density memories |
US8775725B2 (en) * | 2010-12-06 | 2014-07-08 | Intel Corporation | Memory device refresh commands on the fly |
US8539146B2 (en) * | 2011-11-28 | 2013-09-17 | International Business Machines Corporation | Apparatus for scheduling memory refresh operations including power states |
US9269418B2 (en) * | 2012-02-06 | 2016-02-23 | Arm Limited | Apparatus and method for controlling refreshing of data in a DRAM |
US8909874B2 (en) * | 2012-02-13 | 2014-12-09 | International Business Machines Corporation | Memory reorder queue biasing preceding high latency operations |
US9196347B2 (en) * | 2013-03-14 | 2015-11-24 | International Business Machines Corporation | DRAM controller for variable refresh operation timing |
CN104143355B (en) * | 2013-05-09 | 2018-01-23 | 华为技术有限公司 | A kind of method and apparatus of refreshed dram |
CN105280215B (en) * | 2014-06-09 | 2018-01-23 | 华为技术有限公司 | Dynamic random access memory DRAM method for refreshing, equipment and system |
US9685219B2 (en) * | 2015-05-13 | 2017-06-20 | Samsung Electronics Co., Ltd. | Semiconductor memory device for deconcentrating refresh commands and system including the same |
US9576637B1 (en) * | 2016-05-25 | 2017-02-21 | Advanced Micro Devices, Inc. | Fine granularity refresh |
CN106875971B (en) * | 2017-02-16 | 2021-01-22 | 上海兆芯集成电路有限公司 | Dynamic random access memory controller and control method thereof |
EP3605541A4 (en) * | 2017-04-14 | 2020-04-01 | Huawei Technologies Co., Ltd. | Memory refresh technology and computer system |
US10236035B1 (en) * | 2017-12-04 | 2019-03-19 | Nanya Technology Corporation | DRAM memory device adjustable refresh rate method to alleviate effects of row hammer events |
US10969997B2 (en) * | 2018-11-07 | 2021-04-06 | Intel Corporation | Memory controller that filters a count of row activate commands collectively sent to a set of memory banks |
-
2017
- 2017-04-14 CN CN201780089579.5A patent/CN110546707B/en active Active
- 2017-04-14 WO PCT/CN2017/080640 patent/WO2018188085A1/en unknown
- 2017-04-14 AU AU2017409368A patent/AU2017409368B2/en active Active
- 2017-04-14 BR BR112019021554-9A patent/BR112019021554B1/en active IP Right Grant
- 2017-04-14 SG SG11201908892T patent/SG11201908892TA/en unknown
- 2017-04-14 CA CA3058778A patent/CA3058778C/en active Active
- 2017-04-14 KR KR1020197030437A patent/KR102258360B1/en active IP Right Grant
- 2017-04-14 EP EP17905894.6A patent/EP3605542B1/en active Active
- 2017-04-14 JP JP2019555980A patent/JP7043515B2/en active Active
-
2019
- 2019-10-11 US US16/599,980 patent/US20200066330A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20200066330A1 (en) | 2020-02-27 |
CA3058778C (en) | 2023-02-21 |
CN110546707A (en) | 2019-12-06 |
EP3605542B1 (en) | 2021-07-21 |
JP2020517024A (en) | 2020-06-11 |
WO2018188085A1 (en) | 2018-10-18 |
AU2017409368B2 (en) | 2022-07-07 |
BR112019021554A2 (en) | 2020-05-12 |
EP3605542A4 (en) | 2020-05-20 |
CA3058778A1 (en) | 2018-10-18 |
CN110546707B (en) | 2021-10-19 |
KR102258360B1 (en) | 2021-05-31 |
EP3605542A1 (en) | 2020-02-05 |
BR112019021554B1 (en) | 2024-02-27 |
JP7043515B2 (en) | 2022-03-29 |
AU2017409368A1 (en) | 2019-10-24 |
KR20190126888A (en) | 2019-11-12 |
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