SG11201810111UA - Parity for instruction packets - Google Patents

Parity for instruction packets

Info

Publication number
SG11201810111UA
SG11201810111UA SG11201810111UA SG11201810111UA SG11201810111UA SG 11201810111U A SG11201810111U A SG 11201810111UA SG 11201810111U A SG11201810111U A SG 11201810111UA SG 11201810111U A SG11201810111U A SG 11201810111UA SG 11201810111U A SG11201810111U A SG 11201810111UA
Authority
SG
Singapore
Prior art keywords
parity
instruction
international
packet
predesignated
Prior art date
Application number
SG11201810111UA
Other languages
English (en)
Inventor
Erich James Plondke
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of SG11201810111UA publication Critical patent/SG11201810111UA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1032—Simple parity
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Error Detection And Correction (AREA)
  • Devices For Executing Special Programs (AREA)
  • Executing Machine-Instructions (AREA)
SG11201810111UA 2016-06-24 2017-06-02 Parity for instruction packets SG11201810111UA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/192,981 US10108487B2 (en) 2016-06-24 2016-06-24 Parity for instruction packets
PCT/US2017/035713 WO2017222784A1 (en) 2016-06-24 2017-06-02 Parity for instruction packets

Publications (1)

Publication Number Publication Date
SG11201810111UA true SG11201810111UA (en) 2019-01-30

Family

ID=59067918

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201810111UA SG11201810111UA (en) 2016-06-24 2017-06-02 Parity for instruction packets

Country Status (8)

Country Link
US (1) US10108487B2 (zh)
EP (1) EP3475823B1 (zh)
JP (1) JP6943890B2 (zh)
KR (1) KR102433782B1 (zh)
CN (1) CN109313594B (zh)
BR (1) BR112018076279A8 (zh)
SG (1) SG11201810111UA (zh)
WO (1) WO2017222784A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10606587B2 (en) * 2016-08-24 2020-03-31 Micron Technology, Inc. Apparatus and methods related to microcode instructions indicating instruction types
CN115081429A (zh) * 2022-07-07 2022-09-20 北京微纳星空科技有限公司 一种指令校验方法、装置、设备和存储介质
EP4400970A1 (en) * 2023-01-12 2024-07-17 NXP USA, Inc. Central processing unit system and method with improved self-checking

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4005405A (en) 1975-05-07 1977-01-25 Data General Corporation Error detection and correction in data processing systems
US6041430A (en) * 1997-11-03 2000-03-21 Sun Microsystems, Inc. Error detection and correction code for data and check code fields
US7013454B2 (en) 1999-02-22 2006-03-14 Sun Microsystems, Inc. Thread suspension system and method using trapping instructions
US6738892B1 (en) 1999-10-20 2004-05-18 Transmeta Corporation Use of enable bits to control execution of selected instructions
GB2366643B (en) * 2000-05-25 2002-05-01 Siroyan Ltd Methods of compressing instructions for processors
US6934903B1 (en) * 2001-12-17 2005-08-23 Advanced Micro Devices, Inc. Using microcode to correct ECC errors in a processor
US7240277B2 (en) 2003-09-26 2007-07-03 Texas Instruments Incorporated Memory error detection reporting
US7370230B1 (en) 2004-01-08 2008-05-06 Maxtor Corporation Methods and structure for error correction in a processor pipeline
US7302619B1 (en) * 2004-07-06 2007-11-27 Mindspeed Technologies, Inc. Error correction in a cache memory
TW200604934A (en) * 2004-07-16 2006-02-01 Benq Corp Firmware management system and method thereof
US7447948B2 (en) * 2005-11-21 2008-11-04 Intel Corporation ECC coding for high speed implementation
US20080256419A1 (en) 2007-04-13 2008-10-16 Microchip Technology Incorporated Configurable Split Storage of Error Detecting and Correcting Codes
US8135927B2 (en) * 2007-09-28 2012-03-13 International Business Machines Corporation Structure for cache function overloading
US8201067B2 (en) * 2008-02-25 2012-06-12 International Business Machines Corporation Processor error checking for instruction data
JP2009238168A (ja) * 2008-03-28 2009-10-15 Mitsubishi Electric Corp マイクロプロセッサ
US8281111B2 (en) * 2008-09-23 2012-10-02 Qualcomm Incorporated System and method to execute a linear feedback-shift instruction
WO2010100598A1 (en) * 2009-03-02 2010-09-10 Nxp B.V. Software protection
US8904115B2 (en) 2010-09-28 2014-12-02 Texas Instruments Incorporated Cache with multiple access pipelines
US8839069B2 (en) * 2011-04-08 2014-09-16 Micron Technology, Inc. Encoding and decoding techniques using low-density parity check codes
US9176739B2 (en) * 2011-08-05 2015-11-03 Cisco Technology, Inc. System and method for checking run-time consistency for sequentially and non-sequentially fetched instructions
US20140089755A1 (en) * 2012-09-27 2014-03-27 Shveta KANTAMSETTI Reliability enhancements for high speed memory - parity protection on command/address and ecc protection on data
US20140244932A1 (en) * 2013-02-27 2014-08-28 Advanced Micro Devices, Inc. Method and apparatus for caching and indexing victim pre-decode information
CN103279329B (zh) * 2013-05-08 2015-07-29 中国人民解放军国防科学技术大学 支持同步edac校验的高效取指流水线
CN103645964B (zh) * 2013-11-22 2017-05-10 中国电子科技集团公司第三十二研究所 嵌入式处理器的高速缓存容错机制

Also Published As

Publication number Publication date
US20170371739A1 (en) 2017-12-28
JP6943890B2 (ja) 2021-10-06
CN109313594A (zh) 2019-02-05
CN109313594B (zh) 2022-06-17
BR112018076279A2 (pt) 2019-03-26
EP3475823A1 (en) 2019-05-01
EP3475823B1 (en) 2022-04-20
US10108487B2 (en) 2018-10-23
KR102433782B1 (ko) 2022-08-17
JP2019519858A (ja) 2019-07-11
BR112018076279A8 (pt) 2023-01-31
KR20190021247A (ko) 2019-03-05
WO2017222784A1 (en) 2017-12-28

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SG11201810111UA (en) Parity for instruction packets