SG11201805848VA - Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture - Google Patents

Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture

Info

Publication number
SG11201805848VA
SG11201805848VA SG11201805848VA SG11201805848VA SG11201805848VA SG 11201805848V A SG11201805848V A SG 11201805848VA SG 11201805848V A SG11201805848V A SG 11201805848VA SG 11201805848V A SG11201805848V A SG 11201805848VA SG 11201805848V A SG11201805848V A SG 11201805848VA
Authority
SG
Singapore
Prior art keywords
die bond
bond pads
international
die
manufacture
Prior art date
Application number
SG11201805848VA
Inventor
Nathan Sirocka
Trismardawi Tanadi
Andrew Proescholdt
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG11201805848VA publication Critical patent/SG11201805848VA/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
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    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/06506—Wire or wire-like electrical connections between devices
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property -, Organization IIIM141101110101011111 HO 111110111011101111001111111011111110111011111 International Bureau ... .... ..Yjd (10) International Publication Number ..... ...,/ (43) International Publication Date WO 2017/123456 Al 20 July 2017 (20.07.2017) WIPO I PCT (51) International Patent Classification: AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, H01L 25/065 (2006.01) HO1L 23/538 (2006.01) BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, H01L 25/07 (2006.01) H01L 23/00 (2006.01) DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, (21) International Application Number: KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, PCT/US2017/012383 MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, (22) International Filing Date: NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, 5 January 2017 (05.01.2017) RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, (25) Filing Language: English ZA, ZM, ZW. (26) Publication Language: English (84) Designated States (unless otherwise indicated, for every (30) Priority Data: kind of regional protection available): ARIPO (BW, GH, 14/995,925 14 January 2016 (14.01.2016) US GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006 DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, (US). LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, (72) Inventors: SIROCKA, Nathan, J.; 10755 Sunrise Ridge SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, Circle, Auburn, CA 95603 (US). TANADI, Trismardawi; GW, KM, ML, MR, NE, SN, TD, TG). 9542 Harvest View Way, Sacramento, CA 95827 (US). Published: PROESCHOLDT, Andrew, D.; 11205 Platte River — with international search report (Art. 21(3)) — Court, Rancho Cordova, CA 95670 (US). — — before the expiration of the time limit for amending the = (74) Agents: PARKER, Paul, T. et al.; Perkins Coie LLP, P.O. claims and to be republished in the event of receipt of = Box 1247, Seattle, WA 98111-1247 (US). amendments (Rule 48.2(h)) for every (81) Designated States (unless otherwise indicated, kind AE, of national protection available): AG, AL, AM, DUPLICATED DIE BOND PADS AND ASSOCIATED DEVICE PACKAGES (54) Title: SEMICONDUCTOR DEVICES WITH — AND METHODS OF MANUFACTURE = = 210 -Th 214 --? 4 - --2141, ,,,. Da 1 3, = KJ- = DO5 63- - ---_ . ; 2 1 12..J--...._477 - = 250 2 -----, 225 I 1 - -2126 = w _ DQ4} (06 DDJ- = INTEGRATED CIRCUIT _ D292 C6 — NaJ DC171 232 Nt2- —la- - 232 { DO6 o---..,___ 22 . v.) ___,...--227 DO7 02- - --,_, 26 FYI 224--- ----E' 224 -- -- \"' -e' k n ii- = DM 231 227 --- --11 227-- -- IV ' 4 (SE9 '----- 2/40 Fig. 2 214d M L I (57) : Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semicon- ductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads C having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably N coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond en. ) pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.
SG11201805848VA 2016-01-14 2017-01-05 Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture SG11201805848VA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/995,925 US9875993B2 (en) 2016-01-14 2016-01-14 Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture
PCT/US2017/012383 WO2017123456A1 (en) 2016-01-14 2017-01-05 Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture

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SG11201805848VA true SG11201805848VA (en) 2018-08-30

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US (4) US9875993B2 (en)
KR (1) KR102079464B1 (en)
CN (1) CN108701686B (en)
SG (1) SG11201805848VA (en)
TW (1) TWI636539B (en)
WO (1) WO2017123456A1 (en)

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Publication number Priority date Publication date Assignee Title
US9875993B2 (en) 2016-01-14 2018-01-23 Micron Technology, Inc. Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture
EP3841612A4 (en) 2018-09-12 2021-11-03 Huawei Technologies Co., Ltd. Ic die to ic die interconnect using error correcting code and data path interleaving
TWI686924B (en) * 2018-10-18 2020-03-01 普誠科技股份有限公司 Integrated circuit and test method
US10580762B1 (en) * 2018-10-25 2020-03-03 Infineon Technologies Ag Integrated circuit (IC) chip arrangement

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US10388630B2 (en) 2019-08-20
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