SG11201705292QA - Logic block architecture for programmable gate array - Google Patents

Logic block architecture for programmable gate array

Info

Publication number
SG11201705292QA
SG11201705292QA SG11201705292QA SG11201705292QA SG11201705292QA SG 11201705292Q A SG11201705292Q A SG 11201705292QA SG 11201705292Q A SG11201705292Q A SG 11201705292QA SG 11201705292Q A SG11201705292Q A SG 11201705292QA SG 11201705292Q A SG11201705292Q A SG 11201705292QA
Authority
SG
Singapore
Prior art keywords
programmable gate
gate array
logic block
block architecture
architecture
Prior art date
Application number
SG11201705292QA
Inventor
Laurent Rouge
Julien Eydoux
Serge Alexandre Marthely
Original Assignee
Menta
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Menta filed Critical Menta
Publication of SG11201705292QA publication Critical patent/SG11201705292QA/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17758—Structural details of configuration resources for speeding up configuration or reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
SG11201705292QA 2015-10-15 2016-10-07 Logic block architecture for programmable gate array SG11201705292QA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP15306640.2A EP3157171B1 (en) 2015-10-15 2015-10-15 Logic block architecture for programmable gate array
PCT/EP2016/074075 WO2017063956A1 (en) 2015-10-15 2016-10-07 Logic block architecture for programmable gate array

Publications (1)

Publication Number Publication Date
SG11201705292QA true SG11201705292QA (en) 2017-07-28

Family

ID=54360379

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201705292QA SG11201705292QA (en) 2015-10-15 2016-10-07 Logic block architecture for programmable gate array

Country Status (11)

Country Link
US (1) US20180269880A1 (en)
EP (1) EP3157171B1 (en)
JP (1) JP2018538704A (en)
KR (1) KR20180116117A (en)
CN (1) CN107925410A (en)
CA (1) CA2973175A1 (en)
IL (1) IL253181A0 (en)
RU (1) RU2017129271A (en)
SG (1) SG11201705292QA (en)
TW (1) TW201729083A (en)
WO (1) WO2017063956A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI695250B (en) * 2018-11-28 2020-06-01 大陸商北京集創北方科技股份有限公司 Lookup table configuration method capable of reducing the number of multiplexers and information processing device using the same
CN113904677B (en) * 2021-10-11 2022-07-01 北京汤谷软件技术有限公司 Look-up table circuit capable of customizing multiple inputs and novel array structure of FPGA
CN113971159B (en) * 2021-10-28 2024-02-20 山东芯慧微电子科技有限公司 Programmable logic block based on improved lookup table structure

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5414377A (en) 1992-12-21 1995-05-09 Xilinx, Inc. Logic block with look-up table for configuration and memory
US5889413A (en) 1996-11-22 1999-03-30 Xilinx, Inc. Lookup tables which double as shift registers
US6556042B1 (en) * 2002-02-20 2003-04-29 Xilinx, Inc. FPGA with improved structure for implementing large multiplexers
US6798240B1 (en) 2003-01-24 2004-09-28 Altera Corporation Logic circuitry with shared lookup table
US7330052B2 (en) * 2005-09-22 2008-02-12 Altera Corporation Area efficient fractureable logic elements
WO2009100564A1 (en) * 2008-01-30 2009-08-20 Agate Logic (Beijing), Inc. An integrated circuit with improved logic cells
FR2972566B1 (en) 2011-03-11 2013-03-15 Sas Adicsys Design MONO-CHIP SYSTEM COMPRISING A SYNTHETICABLE PROGRAMMABLE HEART AND A METHOD OF MANUFACTURING SUCH A SYSTEM

Also Published As

Publication number Publication date
WO2017063956A1 (en) 2017-04-20
EP3157171A1 (en) 2017-04-19
RU2017129271A (en) 2019-02-18
KR20180116117A (en) 2018-10-24
JP2018538704A (en) 2018-12-27
CN107925410A (en) 2018-04-17
US20180269880A1 (en) 2018-09-20
CA2973175A1 (en) 2017-04-20
EP3157171B1 (en) 2020-06-03
IL253181A0 (en) 2017-08-31
TW201729083A (en) 2017-08-16

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