FR2972566B1 - MONO-CHIP SYSTEM COMPRISING A SYNTHETICABLE PROGRAMMABLE HEART AND A METHOD OF MANUFACTURING SUCH A SYSTEM - Google Patents

MONO-CHIP SYSTEM COMPRISING A SYNTHETICABLE PROGRAMMABLE HEART AND A METHOD OF MANUFACTURING SUCH A SYSTEM

Info

Publication number
FR2972566B1
FR2972566B1 FR1152017A FR1152017A FR2972566B1 FR 2972566 B1 FR2972566 B1 FR 2972566B1 FR 1152017 A FR1152017 A FR 1152017A FR 1152017 A FR1152017 A FR 1152017A FR 2972566 B1 FR2972566 B1 FR 2972566B1
Authority
FR
France
Prior art keywords
syntheticable
mono
manufacturing
chip
programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1152017A
Other languages
French (fr)
Other versions
FR2972566A1 (en
Inventor
Gil Peer Schmitt
Philippe Robert Diehl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
S.A.S ADICSYS, FR
Original Assignee
Sas ADICSYS DESIGN
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sas ADICSYS DESIGN filed Critical Sas ADICSYS DESIGN
Priority to FR1152017A priority Critical patent/FR2972566B1/en
Priority to PCT/EP2012/053271 priority patent/WO2012123243A1/en
Publication of FR2972566A1 publication Critical patent/FR2972566A1/en
Application granted granted Critical
Publication of FR2972566B1 publication Critical patent/FR2972566B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Stored Programmes (AREA)

Abstract

The invention relates to a system-on-a-chip (200, 408) comprising at least one programmable synthesizable core PSC (208, 209) and a dedicated block (201, 202, 203, 207). The PSC core and the dedicated block are synthesized together from a hardware description-language (HDL) model of the dedicated block (201, 202, 203, 207), as well as from a hardware description-language (HDL) model of the PSC core (306, 402) associated with a default configuration file (305, 401).
FR1152017A 2011-03-11 2011-03-11 MONO-CHIP SYSTEM COMPRISING A SYNTHETICABLE PROGRAMMABLE HEART AND A METHOD OF MANUFACTURING SUCH A SYSTEM Active FR2972566B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1152017A FR2972566B1 (en) 2011-03-11 2011-03-11 MONO-CHIP SYSTEM COMPRISING A SYNTHETICABLE PROGRAMMABLE HEART AND A METHOD OF MANUFACTURING SUCH A SYSTEM
PCT/EP2012/053271 WO2012123243A1 (en) 2011-03-11 2012-02-27 System-on-a-chip including a programmable synthesizable core, and method for making such a system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1152017A FR2972566B1 (en) 2011-03-11 2011-03-11 MONO-CHIP SYSTEM COMPRISING A SYNTHETICABLE PROGRAMMABLE HEART AND A METHOD OF MANUFACTURING SUCH A SYSTEM

Publications (2)

Publication Number Publication Date
FR2972566A1 FR2972566A1 (en) 2012-09-14
FR2972566B1 true FR2972566B1 (en) 2013-03-15

Family

ID=44202116

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1152017A Active FR2972566B1 (en) 2011-03-11 2011-03-11 MONO-CHIP SYSTEM COMPRISING A SYNTHETICABLE PROGRAMMABLE HEART AND A METHOD OF MANUFACTURING SUCH A SYSTEM

Country Status (2)

Country Link
FR (1) FR2972566B1 (en)
WO (1) WO2012123243A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3157172B1 (en) 2015-10-15 2018-11-28 Menta System and method for testing and configuration of an fpga
EP3157171B1 (en) 2015-10-15 2020-06-03 Menta Logic block architecture for programmable gate array
EP3355196A1 (en) 2017-01-27 2018-08-01 Menta Fpga and method of operation
EP3376669A1 (en) 2017-03-17 2018-09-19 Menta Fpga and method of fpga programming
CN112948320B (en) 2019-12-11 2024-01-16 瑞昱半导体股份有限公司 chip with memory
WO2022149080A1 (en) 2021-01-08 2022-07-14 Menta System on chip architecture, interposer, fpga and method of design

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5915123A (en) * 1997-10-31 1999-06-22 Silicon Spice Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
US7275232B2 (en) * 2005-04-01 2007-09-25 Altera Corporation Methods for producing equivalent field-programmable gate arrays and structured application specific integrated circuits
US7451426B2 (en) * 2005-07-07 2008-11-11 Lsi Corporation Application specific configurable logic IP

Also Published As

Publication number Publication date
WO2012123243A1 (en) 2012-09-20
FR2972566A1 (en) 2012-09-14

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