SG11201702791TA - Flip-flop circuit, method of controlling a flip-flop circuit and memory device - Google Patents
Flip-flop circuit, method of controlling a flip-flop circuit and memory deviceInfo
- Publication number
- SG11201702791TA SG11201702791TA SG11201702791TA SG11201702791TA SG11201702791TA SG 11201702791T A SG11201702791T A SG 11201702791TA SG 11201702791T A SG11201702791T A SG 11201702791TA SG 11201702791T A SG11201702791T A SG 11201702791TA SG 11201702791T A SG11201702791T A SG 11201702791TA
- Authority
- SG
- Singapore
- Prior art keywords
- flip
- flop circuit
- controlling
- memory device
- flop
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1659—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1693—Timing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SG11201702791TA SG11201702791TA (en) | 2014-10-15 | 2015-10-15 | Flip-flop circuit, method of controlling a flip-flop circuit and memory device |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SG10201406633X | 2014-10-15 | ||
| PCT/SG2015/050390 WO2016060617A1 (en) | 2014-10-15 | 2015-10-15 | Flip-flop circuit, method of controlling a flip-flop circuit and memory device |
| SG11201702791TA SG11201702791TA (en) | 2014-10-15 | 2015-10-15 | Flip-flop circuit, method of controlling a flip-flop circuit and memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11201702791TA true SG11201702791TA (en) | 2017-05-30 |
Family
ID=55747028
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11201702791TA SG11201702791TA (en) | 2014-10-15 | 2015-10-15 | Flip-flop circuit, method of controlling a flip-flop circuit and memory device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US10043563B2 (en) |
| SG (1) | SG11201702791TA (en) |
| WO (1) | WO2016060617A1 (en) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170263299A1 (en) * | 2016-03-11 | 2017-09-14 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| DE102016121696A1 (en) | 2016-11-11 | 2018-05-17 | Tesat-Spacecom Gmbh & Co.Kg | Tristate-capable cross-flow-free output buffer |
| US10348306B2 (en) * | 2017-03-09 | 2019-07-09 | University Of Utah Research Foundation | Resistive random access memory based multiplexers and field programmable gate arrays |
| US10510401B2 (en) * | 2017-05-22 | 2019-12-17 | Taiwan Semicondutor Manufacturing Company Limited | Semiconductor memory device using shared data line for read/write operation |
| US20200144293A1 (en) * | 2017-09-12 | 2020-05-07 | Intel Corporation | Ferroelectric field effect transistors (fefets) having ambipolar channels |
| US10777566B2 (en) | 2017-11-10 | 2020-09-15 | Macronix International Co., Ltd. | 3D array arranged for memory and in-memory sum-of-products operations |
| US10957392B2 (en) | 2018-01-17 | 2021-03-23 | Macronix International Co., Ltd. | 2D and 3D sum-of-products array for neuromorphic computing system |
| US10719296B2 (en) | 2018-01-17 | 2020-07-21 | Macronix International Co., Ltd. | Sum-of-products accelerator array |
| US11138497B2 (en) | 2018-07-17 | 2021-10-05 | Macronix International Co., Ltd | In-memory computing devices for neural networks |
| US11450385B2 (en) * | 2018-09-20 | 2022-09-20 | University Of Utah Research Foundation | Digital RRAM-based convolutional block |
| US11636325B2 (en) | 2018-10-24 | 2023-04-25 | Macronix International Co., Ltd. | In-memory data pooling for machine learning |
| US11562229B2 (en) | 2018-11-30 | 2023-01-24 | Macronix International Co., Ltd. | Convolution accelerator using in-memory computation |
| US11934480B2 (en) | 2018-12-18 | 2024-03-19 | Macronix International Co., Ltd. | NAND block architecture for in-memory multiply-and-accumulate operations |
| US11119674B2 (en) * | 2019-02-19 | 2021-09-14 | Macronix International Co., Ltd. | Memory devices and methods for operating the same |
| US10783963B1 (en) | 2019-03-08 | 2020-09-22 | Macronix International Co., Ltd. | In-memory computation device with inter-page and intra-page data circuits |
| US11132176B2 (en) | 2019-03-20 | 2021-09-28 | Macronix International Co., Ltd. | Non-volatile computing method in flash memory |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3471838A (en) | 1965-06-21 | 1969-10-07 | Magnavox Co | Simultaneous read and write memory configuration |
| EP0475588B1 (en) * | 1990-08-17 | 1996-06-26 | STMicroelectronics, Inc. | A semiconductor memory with inhibited test mode entry during power-up |
| JP4543632B2 (en) * | 2003-08-07 | 2010-09-15 | 日本電気株式会社 | Liquid crystal display device and liquid crystal display device driving method |
| JP5201487B2 (en) * | 2007-12-06 | 2013-06-05 | 日本電気株式会社 | Nonvolatile latch circuit |
| WO2010007173A1 (en) | 2008-07-17 | 2010-01-21 | Universite Paris Sud (Paris 11) | A new sense amplifier circuit |
| US8400822B2 (en) | 2010-03-22 | 2013-03-19 | Qualcomm Incorporated | Multi-port non-volatile memory that includes a resistive memory element |
| US8531907B2 (en) | 2011-01-28 | 2013-09-10 | Infineon Technologies Ag | Semiconductor memory device and method |
| TWI546784B (en) * | 2014-04-30 | 2016-08-21 | 聯詠科技股份有限公司 | Gate driving circuit and driving method thereof |
-
2015
- 2015-10-15 SG SG11201702791TA patent/SG11201702791TA/en unknown
- 2015-10-15 US US15/517,745 patent/US10043563B2/en not_active Expired - Fee Related
- 2015-10-15 WO PCT/SG2015/050390 patent/WO2016060617A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| US20170243624A1 (en) | 2017-08-24 |
| US10043563B2 (en) | 2018-08-07 |
| WO2016060617A1 (en) | 2016-04-21 |
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