SG10202006562UA - Three-dimensional semiconductor devices and methods of fabricating the same - Google Patents

Three-dimensional semiconductor devices and methods of fabricating the same

Info

Publication number
SG10202006562UA
SG10202006562UA SG10202006562UA SG10202006562UA SG10202006562UA SG 10202006562U A SG10202006562U A SG 10202006562UA SG 10202006562U A SG10202006562U A SG 10202006562UA SG 10202006562U A SG10202006562U A SG 10202006562UA SG 10202006562U A SG10202006562U A SG 10202006562UA
Authority
SG
Singapore
Prior art keywords
fabricating
methods
same
semiconductor devices
dimensional semiconductor
Prior art date
Application number
SG10202006562UA
Inventor
Kim Sunggil
Kim Sungjin
Kim Seulye
Kim Junghwan
Kim Chanhyoung
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10202006562UA publication Critical patent/SG10202006562UA/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
SG10202006562UA 2019-08-21 2020-07-08 Three-dimensional semiconductor devices and methods of fabricating the same SG10202006562UA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020190102564A KR20210024318A (en) 2019-08-21 2019-08-21 Three-dimensional semiconductor devices and methods of fabricating the same

Publications (1)

Publication Number Publication Date
SG10202006562UA true SG10202006562UA (en) 2021-03-30

Family

ID=74495872

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10202006562UA SG10202006562UA (en) 2019-08-21 2020-07-08 Three-dimensional semiconductor devices and methods of fabricating the same

Country Status (6)

Country Link
US (2) US11387253B2 (en)
JP (1) JP2021034717A (en)
KR (1) KR20210024318A (en)
CN (1) CN112420723A (en)
DE (1) DE102020121073A1 (en)
SG (1) SG10202006562UA (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210024318A (en) 2019-08-21 2021-03-05 삼성전자주식회사 Three-dimensional semiconductor devices and methods of fabricating the same
JP2022534308A (en) 2019-10-22 2022-07-28 長江存儲科技有限責任公司 Three-dimensional memory device with pocket structure in memory string and method
JP2022139554A (en) * 2021-03-12 2022-09-26 セイコーエプソン株式会社 Electro-optical device and electronic apparatus
TWI789295B (en) * 2022-04-27 2023-01-01 旺宏電子股份有限公司 Memory device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101825534B1 (en) * 2011-02-07 2018-02-06 삼성전자주식회사 Three Dimensional Semiconductor Memory Device
US9425210B2 (en) * 2014-08-13 2016-08-23 SK Hynix Inc. Double-source semiconductor device
US9362298B2 (en) 2014-09-11 2016-06-07 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and manufacturing method thereof
KR20160080365A (en) 2014-12-29 2016-07-08 에스케이하이닉스 주식회사 Electronic device and manufacturing method thereof
US9455261B1 (en) 2015-07-10 2016-09-27 Micron Technology, Inc. Integrated structures
KR102581032B1 (en) 2015-12-08 2023-09-22 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method thereof
KR102589594B1 (en) * 2016-03-02 2023-10-17 삼성전자주식회사 Semiconductor memory device
US9741737B1 (en) 2016-04-15 2017-08-22 Micron Technology, Inc. Integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material
US10121794B2 (en) 2016-06-20 2018-11-06 Sandisk Technologies Llc Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof
US9824966B1 (en) * 2016-08-12 2017-11-21 Sandisk Technologies Llc Three-dimensional memory device containing a lateral source contact and method of making the same
KR102629454B1 (en) 2016-08-22 2024-01-26 에스케이하이닉스 주식회사 Semiconductor memory device
US10361218B2 (en) * 2017-02-28 2019-07-23 Toshiba Memory Corporation Semiconductor device and method for manufacturing same
KR20180129457A (en) 2017-05-26 2018-12-05 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method thereof
US10224340B2 (en) * 2017-06-19 2019-03-05 Sandisk Technologies Llc Three-dimensional memory device having discrete direct source strap contacts and method of making thereof
US10438964B2 (en) 2017-06-26 2019-10-08 Sandisk Technologies Llc Three-dimensional memory device having direct source contact and metal oxide blocking dielectric and method of making thereof
US10199359B1 (en) 2017-08-04 2019-02-05 Sandisk Technologies Llc Three-dimensional memory device employing direct source contact and hole current detection and method of making the same
JP2019041054A (en) 2017-08-28 2019-03-14 東芝メモリ株式会社 Semiconductor device
JP6842386B2 (en) 2017-08-31 2021-03-17 キオクシア株式会社 Semiconductor device
JP2019054162A (en) 2017-09-15 2019-04-04 東芝メモリ株式会社 Method for manufacturing storage device and storage device
US10720445B1 (en) * 2018-02-08 2020-07-21 Sandisk Technologies Llc Three-dimensional memory device having nitrided direct source strap contacts and method of making thereof
US10629613B1 (en) * 2018-11-20 2020-04-21 Sandisk Technologies Llc Three-dimensional memory device having vertical semiconductor channels including source-side boron-doped pockets and methods of making the same
KR20210024318A (en) 2019-08-21 2021-03-05 삼성전자주식회사 Three-dimensional semiconductor devices and methods of fabricating the same

Also Published As

Publication number Publication date
US11387253B2 (en) 2022-07-12
US11792993B2 (en) 2023-10-17
KR20210024318A (en) 2021-03-05
DE102020121073A1 (en) 2021-02-25
US20220352203A1 (en) 2022-11-03
JP2021034717A (en) 2021-03-01
US20210057445A1 (en) 2021-02-25
CN112420723A (en) 2021-02-26

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