SG10201911591QA - Vertical semiconductor device and fabrication method thereof - Google Patents
Vertical semiconductor device and fabrication method thereofInfo
- Publication number
- SG10201911591QA SG10201911591QA SG10201911591QA SG10201911591QA SG10201911591QA SG 10201911591Q A SG10201911591Q A SG 10201911591QA SG 10201911591Q A SG10201911591Q A SG 10201911591QA SG 10201911591Q A SG10201911591Q A SG 10201911591QA SG 10201911591Q A SG10201911591Q A SG 10201911591QA
- Authority
- SG
- Singapore
- Prior art keywords
- semiconductor device
- fabrication method
- vertical semiconductor
- vertical
- fabrication
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020190030113A KR20200110052A (en) | 2019-03-15 | 2019-03-15 | Vertical semiconductor device and manufacturing method of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG10201911591QA true SG10201911591QA (en) | 2020-10-29 |
Family
ID=72241192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG10201911591QA SG10201911591QA (en) | 2019-03-15 | 2019-12-03 | Vertical semiconductor device and fabrication method thereof |
Country Status (5)
| Country | Link |
|---|---|
| US (3) | US11088160B2 (en) |
| KR (1) | KR20200110052A (en) |
| CN (1) | CN111696988B (en) |
| DE (1) | DE102019219549A1 (en) |
| SG (1) | SG10201911591QA (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20210012331A (en) | 2019-07-24 | 2021-02-03 | 에스케이하이닉스 주식회사 | Semiconductor memory device and manufacturing method thereof |
| KR102640175B1 (en) * | 2019-11-18 | 2024-02-23 | 삼성전자주식회사 | Semiconductor devices |
| KR20210147363A (en) * | 2020-05-28 | 2021-12-07 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method of the same |
| US11792988B2 (en) | 2021-08-09 | 2023-10-17 | Sandisk Technologies Llc | Three-dimensional memory device with separated contact regions and methods for forming the same |
| WO2023018456A2 (en) * | 2021-08-09 | 2023-02-16 | Sandisk Technologies Llc | Three-dimensional memory device with separated contact regions and methods for forming the same |
| US11889694B2 (en) | 2021-08-09 | 2024-01-30 | Sandisk Technologies Llc | Three-dimensional memory device with separated contact regions and methods for forming the same |
| US20230063178A1 (en) * | 2021-08-30 | 2023-03-02 | Micron Technology, Inc. | Microelectronic devices including stair step structures, and related electronic systems and methods |
| US20230369100A1 (en) * | 2022-05-12 | 2023-11-16 | Macronix International Co., Ltd. | 3d memory structure and method of forming the same |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5330017B2 (en) | 2009-02-17 | 2013-10-30 | 株式会社東芝 | Nonvolatile semiconductor memory device and manufacturing method thereof |
| KR101805769B1 (en) * | 2010-11-29 | 2017-12-08 | 삼성전자주식회사 | Methods of fabricating three dimensional semiconductor memory devices |
| KR20130072522A (en) * | 2011-12-22 | 2013-07-02 | 에스케이하이닉스 주식회사 | Three dimension non-volatile memory device and method for manufacturing the same |
| KR101974352B1 (en) * | 2012-12-07 | 2019-05-02 | 삼성전자주식회사 | Method of Fabricating Semiconductor Devices Having Vertical Cells and Semiconductor Devices Fabricated Thereby |
| US8759217B1 (en) | 2013-01-07 | 2014-06-24 | Macronix International Co., Ltd. | Method for forming interlayer connectors to a stack of conductive layers |
| KR102568886B1 (en) | 2015-11-16 | 2023-08-22 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method of the same |
| US9905514B2 (en) | 2016-04-11 | 2018-02-27 | Micron Technology, Inc. | Semiconductor device structures including staircase structures, and related methods and electronic systems |
| KR102550571B1 (en) * | 2016-05-02 | 2023-07-04 | 에스케이하이닉스 주식회사 | Semiconductor device and method of manufacturing the same |
| KR102415206B1 (en) * | 2016-06-27 | 2022-07-01 | 에스케이하이닉스 주식회사 | Semiconductor device |
-
2019
- 2019-03-15 KR KR1020190030113A patent/KR20200110052A/en not_active Application Discontinuation
- 2019-09-13 US US16/570,089 patent/US11088160B2/en active Active
- 2019-12-03 SG SG10201911591QA patent/SG10201911591QA/en unknown
- 2019-12-13 DE DE102019219549.0A patent/DE102019219549A1/en active Pending
- 2019-12-16 CN CN201911291878.4A patent/CN111696988B/en active Active
-
2021
- 2021-07-06 US US17/368,630 patent/US11917820B2/en active Active
-
2023
- 2023-10-17 US US18/488,751 patent/US20240049464A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CN111696988A (en) | 2020-09-22 |
| US11917820B2 (en) | 2024-02-27 |
| DE102019219549A1 (en) | 2020-09-17 |
| US20210335800A1 (en) | 2021-10-28 |
| CN111696988B (en) | 2023-11-07 |
| US20200295028A1 (en) | 2020-09-17 |
| KR20200110052A (en) | 2020-09-23 |
| US11088160B2 (en) | 2021-08-10 |
| US20240049464A1 (en) | 2024-02-08 |
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