SG10201804812UA - Semiconductor packages and methods of manufacturing same - Google Patents

Semiconductor packages and methods of manufacturing same

Info

Publication number
SG10201804812UA
SG10201804812UA SG10201804812UA SG10201804812UA SG10201804812UA SG 10201804812U A SG10201804812U A SG 10201804812UA SG 10201804812U A SG10201804812U A SG 10201804812UA SG 10201804812U A SG10201804812U A SG 10201804812UA SG 10201804812U A SG10201804812U A SG 10201804812UA
Authority
SG
Singapore
Prior art keywords
interposer
package substrate
protrusions
package
methods
Prior art date
Application number
SG10201804812UA
Inventor
Kim Sang-Uk
Kim Sunchul
Seol Jinkyeong
Wook Jang Byoung
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201804812UA publication Critical patent/SG10201804812UA/en

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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor package and a method manufacturing the same are disclosed. At least one semiconductor chip is mounted on a package substrate. An insulative mold layer is formed at sides of the semiconductor chip having at least one recess in a region in which conductive connection members are formed, the recess defining one or more protrusions within the mold layer. An interposer is positioned on the protrusions with the conductive connection members connecting and providing electrical connections between conductive pads on the upper surface of the package and conductive pads on the lower surface of the package substrate. The protrusions may position the interposer in the vertical direction by defining the vertical spacing between the lower surface of the interposer and the upper surface of the package substrate. The protrusions may also position the interposer in one or more horizontal directions and/or prevent substantial movement during connecting of the interposer to the package substrate. An under-fill resin layer may be injected into remaining space between the interposer and the package substrate. FIG. 2
SG10201804812UA 2017-07-17 2018-06-06 Semiconductor packages and methods of manufacturing same SG10201804812UA (en)

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KR1020170090453A KR102358323B1 (en) 2017-07-17 2017-07-17 Semiconductor package
US15/956,414 US10510672B2 (en) 2017-07-17 2018-04-18 Semiconductor packages and methods of manufacturing same

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JP (1) JP7160588B2 (en)
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KR20190008723A (en) 2019-01-25
KR102358323B1 (en) 2022-02-04
JP7160588B2 (en) 2022-10-25
CN109273368B (en) 2023-07-21
JP2019021923A (en) 2019-02-07
US10510672B2 (en) 2019-12-17
US20190019758A1 (en) 2019-01-17
CN109273368A (en) 2019-01-25

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