SG10201500104XA - Method, Computer System and Computer-Readable Storage Medium for Creating a Layout of an Integrated Circuit - Google Patents

Method, Computer System and Computer-Readable Storage Medium for Creating a Layout of an Integrated Circuit

Info

Publication number
SG10201500104XA
SG10201500104XA SG10201500104XA SG10201500104XA SG10201500104XA SG 10201500104X A SG10201500104X A SG 10201500104XA SG 10201500104X A SG10201500104X A SG 10201500104XA SG 10201500104X A SG10201500104X A SG 10201500104XA SG 10201500104X A SG10201500104X A SG 10201500104XA
Authority
SG
Singapore
Prior art keywords
computer
layout
creating
storage medium
integrated circuit
Prior art date
Application number
SG10201500104XA
Other languages
English (en)
Inventor
Hensel Ulrich
Mann Rainer
Original Assignee
Globalfoundries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globalfoundries Inc filed Critical Globalfoundries Inc
Publication of SG10201500104XA publication Critical patent/SG10201500104XA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
SG10201500104XA 2014-01-28 2015-01-07 Method, Computer System and Computer-Readable Storage Medium for Creating a Layout of an Integrated Circuit SG10201500104XA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/166,044 US9613175B2 (en) 2014-01-28 2014-01-28 Method, computer system and computer-readable storage medium for creating a layout of an integrated circuit

Publications (1)

Publication Number Publication Date
SG10201500104XA true SG10201500104XA (en) 2015-08-28

Family

ID=53523139

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201500104XA SG10201500104XA (en) 2014-01-28 2015-01-07 Method, Computer System and Computer-Readable Storage Medium for Creating a Layout of an Integrated Circuit

Country Status (6)

Country Link
US (1) US9613175B2 (zh)
KR (1) KR101645633B1 (zh)
CN (1) CN104809264B (zh)
DE (1) DE102015200694A1 (zh)
SG (1) SG10201500104XA (zh)
TW (1) TWI608371B (zh)

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US9613175B2 (en) * 2014-01-28 2017-04-04 Globalfoundries Inc. Method, computer system and computer-readable storage medium for creating a layout of an integrated circuit
US9747404B2 (en) * 2015-07-23 2017-08-29 United Microelectronics Corp. Method for optimizing an integrated circuit layout design
US10169523B2 (en) * 2015-08-27 2019-01-01 International Business Machines Corporation Timing constraints formulation for highly replicated design modules
US9824174B2 (en) * 2015-09-11 2017-11-21 Qualcomm Incorporated Power-density-based clock cell spacing
US9886544B2 (en) 2016-02-23 2018-02-06 Taiwan Semiconductor Manufacturing Co., Ltd. Layout checking system and method
WO2017151681A1 (en) * 2016-02-29 2017-09-08 Synopsys, Inc. Creating and reusing customizable structured interconnects
US10089433B2 (en) * 2016-05-03 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method for triple-patterning friendly placement
US10312192B2 (en) 2016-06-02 2019-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit having staggered conductive features
US10366200B2 (en) 2016-09-07 2019-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. System for and method of manufacturing a layout design of an integrated circuit
KR102499036B1 (ko) * 2017-09-22 2023-02-13 삼성전자주식회사 임계 치수 측정 시스템 및 임계 치수 측정 방법
US10423752B2 (en) 2017-09-29 2019-09-24 International Business Machines Corporation Semiconductor package metal shadowing checks
US10423751B2 (en) 2017-09-29 2019-09-24 International Business Machines Corporation Semiconductor package floating metal checks
KR102545141B1 (ko) * 2017-12-01 2023-06-20 삼성전자주식회사 반도체 소자 및 그의 제조 방법
US10810346B2 (en) * 2018-09-28 2020-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Static voltage drop (SIR) violation prediction systems and methods
US10853553B1 (en) * 2019-06-07 2020-12-01 Avatar Integrated Systems, Inc. Vias with multiconnection via structures
CN112380802B (zh) * 2019-07-29 2024-04-19 星宸科技股份有限公司 集成电路的半自动化设计的方法以及系统
CN112668271A (zh) 2019-10-15 2021-04-16 台湾积体电路制造股份有限公司 集成电路器件设计方法和系统
CN112016263B (zh) * 2020-10-22 2021-01-29 创意电子(南京)有限公司 一种实现数据延时均衡的方法

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DE10255849B4 (de) 2002-11-29 2006-06-14 Advanced Micro Devices, Inc., Sunnyvale Verbesserte Drain/Source-Erweiterungsstruktur eines Feldeffekttransistors mit dotierten Seitenwandabstandselementen mit hoher Permittivität und Verfahren zu deren Herstellung
TW200418113A (en) 2003-03-04 2004-09-16 Macronix Int Co Ltd Method and system for automatically forming the semiconductor test key layout
JP2006301837A (ja) * 2005-04-19 2006-11-02 Nec Electronics Corp マクロ内配線を考慮したネットリストを用いて遅延計算を行う設計方法及びそのネットリストの作成プログラム
US7406671B2 (en) * 2005-10-05 2008-07-29 Lsi Corporation Method for performing design rule check of integrated circuit
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US8453089B2 (en) * 2011-10-03 2013-05-28 Globalfoundries Singapore Pte. Ltd. Method and apparatus for pattern adjusted timing via pattern matching
US8769475B2 (en) * 2011-10-31 2014-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method, system and software for accessing design rules and library of design features while designing semiconductor device layout
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KR101937851B1 (ko) * 2012-06-27 2019-04-10 삼성전자 주식회사 반도체 집적 회로, 그 설계 방법 및 제조방법
US9613175B2 (en) * 2014-01-28 2017-04-04 Globalfoundries Inc. Method, computer system and computer-readable storage medium for creating a layout of an integrated circuit

Also Published As

Publication number Publication date
KR101645633B1 (ko) 2016-08-05
KR20150089938A (ko) 2015-08-05
US20150213185A1 (en) 2015-07-30
TWI608371B (zh) 2017-12-11
CN104809264A (zh) 2015-07-29
DE102015200694A1 (de) 2015-07-30
TW201531873A (zh) 2015-08-16
CN104809264B (zh) 2018-08-10
US9613175B2 (en) 2017-04-04

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