SG10201404749QA - Adhesion layer for through silicon via metallization - Google Patents

Adhesion layer for through silicon via metallization

Info

Publication number
SG10201404749QA
SG10201404749QA SG10201404749QA SG10201404749QA SG10201404749QA SG 10201404749Q A SG10201404749Q A SG 10201404749QA SG 10201404749Q A SG10201404749Q A SG 10201404749QA SG 10201404749Q A SG10201404749Q A SG 10201404749QA SG 10201404749Q A SG10201404749Q A SG 10201404749QA
Authority
SG
Singapore
Prior art keywords
adhesion layer
silicon via
via metallization
metallization
silicon
Prior art date
Application number
SG10201404749QA
Inventor
Artur Kolics
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp filed Critical Lam Res Corp
Publication of SG10201404749QA publication Critical patent/SG10201404749QA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
SG10201404749QA 2013-08-13 2014-08-08 Adhesion layer for through silicon via metallization SG10201404749QA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/966,168 US8980746B2 (en) 2013-08-13 2013-08-13 Adhesion layer for through silicon via metallization

Publications (1)

Publication Number Publication Date
SG10201404749QA true SG10201404749QA (en) 2015-03-30

Family

ID=52467137

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201404749QA SG10201404749QA (en) 2013-08-13 2014-08-08 Adhesion layer for through silicon via metallization

Country Status (5)

Country Link
US (1) US8980746B2 (en)
KR (1) KR102383378B1 (en)
CN (1) CN104377162B (en)
SG (1) SG10201404749QA (en)
TW (1) TWI638423B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10352991B2 (en) 2015-07-21 2019-07-16 Fermi Research Alliance, Llc Edgeless large area ASIC
US10075657B2 (en) 2015-07-21 2018-09-11 Fermi Research Alliance, Llc Edgeless large area camera system
US9899260B2 (en) 2016-01-21 2018-02-20 Micron Technology, Inc. Method for fabricating a semiconductor device
US9881833B1 (en) * 2016-10-26 2018-01-30 International Business Machines Corporation Barrier planarization for interconnect metallization
US11133218B1 (en) * 2020-01-23 2021-09-28 Tae Young Lee Semiconductor apparatus having through silicon via structure and manufacturing method thereof

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6075291A (en) * 1998-02-27 2000-06-13 Micron Technology, Inc. Structure for contact formation using a silicon-germanium alloy
US7084460B2 (en) * 2003-11-03 2006-08-01 International Business Machines Corporation Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates
US7368379B2 (en) * 2005-08-04 2008-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer interconnect structure for semiconductor devices
US7276796B1 (en) * 2006-03-15 2007-10-02 International Business Machines Corporation Formation of oxidation-resistant seed layer for interconnect applications
US8232647B2 (en) * 2008-02-21 2012-07-31 International Business Machines Corporation Structure and process for metallization in high aspect ratio features
US20100090342A1 (en) 2008-10-15 2010-04-15 Hui-Lin Chang Metal Line Formation Through Silicon/Germanium Soaking
EP2500930A4 (en) * 2009-11-09 2013-05-22 Mitsubishi Gas Chemical Co Etching liquid for etching silicon substrate rear surface in through silicon via process and method for manufacturing semiconductor chip having through silicon via using the etching liquid
CN102468220B (en) * 2010-11-08 2013-12-25 中国科学院微电子研究所 Metal interconnection structure and forming method thereof
US8487425B2 (en) * 2011-06-23 2013-07-16 International Business Machines Corporation Optimized annular copper TSV
US8753975B1 (en) * 2013-02-01 2014-06-17 Globalfoundries Inc. Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting device

Also Published As

Publication number Publication date
KR102383378B1 (en) 2022-04-05
CN104377162A (en) 2015-02-25
CN104377162B (en) 2017-05-10
KR20150020100A (en) 2015-02-25
TWI638423B (en) 2018-10-11
US20150050808A1 (en) 2015-02-19
US8980746B2 (en) 2015-03-17
TW201528426A (en) 2015-07-16

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