SE9701874D0 - AdressjusterbartRAM-minne (eller shiftminne) - Google Patents
AdressjusterbartRAM-minne (eller shiftminne)Info
- Publication number
- SE9701874D0 SE9701874D0 SE9701874A SE9701874A SE9701874D0 SE 9701874 D0 SE9701874 D0 SE 9701874D0 SE 9701874 A SE9701874 A SE 9701874A SE 9701874 A SE9701874 A SE 9701874A SE 9701874 D0 SE9701874 D0 SE 9701874D0
- Authority
- SE
- Sweden
- Prior art keywords
- memory
- data element
- data elements
- data
- deletion
- Prior art date
Links
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Memory System (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9701874A SE9701874D0 (sv) | 1997-05-21 | 1997-05-21 | AdressjusterbartRAM-minne (eller shiftminne) |
PCT/SE1998/001054 WO1998056005A2 (en) | 1997-05-21 | 1998-06-03 | Method and device for data sequence manipulation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9701874A SE9701874D0 (sv) | 1997-05-21 | 1997-05-21 | AdressjusterbartRAM-minne (eller shiftminne) |
Publications (1)
Publication Number | Publication Date |
---|---|
SE9701874D0 true SE9701874D0 (sv) | 1997-05-21 |
Family
ID=20407008
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE9701874A SE9701874D0 (sv) | 1997-05-21 | 1997-05-21 | AdressjusterbartRAM-minne (eller shiftminne) |
Country Status (2)
Country | Link |
---|---|
SE (1) | SE9701874D0 (sv) |
WO (1) | WO1998056005A2 (sv) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3744285B2 (ja) | 1999-10-29 | 2006-02-08 | 日本電気株式会社 | シフトレジスタ及びその制御方法 |
IL136297A0 (en) * | 2000-05-22 | 2001-05-20 | Hywire Ltd | The implementation of a content addressable memory using a ram-cell structure |
JP3765273B2 (ja) | 2002-02-06 | 2006-04-12 | 日本電気株式会社 | シフトレジスタ |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3893088A (en) * | 1971-07-19 | 1975-07-01 | Texas Instruments Inc | Random access memory shift register system |
DE3303380C2 (de) * | 1983-02-02 | 1984-11-22 | Johannes Dipl.-Ing. Brauer | Halbleiterspeicher |
EP0166577A3 (en) * | 1984-06-21 | 1987-10-14 | Advanced Micro Devices, Inc. | Information sorting and storage apparatus and method |
US4813015A (en) * | 1986-03-12 | 1989-03-14 | Advanced Micro Devices, Inc. | Fracturable x-y storage array using a ram cell with bidirectional shift |
-
1997
- 1997-05-21 SE SE9701874A patent/SE9701874D0/sv unknown
-
1998
- 1998-06-03 WO PCT/SE1998/001054 patent/WO1998056005A2/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO1998056005A2 (en) | 1998-12-10 |
WO1998056005A3 (en) | 1999-03-11 |
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