SE9401813D0 - phase aligner - Google Patents

phase aligner

Info

Publication number
SE9401813D0
SE9401813D0 SE9401813A SE9401813A SE9401813D0 SE 9401813 D0 SE9401813 D0 SE 9401813D0 SE 9401813 A SE9401813 A SE 9401813A SE 9401813 A SE9401813 A SE 9401813A SE 9401813 D0 SE9401813 D0 SE 9401813D0
Authority
SE
Sweden
Prior art keywords
edge
inverter
pulse
restores
bit stream
Prior art date
Application number
SE9401813A
Other languages
Swedish (sv)
Other versions
SE9401813L (en
SE502106C2 (en
Inventor
Tord Haulin
Per Segerbaeck
Heinz Maeder
Original Assignee
Ellemtel Utvecklings Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from SE9300679A external-priority patent/SE9300679L/en
Application filed by Ellemtel Utvecklings Ab filed Critical Ellemtel Utvecklings Ab
Priority to SE9401813A priority Critical patent/SE502106C2/en
Publication of SE9401813D0 publication Critical patent/SE9401813D0/en
Publication of SE9401813L publication Critical patent/SE9401813L/en
Publication of SE502106C2 publication Critical patent/SE502106C2/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

The differential delay element includes a pair of inverters. One inverter delays the first or second edge of an individual pulse in a data bit stream. The second inverter restores the second or first edge of the pulse to maintain the pulse width of information in the data bit stream. - Preferably, the delay element has a controllable delay for positive and negative pulse edges. Each inverter acts as a level restoring stage which restores an influenced and delayed edge to a correct logic level. The cascade coupled inverters are constructed symmetrically to ensure that pulses are of equal length.
SE9401813A 1993-03-01 1994-05-26 Differential delay element for phase aligner in telecommunications - changes ramp edge to full logic level as soon as threshold is reached in feedback route SE502106C2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SE9401813A SE502106C2 (en) 1993-03-01 1994-05-26 Differential delay element for phase aligner in telecommunications - changes ramp edge to full logic level as soon as threshold is reached in feedback route

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9300679A SE9300679L (en) 1993-03-01 1993-03-01 bit synchronizer
SE9401813A SE502106C2 (en) 1993-03-01 1994-05-26 Differential delay element for phase aligner in telecommunications - changes ramp edge to full logic level as soon as threshold is reached in feedback route

Publications (3)

Publication Number Publication Date
SE9401813D0 true SE9401813D0 (en) 1994-05-26
SE9401813L SE9401813L (en) 1994-09-02
SE502106C2 SE502106C2 (en) 1995-08-21

Family

ID=26661668

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9401813A SE502106C2 (en) 1993-03-01 1994-05-26 Differential delay element for phase aligner in telecommunications - changes ramp edge to full logic level as soon as threshold is reached in feedback route

Country Status (1)

Country Link
SE (1) SE502106C2 (en)

Also Published As

Publication number Publication date
SE9401813L (en) 1994-09-02
SE502106C2 (en) 1995-08-21

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Legal Events

Date Code Title Description
NUG Patent has lapsed