SE8100697L - DEVICE FOR CONTROL OF THE OPERATION OF ONE COUPLE OF COMPUTERS, WHICH ONE WORKS AS ACTIVE RESERVE FOR THE OTHER - Google Patents

DEVICE FOR CONTROL OF THE OPERATION OF ONE COUPLE OF COMPUTERS, WHICH ONE WORKS AS ACTIVE RESERVE FOR THE OTHER

Info

Publication number
SE8100697L
SE8100697L SE8100697A SE8100697A SE8100697L SE 8100697 L SE8100697 L SE 8100697L SE 8100697 A SE8100697 A SE 8100697A SE 8100697 A SE8100697 A SE 8100697A SE 8100697 L SE8100697 L SE 8100697L
Authority
SE
Sweden
Prior art keywords
messages
control
processors
couple
computers
Prior art date
Application number
SE8100697A
Other languages
Swedish (sv)
Inventor
Bellis V De
G Donzellor
Original Assignee
Italtel Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Italtel Spa filed Critical Italtel Spa
Publication of SE8100697L publication Critical patent/SE8100697L/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2025—Failover techniques using centralised failover control functionality
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/54558—Redundancy, stand-by
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2028—Failover techniques eliminating a faulty processor or activating a spare
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2033—Failover techniques switching over of hardware resources
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2097—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

An apparatus DC is provided for detecting malfunctioning of a pair of duplicated processors arranged to control systems for which an especially high degree of reliability is required, such as telephone exchanges. The programme for the two processors comprises control messages which are sent on respective input-output channels in accordance with predetermined modes of operation. The apparatus is designed to detect incorrect operation of the two processors by examining the messages generated by them. More particularly, failure to generate such messages, incorrect sequences of such messages, or sending of non- programmed messages by one processor results in it being excluded from the control process, which is then committed to the other processor.
SE8100697A 1980-02-11 1981-01-30 DEVICE FOR CONTROL OF THE OPERATION OF ONE COUPLE OF COMPUTERS, WHICH ONE WORKS AS ACTIVE RESERVE FOR THE OTHER SE8100697L (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8019830A IT1209187B (en) 1980-02-11 1980-02-11 CONTROL DEVICE FOR THE CORRECT OPERATION OF A COUPLE OF PROCESSORS OPERATING ONE AS THE HOT RESERVE OF THE OTHER.

Publications (1)

Publication Number Publication Date
SE8100697L true SE8100697L (en) 1981-08-12

Family

ID=11161634

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8100697A SE8100697L (en) 1980-02-11 1981-01-30 DEVICE FOR CONTROL OF THE OPERATION OF ONE COUPLE OF COMPUTERS, WHICH ONE WORKS AS ACTIVE RESERVE FOR THE OTHER

Country Status (9)

Country Link
BR (1) BR8100763A (en)
DE (1) DE3104927A1 (en)
ES (1) ES500046A0 (en)
FR (1) FR2475762A1 (en)
GB (1) GB2070391A (en)
IE (1) IE810252L (en)
IT (1) IT1209187B (en)
PT (1) PT72489B (en)
SE (1) SE8100697L (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1133349B (en) * 1980-10-07 1986-07-09 Italtel Spa PERFECT TRANSIT NETWORK FOR TIME DIVISION TELECOMMUNICATIONS SYSTEMS
JPS6061850A (en) * 1983-09-12 1985-04-09 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Computer system
DE3334765A1 (en) * 1983-09-26 1985-04-11 Siemens AG, 1000 Berlin und 8000 München TEST DEVICE FOR DETECTING ERRORS IN DOUBLE CIRCUITS, IN PARTICULAR PROCESSORS OF A TELEPHONE SWITCHING SYSTEM
DE4241319A1 (en) * 1992-12-09 1994-06-16 Ant Nachrichtentech Computer system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2319456A1 (en) * 1973-04-17 1974-10-31 Siemens Ag ARRANGEMENT, IN PARTICULAR TELEPHONE SWITCHING SYSTEM, WITH TWO PROGRAM-CONTROLLED REAL-TIME DATA PROCESSING SYSTEMS
IT1036311B (en) * 1975-06-17 1979-10-30 Cselt Centro Studi Lab Telecom DUPLICATE SYSTEM FOR SUPERVISION AND CONTROL OF DUPLICATED TELECOMMUNICATION SYSTEMS
FR2352344A1 (en) * 1976-05-18 1977-12-16 Labo Cent Telecommunicat DEVICE AND METHOD FOR FACILITATING THE MAINTENANCE AND / OR DIAGNOSIS OF MULTICALCULATOR SYSTEMS
DE2647137C2 (en) * 1976-10-19 1983-11-10 Siemens AG, 1000 Berlin und 8000 München Arrangement of two data processing systems that process the same information
DE2813079C3 (en) * 1978-03-25 1984-08-16 Standard Elektrik Lorenz Ag, 7000 Stuttgart High security multi-computer system

Also Published As

Publication number Publication date
DE3104927A1 (en) 1981-12-24
ES8202224A1 (en) 1982-02-01
PT72489B (en) 1982-03-12
IT1209187B (en) 1989-07-16
IE810252L (en) 1981-08-11
PT72489A (en) 1981-03-01
FR2475762A1 (en) 1981-08-14
BR8100763A (en) 1981-08-25
ES500046A0 (en) 1982-02-01
GB2070391A (en) 1981-09-03
IT8019830A0 (en) 1980-02-11

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